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C
Conv TTL Blocking - Testing
Commit 71db1d42 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Merge remote-tracking branch 'origin/ml-dev' into denia-dev

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fm/doc/hdlg/cern-title.tex
View file @ 71db1d42
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm} \noindent \rule{\textwidth}{.1cm}
\hfill December 11, 2014 \hfill October 26, 2017
\vspace*{3cm} \vspace*{3cm}
......
fm/doc/hdlg/clk_info.tex
View file @ 71db1d42
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
Base address (125-MHz counter): 0x100 \\ Base address (125-MHz counter): 0x100 \\
Base address (20-MHz counter): 0x120 Base address (20-MHz counter): 0x120
{ {
\rowcolors{2}{white}{gray!25} \rowcolors{2}{white}{RoyalPurple!25}
\begin{longtable}{l l l p{.5\textwidth}} \begin{longtable}{l l l p{.5\textwidth}}
\hline \hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name} \textbf{Offset} & \textbf{Reset} & \textbf{Name}
...@@ -51,7 +51,7 @@ reserved registers is undefined ...@@ -51,7 +51,7 @@ reserved registers is undefined
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\ \multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}FULL}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -78,19 +78,19 @@ FULL ...@@ -78,19 +78,19 @@ FULL
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[31:24]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -116,19 +116,19 @@ When this value is reached, the counter will stop and needs to be reset via the ...@@ -116,19 +116,19 @@ When this value is reached, the counter will stop and needs to be reset via the
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[31:24]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -165,7 +165,7 @@ CNTVAL ...@@ -165,7 +165,7 @@ CNTVAL
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTRST}\\ \multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CNTRST}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -204,7 +204,7 @@ CNTRST ...@@ -204,7 +204,7 @@ CNTRST
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTEN}\\ \multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CNTEN}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -231,19 +231,19 @@ CNTEN ...@@ -231,19 +231,19 @@ CNTEN
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[31:24]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
......
fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
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...@@ -73,6 +73,7 @@ work, see \\ ...@@ -73,6 +73,7 @@ work, see \\
11-12-2014 & 1.0 & Updated document according to converter board documentation template, added licensing 11-12-2014 & 1.0 & Updated document according to converter board documentation template, added licensing
information, updated information according to changes in HDL, added memory map information, updated information according to changes in HDL, added memory map
as appendix, removed redundant information \\ as appendix, removed redundant information \\
26-10-2017 & 1.1 & Added Test hwvertest and updated wishbone regsiter maps\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -183,6 +184,21 @@ for the gateware in Appendix~\ref{app:memmap}. ...@@ -183,6 +184,21 @@ for the gateware in Appendix~\ref{app:memmap}.
\section{Test logic} \section{Test logic}
\label{sec:test-logic} \label{sec:test-logic}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 01
%--------------------------------------------------------------------------------------
\subsection{Test hwvertest -- PCB version test}
The PTS software verifies whether the version of the PCB is the one expected to
be tested with this PTS. Each PTS is prepared for a particular version of PCB
and it cannot be used to test other version of hardware.
The test reads the PCB version provided in an HWVERS register (see Annex~\ref{app:pts-regs-csr}).
If the provided version is different than the expected version, no further tests is
run and PTS is stopped.
\textbf{This test is a prerequisite to run all the other tests.}
%-------------------------------------------------------------------------------------- %--------------------------------------------------------------------------------------
% SUBSEC: Test 01 % SUBSEC: Test 01
%-------------------------------------------------------------------------------------- %--------------------------------------------------------------------------------------
......
fm/doc/hdlg/pts_regs.tex
View file @ 71db1d42
\subsection{PTS control and status registers} \subsection{PTS control and status registers}
\label{app:pts-regs} \label{app:pts-regs-csr}
Base address: 0x000 \subsubsection{Memory map summary}
{ \rowcolors{2}{gray!25}{white}
\rowcolors{2}{white}{gray!25} \resizebox{\textwidth}{!}{
\begin{longtable}{l l l p{.5\textwidth}} \begin{tabular}{|l|l|l|l|l|}
\hline \rowcolor{RoyalPurple}
\textbf{Offset} & \textbf{Reset} & \textbf{Name} \color{white} SW Offset & \color{white} Type & \color{white} Name &
& \textbf{Description} \\ \color{white} HW prefix & \color{white} C prefix\\
\hline 0x0& REG & BIDR & pts\_bidr & BIDR\\
\endfirsthead 0x4& REG & CSR & pts\_csr & CSR\\
\hline 0x8& REG & LSR & pts\_lsr & LSR\\
\hline
\endhead
\hline \hline
\endfoot \end{tabular}
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & CSR & Control and Status Register\\
0x8 & (2) & LSR & Line Status Register\\
\end{longtable}
} }
\noindent Note (1): The reset value of the status bits in the CSR cannot be specified, since it is based on the \subsubsection{Register description}
the state of the on-board switches and whether an RTM is plugged in or not. Control bits in the CSR default to 0. \paragraph*{BIDR}\vspace{12pt}
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable \rowcolors{1}{white}{white}
is plugged into the channel or not. \begin{tabular}{l l }
{\bf HW prefix:} & pts\_bidr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & BIDR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\subsubsection{BIDR -- Board ID Register} \vspace{12pt}
\label{app:pts-regs-bidr} Board ID Register
\vspace{11pt} \vspace{12pt}
\noindent \noindent
\resizebox{\textwidth}{!}{ \resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -58,36 +57,40 @@ is plugged into the channel or not. ...@@ -58,36 +57,40 @@ is plugged into the channel or not.
{\bf {\bf
BIDR BIDR
} [\emph{read-only}]: ID register bits } [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\paragraph*{CSR}\vspace{12pt}
\subsubsection{CSR -- Control and Status Register} \rowcolors{1}{white}{white}
\label{app:pts-regs-csr} \begin{tabular}{l l }
{\bf HW prefix:} & pts\_csr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & CSR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{11pt} \vspace{12pt}
Control and Status Register
\vspace{12pt}
\noindent \noindent
\resizebox{\textwidth}{!}{ \resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\ \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}RTM[5:0]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCH[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCH[7:0]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & - & - & - & - & - & \multicolumn{1}{c|}{-}\\ \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[5:0]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CHLEDT}\\ \multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CHLEDT}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -130,6 +133,13 @@ REARPT ...@@ -130,6 +133,13 @@ REARPT
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
HWVERS
} [\emph{read-only}]: PCB version number
\\
6 bits representing HW/PCB version number \\ 4 MSB represent HW version number \\ 2 LSB represent number of execution \\ Eg: value 010010 represents PCB version 4.2
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit } [\emph{read/write}]: Reset unlock bit
\\ \\
...@@ -170,15 +180,21 @@ I2C\_WDTO ...@@ -170,15 +180,21 @@ I2C\_WDTO
\\ \\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it 1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small} \end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize} \end{itemize}
\vspace{11pt} \paragraph*{LSR}\vspace{12pt}
\subsubsection{LSR -- Line Status Register}
\label{app:pts-regs-lsr} \rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_lsr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & LSR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{11pt} \vspace{12pt}
Line Status Register
\vspace{12pt}
\noindent \noindent
\resizebox{\textwidth}{!}{ \resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
...@@ -192,11 +208,11 @@ I2C\_WDTO ...@@ -192,11 +208,11 @@ I2C\_WDTO
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\ \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[3:2]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\ \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONT[5:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -223,9 +239,6 @@ REAR ...@@ -223,9 +239,6 @@ REAR
\\ \\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc. Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small} \end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize} \end{itemize}
......
fm/doc/hdlg/pulse_cnt_wb.tex
View file @ 71db1d42
This diff is collapsed.
fm/pts/Makefile
View file @ 71db1d42
...@@ -20,6 +20,7 @@ all: ...@@ -20,6 +20,7 @@ all:
cp ubuntu/$(BOARD)/pyts/pts.py ubuntu/$(BOARD)/pts cp ubuntu/$(BOARD)/pyts/pts.py ubuntu/$(BOARD)/pts
cp ubuntu/$(BOARD)/pyts/jpts.py ubuntu/$(BOARD)/jpts cp ubuntu/$(BOARD)/pyts/jpts.py ubuntu/$(BOARD)/jpts
cp ubuntu/$(BOARD)/pyts/one.py ubuntu/$(BOARD)/one cp ubuntu/$(BOARD)/pyts/one.py ubuntu/$(BOARD)/one
ln -s pyts/hwvertest.py ubuntu/$(BOARD)/hwvertest.py
ln -s pyts/dac_vcxo_pll.py ubuntu/$(BOARD)/test01.py ln -s pyts/dac_vcxo_pll.py ubuntu/$(BOARD)/test01.py
ln -s pyts/leds.py ubuntu/$(BOARD)/test02.py ln -s pyts/leds.py ubuntu/$(BOARD)/test02.py
ln -s pyts/ttl_pulse_switch.py ubuntu/$(BOARD)/test03.py ln -s pyts/ttl_pulse_switch.py ubuntu/$(BOARD)/test03.py
...@@ -32,9 +33,11 @@ all: ...@@ -32,9 +33,11 @@ all:
mkdir -p ubuntu/$(BOARD)/boot mkdir -p ubuntu/$(BOARD)/boot
mv ubuntu/$(BOARD)/shell/program ubuntu/$(BOARD)/boot mv ubuntu/$(BOARD)/shell/program ubuntu/$(BOARD)/boot
mv ubuntu/$(BOARD)/shell/flash ubuntu/$(BOARD)/boot mv ubuntu/$(BOARD)/shell/flash ubuntu/$(BOARD)/boot
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3696/pts.bit wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/5468/pts-v4.bit
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3710/flash_load.bit wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3710/flash_load.bit
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3515/golden-v0.2_release-v3.0.bin wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/5257/golden-v0.2_release-v4.0.bin
chmod a+x ubuntu/$(BOARD)/shell/* chmod a+x ubuntu/$(BOARD)/shell/*
chmod a+x ubuntu/$(BOARD)/boot/* chmod a+x ubuntu/$(BOARD)/boot/*
......
fm/pts/python/flashtest.py
View file @ 71db1d42
...@@ -66,10 +66,10 @@ def main(bus,tname,inf,log): ...@@ -66,10 +66,10 @@ def main(bus,tname,inf,log):
""" """
tests : Flash chip IC20 tests : Flash chip IC20
uses : golden-v0.2_release-v3.0.bin and flashtest.py uses : golden-v0.2_release-v4.0.bin and flashtest.py
""" """
GWVERS_RELEASE = 3.0 GWVERS_RELEASE = 4.0
GWVERS_GOLDEN = 0.2 GWVERS_GOLDEN = 0.2
# Set the precision of gateware versions based on the number of digits the # Set the precision of gateware versions based on the number of digits the
......
fm/pts/python/hwvertest.py 0 → 100755
View file @ 71db1d42
##_______________________________________________________________________________________________
##
## CONV-TTL-BLO PTS
##
## CERN,BE/CO-HT
##_______________________________________________________________________________________________
##
##-----------------------------------------------------------------------------------------------
##
## CONV-TTL-BLO pcb version
##
##-----------------------------------------------------------------------------------------------
##
## Description Test whether the version of PCB is the expected one
##
##
## Authors Maciej Lipinski (maciej.lipinski@cern.ch)
## Website http://www.ohwr.org/projects/pts
## Date 17/08/2017
##-----------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
sys.path.append("log/")
import time
import os, errno, re, sys, struct
import os.path
import traceback
import glob
import binascii
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : Hardware version
uses : pts.bit and hwvertest.py
"""
HWVERS = 4.0
pel = PTS_ERROR_LOGGER(inf,log)
try:
# Read PCB version: a 6 bits representing HW/PCB version number
# 4 MSB represent HW version number (major)
# 2 LSB represent number of execution (minor)
# Eg: value 010010 represents PCB version 4.2
hwvers = (bus.vv_read(CSR) & 0x3F00) >> CSR_HWVERS_OFS
maj = int(hwvers >> 2)
min = float(hwvers & 0x03)
min /= 10
hwvers = maj + min
# and now check if appropriate
if (hwvers == HWVERS):
msg = "HW/PCB version correct: %2.1f\n" % (hwvers)
inf.write(msg)
else:
msg = "ERROR: HW/PCBe version (%2.1f) incorrect - expected %2.1f" % (hwvers, HWVERS)
pel.set(msg)
print "-->%s" % msg
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
fm/pts/python/jpts.py
View file @ 71db1d42
...@@ -193,65 +193,99 @@ if __name__ == '__main__': ...@@ -193,65 +193,99 @@ if __name__ == '__main__':
except BusWarning, e: except BusWarning, e:
print "Warning:Bus Exception: %s" % (e) print "Warning:Bus Exception: %s" % (e)
# Start running the tests. # Test version of HW/PCB before running any other tests
for t in tns: tname = "hwvertest"
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-BLO board in slot %d\n" % (lun)
inf.write(msg + '\n')
# The test is passed the test name, the log and info files and the
# bus object. The test program returns the number of errors that
# occured. If no errors occur, the test PASSes, otherwise it FAILs.
cc = run_test(tname,bus,inf,log)
if cc == 0:
msg = "PASS: %s" % (tname)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
else:
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname))
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
tname = "test%02d" % t[0] except Exception, e:
pyt = "%s/%s.py" % (dir, tname) if options.debug:
print e
traceback.print_exc()
if path.exists(pyt) and path.isfile(pyt) and access(pyt, R_OK): msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
for n in range(t[1]): # Start running the tests, only if the HW/PCB version is OK
if cc == 0:
for t in tns:
if n == 10: tname = "test%02d" % t[0]
msg = "Printing suppresses after 10 runs" pyt = "%s/%s.py" % (dir, tname)
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
if n < 10: if path.exists(pyt) and path.isfile(pyt) and access(pyt, R_OK):
msg = "Run:%d Begin:%s" % (n+1,tname)
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
try: for n in range(t[1]):
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-BLO board in slot %d\n" % (lun)
inf.write(msg + '\n')
# Each test is passed the test name, the log and info files and the if n == 10:
# bus object. The test program is expected to return the number of msg = "Printing suppresses after 10 runs"
# errors that occured. If no errors occur, the test PASSes, otherwise print msg
# it FAILs. log.write('\n' + msg + '\n')
cc = run_test(tname,bus,inf,log) inf.write('\n' + msg + '\n')
if cc == 0:
msg = "PASS: %s" % (tname) if n < 10:
log.write(msg + '\n') msg = "Run:%d Begin:%s" % (n+1,tname)
inf.write(msg + '\n')
print msg print msg
else: log.write('\n' + msg + '\n')
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname)) inf.write('\n' + msg + '\n')
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-BLO board in slot %d\n" % (lun)
inf.write(msg + '\n')
# Each test is passed the test name, the log and info files and the
# bus object. The test program is expected to return the number of
# errors that occured. If no errors occur, the test PASSes, otherwise
# it FAILs.
cc = run_test(tname,bus,inf,log)
if cc == 0:
msg = "PASS: %s" % (tname)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
else:
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname))
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
except Exception, e:
if options.debug:
print e
traceback.print_exc()
msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n') log.write(msg + '\n')
inf.write(msg + '\n') inf.write(msg + '\n')
print msg print msg
except Exception, e: if n < 10:
if options.debug: msg = "Run:%d End:%s\n" % (n+1,tname)
print e print msg
traceback.print_exc() log.write(msg + '\n')
inf.write(msg + '\n')
msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
if n < 10:
msg = "Run:%d End:%s\n" % (n+1,tname)
print msg
log.write(msg + '\n')
inf.write(msg + '\n')
# Close the bus and the files # Close the bus and the files
bus.vv_close() bus.vv_close()
......
fm/pts/python/ptsdefine.py
View file @ 71db1d42
...@@ -58,10 +58,7 @@ CSR_STLEDT_OFS = 1 ...@@ -58,10 +58,7 @@ CSR_STLEDT_OFS = 1
CSR_RLEDT_OFS = 2 CSR_RLEDT_OFS = 2
CSR_TTLPT_OFS = 3 CSR_TTLPT_OFS = 3
CSR_REARPT_OFS = 4 CSR_REARPT_OFS = 4
CSR_TSTCVCC_OFS = 5 CSR_HWVERS_OFS = 8
CSR_TSTCMUXEN_OFS = 6
CSR_TSTCS0_OFS = 7
CSR_TSTCS1_OFS = 8
CSR_RST_UNLOCK_OFS = 14 CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15 CSR_RST_OFS = 15
CSR_SWITCH_OFS = 16 CSR_SWITCH_OFS = 16
...@@ -74,7 +71,7 @@ LSR = 0x008 ...@@ -74,7 +71,7 @@ LSR = 0x008
LSR_FRONT_OFS = 0 LSR_FRONT_OFS = 0
LSR_FRONTINV_OFS = 6 LSR_FRONTINV_OFS = 6
LSR_REAR_OFS = 10 LSR_REAR_OFS = 10
LSR_REARFS_OFS = 26
# 1-Wire base address, used in therm_id.py # 1-Wire base address, used in therm_id.py
TEMP_1WIRE_BASE = 0x010 TEMP_1WIRE_BASE = 0x010
......
fm/pts/shell/flash
View file @ 71db1d42
#!/bin/bash #!/bin/bash
xc3sprog -c xpc flash_load.bit xc3sprog -c xpc flash_load.bit
xc3sprog -c xpc -I golden-v0.2_release-v3.0.bin:w:0:bin xc3sprog -c xpc -I golden-v0.2_release-v4.0.bin:w:0:bin
fm/pts/shell/program
View file @ 71db1d42
#!/bin/bash #!/bin/bash
xc3sprog -c xpc pts.bit xc3sprog -c xpc pts-v4.bit
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