[DOC] updated register maps in the gateware guide

- regenerated from *.wb map of PTS control and status regs because this one changed - regenerated from *.wb map of Pulse counter regs, just in case - I could not find *.wb file for the Clock coutner regs, so I just changed the color of the colums to match the newly-generated files

[DOC] updated register maps in the gateware guide
- regenerated from *.wb map of PTS control and status regs because this one changed - regenerated from *.wb map of Pulse counter regs, just in case - I could not find *.wb file for the Clock coutner regs, so I just changed the color of the colums to match the newly-generated files
a5f734f7 · Maciej Lipinski · c2059237 · a5f734f7 · a5f734f7 · a5f734f7
Commit a5f734f7 authored Oct 26, 2017 by Maciej Lipinski
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clk_info.tex fm/doc/hdlg/clk_info.tex +16 -16

pts_regs.tex fm/doc/hdlg/pts_regs.tex +66 -53

pulse_cnt_wb.tex fm/doc/hdlg/pulse_cnt_wb.tex +588 -370

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--- a/fm/doc/hdlg/clk_info.tex
+++ b/fm/doc/hdlg/clk_info.tex
@@ -4,7 +4,7 @@
 Base address (125-MHz counter): 0x100 \\
 Base address (20-MHz counter): 0x120
 {
-\rowcolors{2}{white}{gray!25}
+\rowcolors{2}{white}{RoyalPurple!25}
 \begin{longtable}{l l l p{.5\textwidth}}
 \hline
 \textbf{Offset} & \textbf{Reset} & \textbf{Name} 
@@ -51,7 +51,7 @@ reserved registers is undefined
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}FULL}\\
 \hline
 \end{tabular}
 }
@@ -78,19 +78,19 @@ FULL
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTMAX[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -116,19 +116,19 @@ When this value is reached, the counter will stop and needs to be reset via the
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTVAL[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -165,7 +165,7 @@ CNTVAL
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTRST}\\
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CNTRST}\\
 \hline
 \end{tabular}
 }
@@ -204,7 +204,7 @@ CNTRST
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTEN}\\
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CNTEN}\\
 \hline
 \end{tabular}
 }
@@ -231,19 +231,19 @@ CNTEN
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CNTCHK[7:0]}\\
 \hline
 \end{tabular}
 }

--- a/fm/doc/hdlg/pts_regs.tex
+++ b/fm/doc/hdlg/pts_regs.tex
 \subsection{PTS control and status registers}
-\label{app:pts-regs}
+\label{app:pts-regs-csr}
-Base address: 0x000
+\subsubsection{Memory map summary}
-{
+\rowcolors{2}{gray!25}{white}
-\rowcolors{2}{white}{gray!25}
+\resizebox{\textwidth}{!}{
-\begin{longtable}{l l l p{.5\textwidth}}
+\begin{tabular}{|l|l|l|l|l|}
-\hline
+\rowcolor{RoyalPurple}
-\textbf{Offset} & \textbf{Reset} & \textbf{Name} 
+\color{white} SW Offset & \color{white} Type & \color{white} Name &
-		& \textbf{Description} \\
+\color{white} HW prefix & \color{white} C prefix\\
-\hline
+0x0& REG & BIDR & pts\_bidr & BIDR\\
-\endfirsthead
+0x4& REG & CSR & pts\_csr & CSR\\
-\hline
+0x8& REG & LSR & pts\_lsr & LSR\\
-\hline
-\endhead
 \hline
-\endfoot
+\end{tabular}
-0x0 & 0x54424c4f & BIDR & Board ID Register\\
-0x4 & (1) & CSR & Control and Status Register\\
-0x8 & (2) & LSR & Line Status Register\\
-\end{longtable}
 }
-\noindent Note (1): The reset value of the status bits in the CSR cannot be specified, since it is based on the
+\subsubsection{Register description}
-the state of the on-board switches and whether an RTM is plugged in or not. Control bits in the CSR default to 0.
+\paragraph*{BIDR}\vspace{12pt}
-\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
+\rowcolors{1}{white}{white}
-is plugged into the channel or not.
+\begin{tabular}{l l }
+{\bf HW prefix:}  & pts\_bidr\\
+{\bf HW address:}  & 0x0\\
+{\bf SW prefix:}  & BIDR\\
+{\bf SW offset:}  & 0x0\\
+\end{tabular}
-\subsubsection{BIDR -- Board ID Register}
+\vspace{12pt}
-\label{app:pts-regs-bidr}
+Board ID Register
-\vspace{11pt}
+\vspace{12pt}
 \noindent
 \resizebox{\textwidth}{!}{
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[31:24]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[23:16]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[15:8]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[7:0]}\\
 \hline
 \end{tabular}
 }
@@ -58,36 +57,40 @@ is plugged into the channel or not.
 {\bf 
 BIDR
 } [\emph{read-only}]: ID register bits
-\\
-Reset value: 0x54424c4f
-\end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
 \end{small}
 \end{itemize}
+\paragraph*{CSR}\vspace{12pt}
-\subsubsection{CSR -- Control and Status Register}
+\rowcolors{1}{white}{white}
-\label{app:pts-regs-csr}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & pts\_csr\\
+{\bf HW address:}  & 0x1\\
+{\bf SW prefix:}  & CSR\\
+{\bf SW offset:}  & 0x4\\
+\end{tabular}
-\vspace{11pt}
+\vspace{12pt}
+Control and Status Register
+\vspace{12pt}
 \noindent
 \resizebox{\textwidth}{!}{
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}RTM[5:0]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCH[7:0]}\\
+\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCH[7:0]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[5:0]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CHLEDT}\\
+\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CHLEDT}\\
 \hline
 \end{tabular}
 }
@@ -130,6 +133,13 @@ REARPT
 \end{small}
 \item \begin{small}
 {\bf 
+HWVERS
+} [\emph{read-only}]: PCB version number
+\\
+6 bits representing HW/PCB version number \\                     4 MSB represent HW version number \\                     2 LSB represent number of execution \\                      Eg: value 010010 represents PCB version 4.2
+\end{small}
+\item \begin{small}
+{\bf 
 RST\_UNLOCK
 } [\emph{read/write}]: Reset unlock bit
 \\
@@ -170,15 +180,21 @@ I2C\_WDTO
 \\
 1 -- timeout occured \\                     0 -- no timeout \\                     This bit can be cleared by writing a '1' to it
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}
-\vspace{11pt}
+\paragraph*{LSR}\vspace{12pt}
-\subsubsection{LSR -- Line Status Register}
-\label{app:pts-regs-lsr}
+\rowcolors{1}{white}{white}
+\begin{tabular}{l l }
+{\bf HW prefix:}  & pts\_lsr\\
+{\bf HW address:}  & 0x2\\
+{\bf SW prefix:}  & LSR\\
+{\bf SW offset:}  & 0x8\\
+\end{tabular}
-\vspace{11pt}
+\vspace{12pt}
+Line Status Register
+\vspace{12pt}
 \noindent
 \resizebox{\textwidth}{!}{
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
@@ -192,11 +208,11 @@ I2C\_WDTO
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
-\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
+\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[3:2]}\\
 \hline
 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
 \hline
-\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
+\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONT[5:0]}\\
 \hline
 \end{tabular}
 }
@@ -223,9 +239,6 @@ REAR
 \\
 Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
 \end{small}
-\item \begin{small}
-\textbf{Unimplemented bits}: write as '0', read undefined
-\end{small}
 \end{itemize}

--- a/fm/doc/hdlg/pulse_cnt_wb.tex
+++ b/fm/doc/hdlg/pulse_cnt_wb.tex