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\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\title{\textbf{{\LARGE Input connection for the Standard Blocking
Repeater: CTARA and CTDAH}}}
\date{\today}

\begin{document}

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\maketitle{}
\pagebreak 

\pagebreak
{\Large \textbf{History of changes}}\\

This document version has been checked by:\\

This document version has been approved by:\\
\begin{center}
\begin{tabular}{|p{3.5cm}|p{2.5cm}|p{5cm}|}
\hline
\textbf{Date} & \textbf{Pages} & \textbf{Changes}\\ 
\hline
\hline
 August 29, 2011 & All & Initial submission\\
\hline
September 21, 2011 & All & Added references to Standard Blocking\\
\hline
September 23, 2011 & All & Modified chapter 1\\
\hline
\end{tabular}
\end{center}


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\paragraph{System Description and Purpose}
This brief document describes the reflection problem when an input signal is
passed to the Standard Blocking Repeater formed by CTARA and CTADH VME64x
boards. Reflections must be carefully studied when the input signal is
daisy-chained so as to avoid signal degradation.

\pagebreak
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\tableofcontents
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\section{Input connection}
One of the desired functionalities of the Standard Blocking Repeater formed by 
CTARA and CTDAH boards is loopbacking the input signal between two o more
channels. When a signal is daisy-chained special care must be taken to have
control on the reflections that are happening in the input. For instance, in old
8 and 16 Channel Repeaters the picture is as follows:

\begin{figure}[htb]
    \begin{center}
      \includegraphics[scale=1, keepaspectratio]{notBypassed.png}
      \caption{Daisy-chain in old Channel Repeaters}
    \end{center}
\end{figure}
it can be seen that every channel that bypasses the signal represents a stub
that produces reflections.

\subsection{Line termination}
The main issue affecting the integrity of the bypassed signal is reflection.
Reflections should be taking into account when transmission line theory can be
applied to a circuit. As stated in \cite{johnson1993high} or
\cite{bogatin2009signal} a line should be better considered as a transmission
line when the electrical distance of the cable -or trace- is higher than one
sixth of its electrical distance:
\begin{equation}
L_{trace} \geq \frac{L_{electrical}}{6} = \frac{v_{prop} t_{rise}}{6}
\end{equation}
In our design, the three input signals that can be applied with its relevant
reflections parameters are shown below:
\begin{center}
\begin{tabular}{|c|c|c|}
    \hline
     & t$_{rise}$ & L$_{electrical_{threshold}}$\\
    \hline
    TTL & 5 ns & 16.6 cm\\
    \hline
    TTL/bar & 5 ns & 16.6 cm\\
    \hline
    Standard Blocking & 150 ns & 5 m\\
    \hline
    \end{tabular}
\end{center}

Even in the best electrical lenght case -which corresponds to Standard
Blocking \cite{StandardBlocking}-, it is necessary to apply a transmission line
approach. Hence, properly termination of lines is highly
recommended so as to avoid reflections.

\pagebreak
\section{Standard Blocking Repeater Daisy-Chain Configurations}
The image below shows the conversion path of the pulse input to the Standard
Blocking output.

\begin{figure}[htb]
    \begin{center}
      \includegraphics[scale=1, keepaspectratio]{StBlocking.png}
      \caption{Pulse conversion schema}
    \end{center}
\end{figure}

An input signal is received in the FPGA after conditioning. Then a control
signal is generated in the FPGA to the Pulse Converter Unit, which will output a
Standard Blocking compliant pulse. Thus, as the generation of the pulse depends
either on the input signal or the input control, two daisy-chain strategies
are:
\begin{itemize}
  \item \textbf{Copying input signal: FPGA not bypassed}
  \item \textbf{Copying control signal: FPGA bypassed}
\end{itemize}
The table summarizes the properties of every layout:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
Stubs & Daisy-chain signal& Channel interconnection & Added\\
\hline
\hline
\multicolumn{4}{|c|}{\textbf{FPGA not bypassed}}\\
\hline
YES & Input signal & Any order & -\\
\hline
\hline
\multicolumn{4}{|c|}{\textbf{FPGA bypassed}}\\
\hline
\multicolumn{4}{|c|}{\textit{Option A}}\\
\hline
NO & Control signal & Any order & Less reflections\\
& & & FPGA control\\
\hline
\multicolumn{4}{|c|}{\textit{Option B}}\\
\hline
& & & Less reflections\\
NO & Control signal & Contiguous & FPGA control\\
& & & Higher channel\\
& & & integration\\
\hline
\end{tabular}
\end{center}
\subsection{Copying input signal}
This was the technique used in 8 and 16 Channel Repeaters. The input pin was
directly connected to the daisy-chain output of the same channel.

\subsubsection{Signal degradation in Channel Repeaters boards}
So as to better understand the effects of this kind of daisy-chaining, a set of
measures where taken in a 16 Channel Repeater board.\\
A Standard Blocking pulse signal was taken from the Pulse Generator
-\textit{boite d'impulsions}-, routed to the 16 Channel Repeater and the signal
was analyzed in a Lecroy WaveJet 324A oscilloscope.\\
The cables used were 50 $\Omega$ cables of different lengths. To connect the
Pulse Generator with the first channel a 16 $ns$ delay cable was used. For the
rest of daisy-chain connections 1 $ns$ delay cables were attached.
Finally, a 6 $ns$ cable is connected to the oscilloscope.

 \textbf{Standard Blocking input}\\
 In this case, bypassing a slow signal, such
 a Standard Blocking, is not affecting dramatically to the signal integrity. In
 the next page two images are attached. The first one shows the output of a 50
 $\Omega$ terminated channel which is not daisy-chained. The second one shows the signal after daisy-chaining six channels
and 50 $\Omega$ termination in the last one.

\begin{figure}
\centering
\mbox{\subfigure{\includegraphics[width=2.33in]{StdBlockingnoDaisy.png}}\quad
\subfigure{\includegraphics[width=2.33in]{StdBlockingDaisyChained6ch.png}
}}
\caption{Standard Blocking input when no daisy-chained -left- and after 6
daisy-chain stages -right-}
\label{fig12}
\end{figure}

As it can be seen for the case of Standard Blocking, the most noticeable effect
is a degradation of the rise time and a expected lower high level.\\


%The input signal is passed through a three-winding transformer, 1:1:1 ratio.
%One of the two outputs is offered to the current channel and the other is
%routed out to the daisy-chain output. The signal that goes to the current
%channel is terminated, magnetically isolated, converter to LVTTL and connected
%%to the FPGA.\\ The daisy-chain output trace should be a 50 $\Omega$ controlled
%trace.\\ Here a more complicated technical problem arises when it comes to
%termination. For instance, when we daisy-chain two channels the terminating
%resistance and controlled trace should be:
%\begin{equation}
%R_{termination} = 2Z_o
%%%\end{equation}
%%\begin{equation}
%%Z_{trace} = 2Z_o
%%\end{equation}
%As the operator can tie up up to six channels, all the correct termination
%duples should be available:
%\begin{equation}
%R_{termination} = nZ_o \hspace{25pt} n \in [1,\ldots 6]
%%\end{equation}
%%%\begin{equation}
%Z_{trace} = nZ_o \hspace{25pt} n \in [1,\ldots 6]
%\end{equation}
%This can be automatically done in a setup process when all the \textit{Rear
%Panel} cables have been connected.

%In the case of $R_{termination}$, the problem can be solved by means of an
%electronically controlled variable resistor. For $Z_{trace}$, six controlled
%impedance traces must be implemented and a trace switcher it is need to select
%one of them. This implementation is \textbf{unfeasible}.
\pagebreak
 \textbf{Fast TTL inputs}\\
 In this case, so as to obtain fast TTL inputs, the signal was taken from
 CTRV board. As the input pulses have a rise time of 5 $ns$, a higher
 degradation of the signal is expected. Experimental results point out that no significant
 difference is observed when the signal is daisy-chained.\\
 
 \underline{No daisy-chained input captures}\\
\begin{figure}[htb]
    \begin{center}
      \includegraphics[scale=0.33, keepaspectratio]{FastTTLnoDaisy.png}
      \caption{Fast TTL when no daisy-chained}
    \end{center}
\end{figure}

\begin{figure}
\centering
\mbox{\subfigure{\includegraphics[width=2.33in]{FastTTLnoDaisyDetailFallEdge.png}}\quad
\subfigure{\includegraphics[width=2.33in]{FastTTLnoDaisyDetailRiseEdge.png}
}}
\caption{No terminated line: Detail of the fall and rise edge}
\label{fig12}
\end{figure}

\begin{figure}
\centering
\mbox{\subfigure{\includegraphics[width=2.33in]{DaisyNoChTerminatedFall.png}}\quad
\subfigure{\includegraphics[width=2.33in]{DaisyNoChTerminatedRise.png}
}}
\caption{$50\Omega$ terminated line: Detail of the fall and rise edge}
\label{fig12}
\end{figure}

\pagebreak
 \underline{6 daisy-chained channels input captures}\\
\begin{figure}[htb]
    \begin{center}
      \includegraphics[scale=0.33,
      keepaspectratio]{FastTTLDaisyChained6ch.png}
      \caption{Fast TTL input after 6 daisy-chain stages}
    \end{center}
\end{figure}

\begin{figure}
\centering
\mbox{\subfigure{\includegraphics[width=2.33in]{FastTTLDaisyChained6chDetailFallEdge.png}}\quad
\subfigure{\includegraphics[width=2.33in]{FastTTLDaisyChained6chDetailRiseEdge.png}
}}
\caption{Detail of the fall and rise edge} \label{fig12}
\end{figure}

\begin{figure}
\centering
\mbox{\subfigure{\includegraphics[width=2.33in]{Daisy6chTerminatedFall.png}}\quad
\subfigure{\includegraphics[width=2.33in]{Daisy6chTerminatedRise.png}
}}
\caption{$50\Omega$ terminated line: Detail of the fall and rise edge}
\label{fig12}
\end{figure}

\pagebreak
\subsection{Copying control signal}
With this different approach, the FPGA internally daisy-chain the control signal
that generates the Standard Blocking pulses. By doing this, the input signal is
never daisy-chained, theoretically improving signal integrity.
Two options are offered as suitable solutions for bypassing control signal
between channels, but the main idea beyond them is the same: detecting the
daisy-chained channels and internally copy the control signal between them.\\

\textbf{Copying control signal improvements over copying input
signal}
\begin{itemize}
  \item \textit{Less reflections}: as no stubs are added to the line for every
  daisy-chained channel, reflection effects are lesser.
  \item \textit{FPGA control}: the daisy-chain topology of a card can be easily
  known by the FPGA. Thanks to this, more complete control techniques can be
  implemented to detect where a failure is happening throught the signal
  repetition path.
\end{itemize}
In \textbf{Option A} there are two connectors used for daisy-chain. One of this
connectors is a daisy-chain input, the other is a daisy-chain output. So as to
enable the daisy-chain operation, the operator must connect one daisy-chain
output of one channel with a daisy-chain input of a different channel. It is not
necessary that the channels are contiguous, thus providing more flexibility to
the operator when it comes to the installation process.\\
\begin{figure}
\begin{center}
      \includegraphics[scale=1, keepaspectratio]{OptionA.png}
      \caption{Daisy-chain: Option A}
    \end{center}
\end{figure}
After the installation, a daisy-chain detection process must be carried
out by the FPGA. Instead of outputting the signal through the daisy-chain
connectors, it is internally loopbacked between the detected daisy-chained
channels. By internally loopbacking, the associated delay is reduced. A
maximum FPGA bypassing delay must be specified.\\
\textbf{Option B} represents a different approach to the same problem. Instead
of having two dedicated daisy-chain connectors, there is a switch in every
channel.  This switch allows loopbacking the signal of the current channel to,
and only to, the next channel.\\ After setting up the switch in the desired
position, the FPGA will detect its state and will proceed -or not- to internally
loopback the signal to the next channel.
\begin{figure}[htb]
\begin{center}
      \includegraphics[scale=1, keepaspectratio]{OptionB.png}
      \caption{Daisy-chain: Option B}
    \end{center}
\end{figure}

\textbf{Option B improvements over Option A}
\begin{itemize}
  \item \textit{Higher channel integration}: due to the fact that less
  connectors are needed to daisy-chain, a higher integration of channel can be
  made in CTARA board.
\end{itemize}

\pagebreak
\bibliographystyle{unsrt}
\bibliography{BlockingInput}
\end{document}
