\contentsline {paragraph}{Acknowledgements}{ii}{section*.1}
\contentsline {paragraph}{System Description and Purpose}{ii}{section*.2}
\contentsline {section}{\numberline {1}General schema}{1}{section.1}
\contentsline {section}{\numberline {2}Panels}{2}{section.2}
\contentsline {subsection}{\numberline {2.1}Front Panel}{2}{subsection.2.1}
\contentsline {subsection}{\numberline {2.2}Rear Panel}{3}{subsection.2.2}
\contentsline {section}{\numberline {3}Power-up and System Monitoring}{4}{section.3}
\contentsline {subsection}{\numberline {3.1}Power Supplies}{4}{subsection.3.1}
\contentsline {subsection}{\numberline {3.2}Board Temperature}{4}{subsection.3.2}
\contentsline {subsection}{\numberline {3.3}Daisy-chain detection}{4}{subsection.3.3}
\contentsline {section}{\numberline {4}FPGA Control and Pulse Converter Unit}{7}{section.4}
\contentsline {subsection}{\numberline {4.1}Board ID}{7}{subsection.4.1}
\contentsline {subsection}{\numberline {4.2}HDL control}{7}{subsection.4.2}
\contentsline {subsection}{\numberline {4.3}Pulse Converter Unit}{8}{subsection.4.3}
\contentsline {subsubsection}{\numberline {4.3.1}Input}{8}{subsubsection.4.3.1}
\contentsline {subsubsection}{\numberline {4.3.2}Output}{8}{subsubsection.4.3.2}
\contentsline {section}{\numberline {5}On board memory and FPGA reprogramming}{9}{section.5}
\contentsline {section}{\numberline {6}Testing methodologies}{10}{section.6}
