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\begin{document}
\title{\textbf{CONV-TTL-BLO \\ Multiboot HDL module}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{February 23, 2012}
\maketitle

\begin{abstract}
The \textit{multiboot module} is in charge of configuring multibooting
capability and assert the reprogramming of the FPGA.

This document shows:
\begin{itemize}
  \item Parameters used as \textit{generic}
  \item The registers to control the module.
  \item Step-by-step instructions for proper use.
\end{itemize}
\end{abstract}

\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & Multiboot manager & February 23, 2012\\
\hline
\end{tabular}
\end{center}

\pagebreak

\tableofcontents

\pagebreak

\section{Structure}
\begin{tabular}{|l|}
\hline
\textit{NOTE1:} this module is platform specific. It only works with Spartan
6\\
\hline
\textit{NOTE2:} in case the EEPROM memory is replaced, SPI opcode will\\ change.
User should notice this issue.\\
\hline
\end{tabular}\\

The trigger module contains sever 
blocks related the following way:\\

--  \textbf{\textit{multiboot\_top.vhd}}

----- \textbf{multiboot\_regs.vhd}

----- \textbf{multiboot\_core.vhd}

--------- ICAP\_SPARTAN6 (\textit{Xilinx primitive})


\subsection{\textit{multiboot\_top.vhd}}

The top file of the module. It interconnects the Wishbone to internal register
module, \textit{multiboot\_regs.vhd}, to the core logic in
\textit{multiboot\_core.vhd}.

No \textit{generics} are implemented in this HDL module.

\subsection{multiboot\_regs.vhd}

In this module the registers neeeded for specifiying the memory addresses in
which the FPGA must boot to are defined.

An internal register is defined for selectively controlling operations to be
performed by this module (full ICAP reprogramming process, issuing ICAP
commands, refreshing ICAP registers). The set of operations that can be issued
is restricted for security reasons. The allowed operations are further listed in
the \textit{Register subsection}.

\subsection{multiboot\_core.vhd}

It is responsible of accessing ICAP port through the internal
\textit{ICAP\_SPARTAN6 Xilinx primitive}. A finite state machine is implemented
in accordance to Chapter 7 of \cite{UG380}.

\subsection{Behaviour}

Following the instructions of \cite{UG380} strictly leads to correct multiboot
of the FPGA. Firstly, registers \textit{GENERAL1}, \textit{GENERAL2},
\textit{GENERAL3} and \textit{GENERAL4} must be programmed with valid values. It
should be keept in mind that the \textit{SPI opcode} in \textit{GENERAL4}
register depends on the \textit{EEPROM chip} mounted on the board.\\
Then, a \textit{full multiboot} command must be performed via ICAP interface
through a write in \textit{CTRL} register in \textit{multiboot module}.

\section{Parameters}

No \textit{generic} parameters are offered in this module.

\section{Registers}
\subsection{CTRL}
The \textit{CTRL} register is a read-write register for \textit{OP} field and a
read-only for \textit{PEND} bit.
It specifies the operations that can be controlled by an user.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
3-0 & OP   & OPeration to be performed \\
\hline
4   & PEND & operation PENDing \\
\hline
\end{tabular}\\

Whenever an operation is specified by the user, it is passed to ICAP Xilinx
primitive through \textit{multiboot\_core.vhd} and the bit flag \textit{PEND} is
set to '1' until it is completely finished.

\subsubsection{Operations}

The valid operations that can be requested are the following:\\

\begin{tabular}{| c | l |}
\hline
\textbf{OP byte} & \textbf{Operation}\\
\hline
\hline
0x0 & \textbf{Full multiboot process} as specified in \cite{UG380}\\
 \hline
0x1 & \textbf{Write GENERAL1} register from \\
        & \textit{multiboot\_regs.vhd} into FPGA\\
 \hline
 0x2 & \textbf{Write GENERAL2} register from \\
        & \textit{multiboot\_regs.vhd} into FPGA\\
 \hline
0x3 & \textbf{Write GENERAL3} register from \\
        & \textit{multiboot\_regs.vhd} into FPGA\\
 \hline
0x4 & \textbf{Write GENERAL4} register from \\
        & \textit{multiboot\_regs.vhd} into FPGA\\
 \hline
0x7 & Perform \textbf{IPROG command}\\
 \hline
0xD & \textbf{Refresh STAT} register\\
        & into \textit{multiboot\_regs.vhd} \\
\hline
\end{tabular}\\

Full multiboot process, \textit{OP} = 0x0, comprises commamnds:
\begin{enumerate}
  \item \textit{OP} = 0x1
  \item \textit{OP} = 0x2
  \item \textit{OP} = 0x3
  \item \textit{OP} = 0x4
  \item \textit{OP} = 0x7
\end{enumerate}

\subsection{STAT}

The \textit{STAT} register is a read-only register. A \textit{refresh operation}
should be completed before retrieving correct \textit{STAT} information.\\

\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
 0 & CRC\_ERROR & CRC ERROR detected in bitstream\\
\hline
 1 & ID\_ERROR  & IDCODE not validated\\
\hline
 2 & DCM\_LOCK  & DCMs and PLL are locked \\
\hline
 3 & GTS\_CFG\_B & Global tristate\\
\hline
 4 & GWE & Global Write Enable\\
\hline
 5 & GHIGH\_B & GHIGH\\
\hline
 6 & DEC\_ERROR & DEC\_ERROR\\
\hline
 7 & PART\_SECURED & Decryption is set\\
\hline
 8 & HSWAPEN & HWSAPEN\\
\hline
 11-9 & MODE & MODE pins\\
\hline
 12 & INIT\_B & INIT\_B\\
\hline
 13 & DONE & DONE input pins\\
\hline
 14 & IN\_PWRDWN & suspend status\\
\hline
 15 & SWWD\_STRIKEOUT & config error because of invalid sync\\
\hline
\end{tabular}\\

\subsection{GENERAL1}

Bit scrambling is done in VHDL code. Bit order must be as specified below:\\

\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
15-0 & MBT\_ADDR\_L & MultiBoot image ADDRess Lower half\\
\hline
\end{tabular}\\

\subsection{GENERAL2}

Bit scrambling is done in VHDL code. Bit order must be as specified below:\\

\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
7-0 & MBT\_ADDR\_L & Multiboot image ADDRess Lower Half\\
\hline
15-8 & SPIO & SPI Opcode\\
\hline
\end{tabular}\\

\subsection{GENERAL3}

Bit scrambling is done in VHDL code. Bit order must be as specified below:\\

\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
15-0 & GLD\_ADDR\_L & GolDen image ADDRess Lower half\\
\hline
\end{tabular}\\

\subsection{GENERAL4}

Bit scrambling is done in VHDL code. Bit order must be as specified below:\\

\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
7-0 & GLD\_ADDR\_H & GoLDen image ADDRess Higher Half\\
\hline
15-8 & SPIO & SPI Opcode\\
\hline
\end{tabular}\\

\section{Internal Memory Mapping}

The Internal Memory Mapping is as follows:\\

\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{CTRL} & Read-only\\
\hline
\textbf{0x1} & \textit{STAT} & See \textit{STAT} description\\
\hline
\textbf{0x2} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x3} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x4} & \textit{GENERAL1} & Read-write\\
\hline
\textbf{0x5} & \textit{GENERAL2} & Read-write\\
\hline
\textbf{0x6} & \textit{GENERAL3} & Read-only\\
\hline
\textbf{0x7} & \textit{GENERAL4} & Read-write\\
\hline
\end{tabular}


\section{How to use it}

It requieres three parameters to be specified:

\begin{itemize}
  \item Address of the Golden Image
  \item Address of the Multiboot Image
  \item SPI Opcode of the EEPROM serial interface 
\end{itemize}

Bad specifications of addresses will not reprogram the FPGA.

\subsection{Submitting ICAP instructions}

It can be either a two-step or a single-step process. Two-step processes are
related with changes in \textit{GENERAL[X]} register. Submitting an ICAP
command is a single-step-process (\textit{IPROG} instruction, for instance).

\begin {itemize}
\item[\textbf{Example A:}]\\
\textbf{Full Multiboot Configuration}\\
This is a scenario is useful when the EEPROM memory map has changed for
the allocation of the two FPGA bitstreams.
\begin {enumerate}
  \item Write \textit{GENERAL1} register.
  \item Write \textit{GENERAL2} register.
  \item Write \textit{GENERAL3} register.
  \item Write \textit{GENERAL4} register.
  \item Write \textit{CTRL} register.\\
  \textit{CTRL} should issue a \textbf{Full multiboot process} operation code
  (0x0).
\end {enumerate}
\item[\textbf{Example B:}]\\
\textbf{Change an individual Boot Look Up Address}\\
This is a scenario is useful when the EEPROM memory map has changed for
the allocation of only one of the FPGA bitstreams.
\begin {enumerate}
  \item Write \textit{GENERAL[X]} register. Where X={1,3}
  \item Write \textit{GENERAL[X+1]} register.
  \item Write \textit{CTRL} register.\\
  \textit{CTRL} should issue a \textbf{Write GENERAL[X]} operation code.
  \item Write \textit{CTRL} register.\\
  \textit{CTRL} should issue a \textbf{Write GENERAL[X+1]} operation code.
\end {enumerate}

\item[\textbf{Example C:}]\\
\textbf{Reprogram FPGA without change in Bitstream Location}\\
If the EEPROM memory map has not changed but we want to reload one of the
images, we just issue an \textit{IPROG} instruction through the \textit{ICAP}
interface.
\begin {enumerate}
  \item Write \textit{CTRL} register.\\
  \textit{CTRL} should issue an \textbf{IPROG} operation code(0x7).
\end {enumerate}
\end {itemize}

\pagebreak
\bibliographystyle{unsrt}
\bibliography{multiboot}
\end{document}
