--------------------------------------------------------------------------------
-- Company:       CERN, BE-CO-HT 
-- Engineer:      Carlos Gil Soriano
--
-- Create Date:   12:07:51 10/26/2011
-- Design Name:   i2c slave to wb_master testbench
-- Module Name:   /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name:  CTDAH
-- Target Device: Spartan 6
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: i2c_bit
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
 
ARCHITECTURE behavior OF i2c_bit_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
   component i2c_bit
      port(
         rst_i    : IN  std_logic;
         wb_clk_i : IN  std_logic;
         presc_e  : IN  std_logic;
         presc    : IN  std_logic_vector(15 downto 0);
         done     : OUT  std_logic;
         sda_i    : IN  std_logic;
         scl_i    : IN  std_logic;
         start_o  : OUT  std_logic;
         pause_o  : OUT  std_logic;
         rcved_o  : OUT  std_logic
        );
   end component;
    
   --Inputs
   signal rst_i    : std_logic := '0';
   signal wb_clk_i : std_logic := '0';
   signal presc_e  : std_logic := '0';
   signal presc    : std_logic_vector(15 downto 0) := (others => '0');
   signal sda_i    : std_logic := '0';
   signal scl_i    : std_logic := '0';

 	--Outputs
   signal done     : std_logic;
   signal start_o  : std_logic;
   signal pause_o  : std_logic;
   signal rcved_o  : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   constant wb_clk_i_period : time := 50 ns;    -- @ 20 MHz
   constant scl_i_period    : time := 2500 ns;  -- @ 400 KHz
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: i2c_bit
      PORT MAP (
         rst_i => rst_i,
         wb_clk_i => wb_clk_i,
			presc_e => presc_e,
         presc => presc,
         done => done,
         sda_i => sda_i,
         scl_i => scl_i,
         start_o => start_o,
         pause_o => pause_o,
         rcved_o => rcved_o
      );

--   procedure stop is
--   begin
--   end procedure;
--
--   procedure one is
--   begin
--   end procedure;
--
--   procedure zero is
--   begin
--   end procedure;

   -- Clock process definitions
   wb_clk_i_process :process
   begin
      wb_clk_i  <= '1';
         wait for wb_clk_i_period/2;
      wb_clk_i  <= '0';
         wait for wb_clk_i_period/2;
   end process;

   scl_i_process :process
   begin
      scl_i     <= '1';
         wait for scl_i_period/2;
      scl_i     <= '0';
         wait for scl_i_period/2;
   end process;
 
   -- Stimulus process
   stim_proc: process
      procedure init_cond is
      begin
         sda_i   <= '1';
         scl_i   <= 'Z';
      end init_cond;

      procedure rst is
      begin
            wait for wb_clk_i_period*2;
         rst_i   <= '1';
            wait for wb_clk_i_period*2;
         rst_i   <= '0';
            wait for wb_clk_i_period*2;
      end rst;

      procedure start is
      begin
         sda_i  <= '1';
            wait until rising_edge(scl_i);
            wait for scl_i_period/4;
         sda_i  <= '0';
            wait until falling_edge(scl_i);
            wait for scl_i_period/4;
      end start;

      procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
      begin
         for i in 0 to 6 loop
            sda_i <= addr(i);
               wait for scl_i_period;
         end loop;
      end addr_send;

      procedure pause is 
      begin
         sda_i  <= '0';
            wait until rising_edge(scl_i);
            wait for scl_i_period/4;
         sda_i  <= '1';
            wait until falling_edge(scl_i);
            wait for scl_i_period/4;
      end pause;

   begin		

      init_cond;
      rst;
      start;
      addr_send("0101100");
      pause;
      -- insert stimulus here 

      wait;
   end process;

END;
