-- testbench template 

library IEEE;
use IEEE.STD_LOGIC_1164.ALl;
use IEEE.NUMERIC_STD.ALL;

entity image0_top_tb is
   end image0_top_tb;

architecture Behavior of image0_top_tb is 

   -- component declaration
   component image0_top 
      port(
             rst_i   : in  STD_LOGIC;
             clk_i   : in  STD_LOGIC;
             pulse_i : in  STD_LOGIC_VECTOR(5 downto 0)
             pulse_o : out STD_LOGIC_VECTOR(5 downto 0)
          );
   end component;

   constant wb_clk_period : TIME = 50 ns;

   signal rst_i           : STD_LOGIC;  
   signal clk_i           : STD_LOGIC;  
   signal pulse_i         : STD_LOGIC_VECTOR(5 downto 0); 
   signal pulse_o         : STD_LOGIC_VECTOR(5 downto 0); 


begin

   -- component instantiation
   image0_top_uut: image0_top
   port map(
              rst_i    =>  rst_i  , 
              clk_i    =>  clk_i  ,
              pulse_i  =>  pulse_i,
              pulse_o  =>  pulse_o
           );

   wb_clk_proc: process
   begin
      clk_i <= '1';
        wait for wb_clk_period;
      clk_i <= '0';
        wait for wb_clk_period;
   end process;

   tb_proc: process

      procedure rst_sync(lenght: TIME)
      begin
          wait until rising_edge(clk_i);
        rst_i  <= '1';
          wait for 100000*wb_clk_period; -- 50ms
        rst_i  <= '0';
      end procedure;

      procedure rst_async(t0: TIME; lenght: TIME)
      begin
      end procedure;

      procedure pulse(channel: INTEGER; lenght:TIME)
      begin
           wait until rising_edge(wb_clk_i);
         pulse_i(channel) <= '1';
           wait for lenght;
         pulse_i(channel) <= '0';
      end procedure;

   begin

      rst_sync;


      -------------------------------------------------------------------------
      -- Pulse should be reproduced with a value of 1.5us which equals
      -- 30 wb_ck_period clocks. Then, another pulse_lenght time slot, the
      -- triggers will be forbidden to reproduce pulses for safety reasons.
      -- A default current glitch mask of "111111" (six wb_clk_period, 300 ns)
      -- is set.
      --
      --------------------------------
      -- INPUT PULSES TESTS
      --                           INPUT                 OUTPUT
      -- 1.- Normal operation:      20 wb_clk_period      1 pulse
      -- 2.- Testing antiglitch      5 wb_clk_period      0 pulses
      -- 3.- Testing long pulses    59 wb_clk_period      1 pulse
      --                            60 wb_clk_period      2 pulses?
      --                            61 wb_clk_period      2 pulses
      --------------------------------
      -------------------------------------------------------------------------

      pulse(1, 20 * wb_clk_period);
        wait for 10 * wb_clk_period;
      pulse(1,  5 * wb_clk_period);
        wait for 10 * wb_clk_period;
      pulse(1, 59 * wb_clk_period);
        wait for 10 * wb_clk_period;
      pulse(1, 60 * wb_clk_period);
        wait for 10 * wb_clk_period;
      pulse(1, 61 * wb_clk_period);
        wait for 10 * wb_clk_period;

   end process;

end;
