library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gc_RAM is
  generic(
  g_DATA_WIDTH : INTEGER := 32;
  g_ADDR_WIDTH : INTEGER := 8);
port(
      clka   : in  STD_LOGIC;
      wea    : in  STD_LOGIC;
      addra  : in  STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
      dina   : in  STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
      clkb   : in  STD_LOGIC;
      rstb   : in  STD_LOGIC;
      addrb  : in  STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
      doutb  : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
    );
end gc_RAM;

architecture Behavioural of gc_RAM is

  type ram_type is array(2**g_ADDR_WIDTH - 1  downto 0) of STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);

 signal RAM: ram_type;

begin

  write_proc: process (clka)
  begin
    if rising_edge(clka) then
      if rstb = '1' then
         erase_loop: for i in 0 to 2**g_ADDR_WIDTH - 1 loop
           RAM(i) <= (others => '0');
         end loop erase_loop;
      else
        RAM(conv_integer(addra)) <= dina;
      end if;
    else
    end if; 
  end process;

  read_proc: process (clkb)
  begin
     if rising_edge(clkb) then
       if rstb = '1' then
        doutb <= (others => '0');
      elsif addrb = addra then
        doutb <= dina;
      else
        doutb <= RAM(conv_integer(addrb));
       end if;
    else
    end if; 
 end process;
end Behavioural;
