-------------------------------------------------------------------------------
-- Title      : Clock divider
-- Project    : CTDAH
-------------------------------------------------------------------------------
-- File       : gc_clk_divider.vhd
-- Author     : Carlos Gil Soriano
-- Company    : CERN BE-CO-HT
-- Created    : 15-06-2012
-- Last update: 15-06-2012
-- Platform   : FPGA-generic
-- Standard   : VHDL '93
------------------------------------------------------------------------------
-- Description: Clock divider with output enable feature 
--              It divides to twice the value inputed in divider_i. Hence,
--              even period of clk_i can be outputted.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2012-15-06  1.0      gilsoriano      Created
-------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL;

entity gc_clk_divider is
   generic( g_clk_division_logSize : NATURAL := 8);
   port (
      clk_i      : in  STD_LOGIC;
      rst_i      : in  STD_LOGIC;
      oe_n_i     : in  STD_LOGIC;
      clk_o      : out STD_LOGIC;
      divider_i  : in  STD_LOGIC_VECTOR (g_clk_division_logSize - 1 downto 0) --Divides by twice the value specified
   );
end gc_clk_divider;

architecture Behavioral of gc_clk_divider is

signal s_clk_o      : STD_LOGIC;
signal clk_i_count  : UNSIGNED(g_clk_division_logSize - 1 downto 0);

begin
   clk_o <= s_clk_o;

   p_div: process(clk_i)
   begin
      if rising_edge (clk_i) then
         if rst_i = '1' then
            s_clk_o     <= '0';
--            clk_i_count <= unsigned(divider_i);
            clk_i_count <= to_unsigned(1, g_clk_division_logSize);
         else
            if oe_n_i = '0' then
               clk_i_count <= clk_i_count + 1;
               if clk_i_count = unsigned(divider_i) then
                  s_clk_o     <= not(s_clk_o);
                  clk_i_count <= to_unsigned(1, g_clk_division_logSize);
               else
               end if;
            else
               s_clk_o     <= '0';
            end if;
         end if;
      else
      end if;
   end process;

end Behavioral;
