----------------------------------------------------------------------------------
-- Company:        CERN, BE-CO-HT
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    09:58:06 10/12/2011 
-- Design Name:    HDL trigger top
-- Module Name:    trigger - Behavioral 
-- Project Name:   CTDAH
-- Target Devices: Spartan 6
-- Tool versions: 
-- Description:    This is the wishbone trigger which receives a input
--                 and outputs a trigger signal for the pulse converter.
--                 It internally debounces the inputs and control the output
--                 driver.
--                 The registers it has can be modified via wishbone access.
-- Dependencies:   none
--
-- Revision: 
-- Revision 0.1
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
library work;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.trigger_pkg.ALL;


entity trigger_top is
  port (
         pulse_i    : in   STD_LOGIC;
         pulse_o    : out  STD_LOGIC;

         led_o      : out  STD_LOGIC;

         utc_i      : in   STD_LOGIC_VECTOR(95 downto 0);

         wb_rst_i   : in   STD_LOGIC;		
         wb_clk_i   : in   STD_LOGIC;		
         wb_stb_i   : in   STD_LOGIC;
         wb_cyc_i   : in   STD_LOGIC;
         wb_ack_o   : out  STD_LOGIC;
         wb_err_o   : out  STD_LOGIC;
         wb_rty_o   : out  STD_LOGIC;
         wb_we_i    : in   STD_LOGIC;		
         wb_sel_i   : in   STD_LOGIC_VECTOR (3  downto 0);
         wb_data_i  : in   STD_LOGIC_VECTOR (31 downto 0);
         wb_data_o  : out  STD_LOGIC_VECTOR (31 downto 0);
         wb_addr_i  : in   STD_LOGIC_VECTOR (2  downto 0)
       );
end trigger_top;


architecture Behavioral of trigger_top is

  signal s_CTR0     : r_CTR0;
  signal s_CTR1     : r_CTR1;
  signal s_CTR2     : r_CTR2;
  signal s_RAM0     : r_RAM0;
  signal s_RAM1     : r_RAM1;
  signal s_RAM2     : r_RAM2;

  signal write_tt_s : STD_LOGIC;

  signal ramTT_s    : STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH*8 - 1 downto 0);
  signal ramID_s    : STD_LOGIC_VECTOR(31 downto 0);

begin

  core: trigger_core
  port map(
            pulse_i     => pulse_i, 
            pulse_o     => pulse_o,

            led_o       => led_o,

            wb_clk_i    => wb_clk_i,
            wb_rst_i    => wb_rst_i,

            write_tt_o  => write_tt_s,

            CTR0_i      => CTR0_s,
            CTR1_i      => CTR1_s,
            CTR2_o      => CTR2_s
            );


  registers: trigger_regs
  port map(
            wb_rst_i    => wb_rst_i,
            wb_clk_i      => wb_clk_i,
            wb_stb_i    => wb_stb_i,
            wb_cyc_i    => wb_cyc_i,
            wb_ack_o    => wb_ack_o,
            wb_err_o    => wb_err_o,
            wb_rty_o    => wb_rty_o,
            wb_we_i     => wb_we_i,
            wb_sel_i    => wb_sel_i,
            wb_data_i   => wb_data_i,
            wb_data_o   => wb_data_o,
            wb_addr_i   => wb_addr_i,

            CTR0_o      => CTR0_s,
            CTR1_o      => CTR1_s,
            RAM0_o      => RAM0_s,
            RAM1_i      => RAM1_s,
            RAM2_o      => RAM2_s,

            ramTT_i     => ramTT_s,            
            ramID_i     => ramID_s
          );


end Behavioral;
