--------------------------------------------------------------------------------
-- Company:        CERN, BE-CO-HT 
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    18:15:56 11/09/2011 
-- Design Name:    A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name:    i2c_slave_top - Behavioral 
-- Project Name:   CTDAH 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity i2c_slave_top is
   port (
      sda_oen          : out  STD_LOGIC;
      sda_i            : in   STD_LOGIC;
      sda_o            : out  STD_LOGIC;
      scl_oen          : out  STD_LOGIC;
      scl_i            : in   STD_LOGIC;
      scl_o            : out  STD_LOGIC;
      wb_clk           : in   STD_LOGIC;
      wb_rst_i         : in   STD_LOGIC;
      wb_master_stb_o  : out STD_LOGIC;
      wb_master_cyc_o  : out STD_LOGIC;
      wb_master_sel_o  : out STD_LOGIC_VECTOR (3  downto 0);
      wb_master_we_o   : out STD_LOGIC;
      wb_master_data_i : in  STD_LOGIC_VECTOR (31 downto 0);
      wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0);
      wb_master_addr_o : out STD_LOGIC_VECTOR (15  downto 0);
      wb_master_ack_i  : in  STD_LOGIC;
      wb_master_rty_i  : in  STD_LOGIC;
      wb_master_err_i  : in  STD_LOGIC;
      wb_slave_stb_i   : in   STD_LOGIC;
      wb_slave_cyc_i   : in   STD_LOGIC;
      wb_slave_sel_i   : in   STD_LOGIC_VECTOR(3  downto 0);
      wb_slave_we_i    : in   STD_LOGIC;
      wb_slave_data_i  : in   STD_LOGIC_VECTOR(31 downto 0);
      wb_slave_data_o  : out  STD_LOGIC_VECTOR(31 downto 0);
      wb_slave_addr_i  : in   STD_LOGIC_VECTOR(3  downto 0);
      wb_slave_ack_o   : out  STD_LOGIC;
      wb_slave_rty_o   : out  STD_LOGIC;
      wb_slave_err_o   : out  STD_LOGIC;
      pf_wb_addr_o     : out  STD_LOGIC;
      rd_done_o        : out  STD_LOGIC;
      wr_done_o        : out  STD_LOGIC;
      i2c_addr         : in   STD_LOGIC_VECTOR(6  downto 0)
   );
end i2c_slave_top;

architecture Behavioral of i2c_slave_top is


signal s_I2C_MASK: STD_LOGIC_VECTOR (6 downto 0);
signal s_CTR0    : STD_LOGIC_VECTOR (15 downto 0);
signal s_CTR1    : STD_LOGIC_VECTOR (15 downto 0);
signal s_STA     : STD_LOGIC_VECTOR (15 downto 0);
signal s_DRX0    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DRX1    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DRX2    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DRX3    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DRX4    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DRX5    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DTX0    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DTX1    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DTX2    : STD_LOGIC_VECTOR (7  downto 0);
signal s_DTX3    : STD_LOGIC_VECTOR (7  downto 0);
signal s_load_TX      : STD_LOGIC;
signal s_pf_wb_addr   : STD_LOGIC; 
signal s_rd_done      : STD_LOGIC; 
signal s_wr_done      : STD_LOGIC; 

   component i2c_slave_core
   port (
      wb_clk          : in  STD_LOGIC;
      wb_rst_i        : in  STD_LOGIC;
      sda_oen         : out  STD_LOGIC;
      sda_i           : in   STD_LOGIC;
      sda_o           : out  STD_LOGIC;
      scl_oen         : out  STD_LOGIC;
      scl_i           : in   STD_LOGIC;
      scl_o           : out  STD_LOGIC;
      I2C_MASK_i      : in   STD_LOGIC_VECTOR (6  downto 0);
      CTR0_i          : in   STD_LOGIC_VECTOR (15  downto 0);
      CTR1_i          : in   STD_LOGIC_VECTOR (15  downto 0);
      STA_o           : out  STD_LOGIC_VECTOR (15 downto 0);
      DRX0_o          : out  STD_LOGIC_VECTOR (7  downto 0);
      DRX1_o          : out  STD_LOGIC_VECTOR (7  downto 0);
      DRX2_o          : out  STD_LOGIC_VECTOR (7  downto 0);
      DRX3_o          : out  STD_LOGIC_VECTOR (7  downto 0);
      DRX4_o          : out  STD_LOGIC_VECTOR (7  downto 0);
      DRX5_o          : out  STD_LOGIC_VECTOR (7  downto 0);
      DTX0_i          : in   STD_LOGIC_VECTOR (7  downto 0);
      DTX1_i          : in   STD_LOGIC_VECTOR (7  downto 0);
      DTX2_i          : in   STD_LOGIC_VECTOR (7  downto 0);
      DTX3_i          : in   STD_LOGIC_VECTOR (7  downto 0);
      load_TX         : in   STD_LOGIC;
      pf_wb_addr_o    : out  STD_LOGIC;
      rd_done_o       : out  STD_LOGIC;
      wr_done_o       : out  STD_LOGIC 
   );
   end component;

   component i2c_regs
      port (

              pf_wb_addr_i     : in  STD_LOGIC;
              rd_done_i        : in  STD_LOGIC;
              wr_done_i        : in  STD_LOGIC;

              -- These are the registers offers to others modules of the FPGA
              wb_rst_i         : in  STD_LOGIC;
              wb_clk           : in  STD_LOGIC;
              wb_master_we_o   : out STD_LOGIC;
              wb_master_stb_o  : out STD_LOGIC;
              wb_master_cyc_o  : out STD_LOGIC;
              wb_master_sel_o  : out STD_LOGIC_VECTOR (3  downto 0);
              wb_master_data_i : in  STD_LOGIC_VECTOR (31 downto 0);
              wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0);
              wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0);
              wb_master_ack_i  : in  STD_LOGIC;
              wb_master_rty_i  : in  STD_LOGIC;
              wb_master_err_i  : in  STD_LOGIC;
              wb_slave_we_i    : in  STD_LOGIC;
              wb_slave_stb_i   : in  STD_LOGIC;
              wb_slave_cyc_i   : in  STD_LOGIC;
              wb_slave_sel_i   : in  STD_LOGIC_VECTOR(3  downto 0);
              wb_slave_data_i  : in  STD_LOGIC_VECTOR(31 downto 0);
              wb_slave_data_o  : out STD_LOGIC_VECTOR(31 downto 0);
              wb_slave_addr_i  : in  STD_LOGIC_VECTOR(3  downto 0);
              wb_slave_ack_o   : out STD_LOGIC;
              wb_slave_rty_o   : out STD_LOGIC;
              wb_slave_err_o   : out STD_LOGIC;

              i2c_addr        : in   STD_LOGIC_VECTOR (6  downto 0);
      -- These are the registers that are offered to the i2c slave core
              STA_i     : in   STD_LOGIC_VECTOR (15 downto 0);
              I2C_MASK_o: out  STD_LOGIC_VECTOR (6  downto 0);
              CTR0_o    : out  STD_LOGIC_VECTOR (15 downto 0);
              CTR1_o    : out  STD_LOGIC_VECTOR (15 downto 0);
              DRX0_i    : in   STD_LOGIC_VECTOR (7  downto 0);
              DRX1_i    : in   STD_LOGIC_VECTOR (7  downto 0);
              DRX2_i    : in   STD_LOGIC_VECTOR (7  downto 0);
              DRX3_i    : in   STD_LOGIC_VECTOR (7  downto 0);
              DRX4_i    : in   STD_LOGIC_VECTOR (7  downto 0);
              DRX5_i    : in   STD_LOGIC_VECTOR (7  downto 0);
              DTX0_o    : out  STD_LOGIC_VECTOR (7  downto 0);
              DTX1_o    : out  STD_LOGIC_VECTOR (7  downto 0);
              DTX2_o    : out  STD_LOGIC_VECTOR (7  downto 0);
              DTX3_o    : out  STD_LOGIC_VECTOR (7  downto 0);
              load_TX     : out  STD_LOGIC
           );
   end component;


begin

pf_wb_addr_o   <=   s_pf_wb_addr;
rd_done_o      <=   s_rd_done;
wr_done_o      <=   s_wr_done;

   inst_i2c_slave_core: i2c_slave_core
   port map(
       wb_clk         => wb_clk,
       wb_rst_i       => wb_rst_i,
       sda_oen        => sda_oen,
       sda_i          => sda_i,
       sda_o          => sda_o,
       scl_oen        => scl_oen,
       scl_i          => scl_i,
       scl_o          => scl_o,
       I2C_MASK_i     => s_I2C_MASK,
       CTR0_i         => s_CTR0,
       CTR1_i         => s_CTR1,
       STA_o          => s_STA,
       DRX0_o         => s_DRX0,
       DRX1_o         => s_DRX1,
       DRX2_o         => s_DRX2,
       DRX3_o         => s_DRX3,
       DRX4_o         => s_DRX4,
       DRX5_o         => s_DRX5,
       DTX0_i         => s_DTX0,
       DTX1_i         => s_DTX1,
       DTX2_i         => s_DTX2,
       DTX3_i         => s_DTX3,
       load_tx        => s_load_tx,
       pf_wb_addr_o   => s_pf_wb_addr,
       rd_done_o      => s_rd_done,
       wr_done_o      => s_wr_done 
   );

   inst_i2c_regs: i2c_regs
   port map(
       pf_wb_addr_i   => s_pf_wb_addr,
       rd_done_i      => s_rd_done,
       wr_done_i      => s_wr_done, 

       wb_rst_i       => wb_rst_i,
       wb_clk         => wb_clk,

       wb_master_we_o   => wb_master_we_o, 
       wb_master_stb_o  => wb_master_stb_o, 
       wb_master_cyc_o  => wb_master_cyc_o, 
       wb_master_sel_o  => wb_master_sel_o, 
       wb_master_data_i => wb_master_data_i, 
       wb_master_data_o => wb_master_data_o, 
       wb_master_addr_o => wb_master_addr_o, 
       wb_master_ack_i  => wb_master_ack_i, 
       wb_master_rty_i  => wb_master_rty_i, 
       wb_master_err_i  => wb_master_err_i, 

       wb_slave_we_i    => wb_slave_we_i,
       wb_slave_stb_i   => wb_slave_stb_i,
       wb_slave_cyc_i   => wb_slave_cyc_i,
       wb_slave_sel_i   => wb_slave_sel_i,
       wb_slave_data_i  => wb_slave_data_i,
       wb_slave_data_o  => wb_slave_data_o,
       wb_slave_addr_i  => wb_slave_addr_i,
       wb_slave_ack_o   => wb_slave_ack_o,
       wb_slave_rty_o   => wb_slave_rty_o,
       wb_slave_err_o   => wb_slave_err_o,

       i2c_addr       => i2c_addr,
       I2C_MASK_o     => s_I2C_MASK,
       CTR0_o         => s_CTR0,  
       CTR1_o         => s_CTR1,  
       STA_i          => s_STA,  
       DRX0_i         => s_DRX0,  
       DRX1_i         => s_DRX1,  
       DRX2_i         => s_DRX2,  
       DRX3_i         => s_DRX3,  
       DRX4_i         => s_DRX4,  
       DRX5_i         => s_DRX5,  
       DTX0_o         => s_DTX0,  
       DTX1_o         => s_DTX1,  
       DTX2_o         => s_DTX2,  
       DTX3_o         => s_DTX3,
       load_tx        => s_load_tx
   );



end Behavioral;
