--------------------------------------------------------------------------------
-- Company:       CERN, BE-CO-HT 
-- Engineer:      Carlos Gil Soriano
--
-- Create Date:   23:03:04 10/16/2011
-- Design Name:   HDL trigger testbench for CTDAH
-- Module Name:   /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/test/trigger_test.vhd
-- Project Name:  CTDAH
-- Target Device: Spartan 6
-- Tool versions:  
-- Description:   This is a testbench for CTDAH trigger circuit
-- 
-- VHDL Test Bench Created by ISE for module: trigger
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY trigger_test IS
END trigger_test;
 
ARCHITECTURE behavior OF trigger_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT trigger
    PORT(
         input      : IN  std_logic;
         trigger_o  : OUT std_logic;
         utc_i      : IN  std_logic_vector(95 downto 0);
         wb_rst_i   : IN  std_logic;
         wb_clk     : IN  std_logic;
         wb_stb_i   : IN  std_logic;
         wb_cyc_i   : IN  std_logic;
         wb_ack_o   : OUT std_logic;
         wb_err_o   : OUT std_logic;
         wb_rty_o   : OUT std_logic;
         wb_we_i    : IN  std_logic;
         wb_sel_i   : IN  std_logic_vector(3 downto 0);
         wb_data_i  : IN  std_logic_vector(31 downto 0);
         wb_data_o  : OUT std_logic_vector(31 downto 0);
         wb_addr_i  : IN  std_logic_vector(5 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal input     : std_logic := '0';
   signal wb_rst_i  : std_logic := '0';
   signal wb_clk    : std_logic := '0';
   signal wb_stb_i  : std_logic := '0';
   signal wb_cyc_i  : std_logic := '0';
   signal wb_we_i   : std_logic := '0';
   signal wb_sel_i  : std_logic_vector(3 downto 0)  := (others => '0');
   signal wb_data_i : std_logic_vector(31 downto 0) := (others => '0');
   signal wb_addr_i : std_logic_vector(5 downto 0)  := (others => '0');

 	--Outputs
   signal trigger_o   : std_logic;
   signal utc_i       : std_logic_vector(95 downto 0);
   signal wb_ack_o  : std_logic;
   signal wb_err_o  : std_logic;
   signal wb_rty_o  : std_logic;
   signal wb_data_o : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant wb_clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: trigger PORT MAP (
          input     => input,
          trigger_o => trigger_o,
          utc_i     => utc_i,
          wb_rst_i  => wb_rst_i,
          wb_clk    => wb_clk,
          wb_stb_i  => wb_stb_i,
          wb_cyc_i  => wb_cyc_i,
          wb_ack_o  => wb_ack_o,
          wb_err_o  => wb_err_o,
          wb_rty_o  => wb_rty_o,
          wb_we_i   => wb_we_i,
          wb_sel_i  => wb_sel_i,
          wb_data_i => wb_data_i,
          wb_data_o => wb_data_o,
          wb_addr_i => wb_addr_i
        );

   -- Clock process definitions
   wb_clk_process :process
   begin
		wb_clk <= '1';
		wait for wb_clk_period/2;
		wb_clk <= '0';
		wait for wb_clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
      wb_rst_i <= '1';
      wait for wb_clk_period*10;

      wb_rst_i <= '0';
      utc_i    <= X"0123456789ABCDEF0123456789ABCDEF";
      wait for wb_clk_period*10;

-- Read registers via wishbone
      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "000000";
      wait for wb_clk_period;
      assert wb_data_o = X"0000DEAD"
         report "E@wb_rg: Register out of range, should be DEAD"
         severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "000100";
      wait for wb_clk_period;
      assert wb_data_o(5 downto 0) = "000110"
         report "E@wb_rg: c_MAX_GLITCH_STAGES should be 000110"
         severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
     wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "001000";
      wait for wb_clk_period;
      assert wb_data_o(5 downto 0) = "111111"
         report "E@wb_rg: CURRENT_GLITCH_MASK, should be 111111"
         severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "001100";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"003F"
         report "E@wb_rg: MIN_MONOSTABLE_LENGTH, should be 64"
         severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "010000";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"00FF"
	 report "E@wb_rg: MAX_MONOSTABLE_LENGTH, should be 256"
	 severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "010100";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"007F"
         report "E@wb_rg: CURRENT_MONOSTABLE_LENGTH, should be 128"
         severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

-- Write registers via wishbone
      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '1';
      wb_sel_i <= X"F";
      wb_addr_i <= "001000";
      wb_data_i(31 downto 6) <= (others => '0');
      wb_data_i(5 downto 0)  <= "001111";
      wait for wb_clk_period*2;
      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i  <= "001000";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"000F"
         report "E@wb_rg: CURRENT_GLITCH_MASK modified, should be 16"
         severity Error;
      wait for wb_clk_period*2;
      -- insert stimulus here 

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '1';
      wb_sel_i <= X"F";
      wb_addr_i <= "001100";
      wb_data_i(31 downto 6) <= (others => '0');
      wb_data_i(5 downto 0)  <= "000111";
      wait for wb_clk_period*2;
      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "001100";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"0007"
         report "E@wb_rg: MIN_MONOSTABLE_LENGTH modified, should be 7"
         severity Error;
      wait for wb_clk_period*2;

      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '1';
      wb_sel_i <= X"F";
      wb_addr_i <= "010100";
      wb_data_i(31 downto 6) <= (others =>'0');
      wb_data_i(5 downto 0)  <= "001111";
      wait for wb_clk_period*2;
      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i <= "010100";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"000F"
         report "E@wb_rg: CURRENT_MONOSTABLE_LENGTH modified, should be 16"
         severity Error;
      wait for wb_clk_period*2;


      wb_stb_i <= '0';
      wb_cyc_i <= '0';
      wait for wb_clk_period*2;

      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '1';
      wb_sel_i <= X"F";
      wb_addr_i <= "001000";
      wb_data_i(31 downto 6) <= (others => '0');
      wb_data_i(5 downto 0)  <= "000011";
      wait for wb_clk_period*2;
      wb_stb_i <= '1';
      wb_cyc_i <= '1';
      wb_we_i  <= '0';
      wb_sel_i <= X"F";
      wb_addr_i  <= "001000";
      wait for wb_clk_period;
      assert wb_data_o(15 downto 0) = X"0003"
         report "E@wb_rg: CURRENT_GLITCH_MASK modified, should be 03"
         severity Error;
      wait for wb_clk_period*2;


      input    <= '1';
      wait for wb_clk_period*32;

      input    <= '0';
      wait for wb_clk_period*2048;

      wait for wb_clk_period*10;

      wait for wb_clk_period*1028;

      wait;
   end process;

END;
