--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:31:47 06/20/2012
-- Design Name:   
-- Module Name:   /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name:  spi_master_multifield
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: spi_master_core
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------

library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;

entity spi_slave_writer is
   generic(
      g_READ_LENGTH         : NATURAL := c_READ_LENGTH);
   port(  rst_i           : in  STD_LOGIC;
          SPI0_i          : in  r_SPI0;
          SPI1_i          : in  r_SPI1;
          STATUS_i        : in  r_STATUS;

          bytes_to_wr_i   : in  NATURAL;
          read_i          : in STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);

          end_read_flag_o : out STD_LOGIC;

          spi_miso_o      : out STD_LOGIC;
          spi_clk_i       : in  STD_LOGIC
       );
end spi_slave_writer;

architecture Behavioral of spi_slave_writer is 
 
   signal s_spi_count   : NATURAL := 0;

   signal s_SPI0        : r_SPI0;
   signal s_SPI1        : r_SPI1;

   signal s_STATUS      : r_STATUS;

   signal s_spi_clk     : STD_LOGIC; 

   signal s_read        : STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0)
                                                      := (others => '0');

   signal s_bytes_writen  : NATURAL;
   signal s_end_read_flag : STD_LOGIC;

begin

   s_SPI0      <= SPI0_i;
   s_SPI1      <= SPI1_i;
   s_spi_clk   <= spi_clk_i;
   s_read      <= read_i;

   s_STATUS    <= STATUS_i;
   end_read_flag_o <= s_end_read_flag;

      p_spi_writer : process (spi_clk_i, rst_i) is

         function write_on_rise (r_reg : r_SPI0) return STD_LOGIC is
            variable v_return  : STD_LOGIC;
         begin
            case r_reg.CPOL is
               when '0'    =>
                  if r_reg.CPHA = '0' then
                     v_return := '0';
                  else
                     v_return := '1';
                  end if;
               when others =>
                  if r_reg.CPHA = '0' then
                     v_return := '1';
                  else
                     v_return := '0';
                  end if;
            end case;
            return v_return;
         end function;

         procedure write_bit is
         begin
            if s_STATUS.spi_clk_fsm = S5_READ then
               s_bytes_writen <= s_bytes_writen + 1;
               spi_miso_o     <= s_read(r_SPI3'a_length - 1 - s_bytes_writen);
               if s_bytes_writen = g_READ_LENGTH*8 - 1  then
                  s_end_read_flag <= '1';
               end if;
            else
               spi_miso_o     <= 'Z';
            end if;
         end procedure;

      begin
         if rst_i = '1' then
            s_bytes_writen  <= 0;
            spi_miso_o      <= 'Z';
            s_end_read_flag <= '0';
         else
            if     rising_edge(spi_clk_i) 
               and (write_on_rise(s_SPI0) = '1') then
                  write_bit;
            elsif   falling_edge(spi_clk_i) 
               and (write_on_rise(s_SPI0) = '0') then
                  write_bit;
            end if;
         end if;
      end process p_spi_writer;

end;
