--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:31:47 06/20/2012
-- Design Name:   
-- Module Name:   /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name:  spi_master_multifield
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: spi_master_core
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------

library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;

package m25p32_top_tb_pkg is

   component m25p32_top is
      port ( 
              wb_rst_i       : in  STD_LOGIC;
              wb_clk         : in  STD_LOGIC;

              wb_we_i        : in  STD_LOGIC;
              wb_stb_i       : in  STD_LOGIC;
              wb_cyc_i       : in  STD_LOGIC;
              wb_sel_i       : in  STD_LOGIC_VECTOR (3  downto 0);
              wb_data_i      : in  STD_LOGIC_VECTOR (31 downto 0); 
              wb_data_o      : out STD_LOGIC_VECTOR (31 downto 0); 
              wb_addr_i      : in  STD_LOGIC_VECTOR (3  downto 0); 
              wb_ack_o       : out STD_LOGIC; 
              wb_rty_o       : out STD_LOGIC; 
              wb_err_o       : out STD_LOGIC;

              prom_mosi_o    : out STD_LOGIC;
              prom_cclk_o    : out STD_LOGIC;
              prom_cs0_b_n_o : out STD_LOGIC;
              prom_din_i     : in  STD_LOGIC
           );
   end component;

   procedure wishbone_write (
              signal wb_we     : out STD_LOGIC;
              signal wb_stb    : out STD_LOGIC;
              signal wb_cyc    : out STD_LOGIC;
              signal wb_sel    : out STD_LOGIC_VECTOR (3  downto 0);
              signal wb_data   : out STD_LOGIC_VECTOR (31 downto 0);
              signal wb_addr   : out STD_LOGIC_VECTOR (3  downto 0);
                     reg_data  :     STD_LOGIC_VECTOR (31 downto 0);
                     reg_addr  :     STD_LOGIC_VECTOR (1  downto 0)); 

   procedure wishbone_read (
              signal wb_we     : out STD_LOGIC;
              signal wb_stb    : out STD_LOGIC;
              signal wb_cyc    : out STD_LOGIC;
              signal wb_sel    : out STD_LOGIC_VECTOR (3  downto 0);
              signal wb_data   : in  STD_LOGIC_VECTOR (31 downto 0);
              signal wb_addr   : out STD_LOGIC_VECTOR (3  downto 0);
              signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
                     reg_addr  :     STD_LOGIC_VECTOR(1  downto 0));

                     
end m25p32_top_tb_pkg;

package body m25p32_top_tb_pkg is


      procedure wishbone_write (
                 signal wb_we     : out STD_LOGIC;
                 signal wb_stb    : out STD_LOGIC;
                 signal wb_cyc    : out STD_LOGIC;
                 signal wb_sel    : out STD_LOGIC_VECTOR (3  downto 0);
                 signal wb_data   : out STD_LOGIC_VECTOR (31 downto 0);
                 signal wb_addr   : out STD_LOGIC_VECTOR (3  downto 0);
                        reg_data  :     STD_LOGIC_VECTOR (31 downto 0);
                        reg_addr  :     STD_LOGIC_VECTOR (1  downto 0)) is
      begin
           wait until rising_edge(wb_clk);
         wb_we    <= '1';  
         wb_stb   <= '1';  
         wb_cyc   <= '1';  
         wb_sel   <= X"F";  
         wb_data  <= reg_data; 
         wb_addr  <= reg_addr;
           wait until rising_edge(wb_clk);
           --! Here we wait for the ack and keep till operation is finished
           wait until rising_edge(wb_clk);
         wb_we    <= '0';  
         wb_stb   <= '0';  
         wb_cyc   <= '0';  
         wb_sel   <= X"F";  
      end procedure;

      procedure wishbone_read (
                 signal wb_we     : out STD_LOGIC;
                 signal wb_stb    : out STD_LOGIC;
                 signal wb_cyc    : out STD_LOGIC;
                 signal wb_sel    : out STD_LOGIC_VECTOR (3  downto 0);
                 signal wb_data   : in  STD_LOGIC_VECTOR (31 downto 0);
                 signal wb_addr   : out STD_LOGIC_VECTOR (3  downto 0);
                 signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
                        reg_addr  :     STD_LOGIC_VECTOR(1  downto 0)) is
      begin
           wait until rising_edge(wb_clk);
         wb_we    <= '0';  
         wb_stb   <= '1';  
         wb_cyc   <= '1';  
         wb_sel   <= X"F";  
         wb_addr  <= reg_addr;
           wait until rising_edge(wb_clk);
           --! Here we wait for the ack and keep till operation is finished
         read_data  <= wb_data; 
           wait until rising_edge(wb_clk);
         wb_stb   <= '0';  
         wb_cyc   <= '0';  
         wb_sel   <= X"F";  
      end procedure;


end m25p32_top_tb_pkg;
