<WIZARD></WIZARD>

# Generation Report - ALTMEMPHY v11.1

Entity Name | ddr3_mem_phy_alt_mem_phy
Variation Name | ddr3_mem_phy
Variation HDL | VHDL
Output Directory | /home/stefan/quartus_projects/wr-hdl/platform/altera/ddr3

## File Summary

The MegaWizard interface is creating the following files in the output directory:

File | Description
--- | ---
ddr3_mem_phy.vhd | A MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr3_mem_phy.cmp | A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.
ddr3_mem_phy.qip | Contains Quartus II project information for your MegaCore function variation.
ddr3_mem_phy.html | The MegaCore function report file.
ddr3_mem_phy_alt_mem_phy_seq_wrapper.v | A wrapper file that calls the sequencer file, this file is for compilation.
ddr3_mem_phy_alt_mem_phy_seq.vhd | Contains the sequencer used during calibration.
ddr3_mem_phy_alt_mem_phy_dq_dqs.vhd |
ddr3_mem_phy_alt_mem_phy.v | Contains all modules of the ALTMEMPHY variation except for the sequencer.
ddr3_mem_phy_alt_mem_phy_pll.vhd | The PLL megafunction file for your ALTMEMPHY variation.
ddr3_mem_phy_pin_assignments.tcl | Contains I/O standard, drive strength, output enable grouping, and termination assignments for your ALTMEMPHY variation. If your top-level design pin names do not match the default pin names or a prefixed version, edit the assignments in this file.
ddr3_mem_phy_ddr_pins.tcl | Contains procedures used in the ddr3_mem_phy_report_timing.tcl file.
ddr3_mem_phy_report_timing.tcl | Script that reports timing for your ALTMEMPHY variation during compilation.
ddr3_mem_phy_report_timing_core.tcl | Contains procedures used in the ddr3_mem_phy_report_timing.tcl file.
ddr3_mem_phy_ddr_timing.tcl | Contains timing parameters for your ALTMEMPHY variation.
ddr3_mem_phy_ddr_timing.sdc | Contains timing constraints for your ALTMEMPHY variation.
ddr3_mem_phy_alt_mem_phy_pll.qip | Quartus II IP file for the ALTPLL variation, containing the files associated with the ALTPLL megafunction.
alt_mem_phy_defines.v | Contains constants used in the interface.
ddr3_mem_phy.ppf | Pin planner file for your ALTMEMPHY variation.
ddr3_mem_phy_alt_mem_phy_dq_dqs.vhd_clearbox.txt | Clearbox wysiwyg

## MegaCore Function Variation File Ports

Name | Direction | Width
--- | --- | ---
pll_ref_clk | INPUT | 1
global_reset_n | INPUT | 1
soft_reset_n | INPUT | 1
reset_request_n | OUTPUT | 1
ctl_clk | OUTPUT | 1
ctl_reset_n | OUTPUT | 1
ctl_dqs_burst | INPUT | 4
ctl_wdata_valid | INPUT | 4
ctl_wdata | INPUT | 64
ctl_dm | INPUT | 8
ctl_wlat | OUTPUT | 5
ctl_addr | INPUT | 26
ctl_ba | INPUT | 6
ctl_cas_n | INPUT | 2
ctl_cke | INPUT | 2
ctl_cs_n | INPUT | 2
ctl_odt | INPUT | 2
ctl_ras_n | INPUT | 2
ctl_we_n | INPUT | 2
ctl_rst_n | INPUT | 2
ctl_mem_clk_disable | INPUT | 1
ctl_doing_rd | INPUT | 4
ctl_rdata | OUTPUT | 64
ctl_rdata_valid | OUTPUT | 2
ctl_rlat | OUTPUT | 5
ctl_cal_req | INPUT | 1
ctl_cal_byte_lane_sel_n | INPUT | 2
ctl_cal_success | OUTPUT | 1
ctl_cal_fail | OUTPUT | 1
ctl_cal_warning | OUTPUT | 1
mem_addr | OUTPUT | 13
mem_ba | OUTPUT | 3
mem_cas_n | OUTPUT | 1
mem_cke | OUTPUT | 1
mem_cs_n | OUTPUT | 1
mem_dm | OUTPUT | 2
mem_odt | OUTPUT | 1
mem_ras_n | OUTPUT | 1
mem_we_n | OUTPUT | 1
mem_reset_n | OUTPUT | 1
mem_clk | BIDIR | 1
mem_clk_n | BIDIR | 1
mem_dq | BIDIR | 16
mem_dqs | BIDIR | 2
mem_dqs_n | BIDIR | 2
oct_ctl_rs_value | INPUT | 14
oct_ctl_rt_value | INPUT | 14
dqs_offset_delay_ctrl | INPUT | 6
dqs_delay_ctrl_import | INPUT | 6
dqs_delay_ctrl_export | OUTPUT | 6
dll_reference_clk | OUTPUT | 1
dbg_clk | INPUT | 1
dbg_reset_n | INPUT | 1
dbg_addr | INPUT | 13
dbg_wr | INPUT | 1
dbg_rd | INPUT | 1
dbg_cs | INPUT | 1
dbg_wr_data | INPUT | 32
dbg_rd_data | OUTPUT | 32
dbg_waitrequest | OUTPUT | 1
aux_half_rate_clk | OUTPUT | 1
aux_full_rate_clk | OUTPUT | 1