<WIZARD></WIZARD>

# Generation Report - DDR3 SDRAM Controller with ALTMEMPHY v11.1

Entity Name | ddr3_mem_controller_phy
Variation Name | ddr3_mem
Variation HDL | VHDL
Output Directory | /home/stefan/quartus_projects/wr-hdl/platform/altera/ddr3

## File Summary

The MegaWizard interface is creating the following files in the output directory:

File | Description
--- | ---
ddr3_mem.vhd | A MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr3_mem.cmp | A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.
ddr3_mem.qip | Contains Quartus II project information for your MegaCore function variation.
ddr3_mem.html | The MegaCore function report file.
ddr3_mem_example_driver.vhdl | Example self-checking test generator that matches your variation.
ddr3_mem_example_top.vhdl | Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller.
ddr3_mem_example_top.sdc | Example Synopsys Design Constraints file for paths in the example top level.
ddr3_mem_ex_lfsr8.vhdl | Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver.
testbench | ddr3_mem_example_top_tb.vhdl | Example testbench that instantiates the example top level design file and the example memory model.
testbench | ddr3_mem_mem_model.vhdl | A simple example memory model that matches your variation.
testbench | ddr3_mem_full_mem_model.vhdl | Memory model that allocates memory for all available addresses.
ddr3_mem_pin_assignments.tcl | TCL script
ddr3_mem_advisor.ipa | IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software.
ddr3_mem_phy.qip | Generated ALTMEMPHY QIP file.

## MegaCore Function Variation File Ports

Name | Direction | Width
--- | --- | ---
local_address | INPUT | 24
local_write_req | INPUT | 1
local_read_req | INPUT | 1
local_burstbegin | INPUT | 1
local_ready | OUTPUT | 1
local_rdata | OUTPUT | 64
local_rdata_valid | OUTPUT | 1
local_wdata | INPUT | 64
local_be | INPUT | 8
local_size | INPUT | 3
local_refresh_ack | OUTPUT | 1
local_init_done | OUTPUT | 1
reset_phy_clk_n | OUTPUT | 1
dbg_addr | INPUT | 13
dbg_wr | INPUT | 1
dbg_rd | INPUT | 1
dbg_cs | INPUT | 1
dbg_wr_data | INPUT | 32
dbg_rd_data | OUTPUT | 32
dbg_waitrequest | OUTPUT | 1
dll_reference_clk | OUTPUT | 1
dqs_delay_ctrl_export | OUTPUT | 6
mem_odt | OUTPUT | 1
mem_clk | BIDIR | 1
mem_clk_n | BIDIR | 1
mem_cs_n | OUTPUT | 1
mem_cke | OUTPUT | 1
mem_addr | OUTPUT | 13
mem_ba | OUTPUT | 3
mem_ras_n | OUTPUT | 1
mem_cas_n | OUTPUT | 1
mem_we_n | OUTPUT | 1
mem_dq | BIDIR | 16
mem_dqs | BIDIR | 2
mem_dqsn | BIDIR | 2
mem_dm | OUTPUT | 2
mem_reset_n | OUTPUT | 1
global_reset_n | INPUT | 1
pll_ref_clk | INPUT | 1
phy_clk | OUTPUT | 1
aux_full_rate_clk | OUTPUT | 1
aux_half_rate_clk | OUTPUT | 1
soft_reset_n | INPUT | 1
reset_request_n | OUTPUT | 1