use_dqs_output_delay_chain1=FALSE
use_dqs_output_delay_chain2=FALSE
use_dynamic_oct=FALSE
use_dqs_oe_delay_chain1=FALSE
use_dqs_oe_delay_chain2=FALSE
use_io_clock_divider_phasectrlin=FALSE
number_of_output_dq=1
use_dqs_enable_ctrl=TRUE
use_dq_output_delay_chain1=FALSE
dqs_output_reg_power_up=LOW
use_dqs_output_path=TRUE
use_dq_output_delay_chain2=FALSE
use_dqsenable_delay_chain=FALSE
dq_oe_reg_mode=FF
dq_input_reg_async_mode=NONE
dq_ipa_add_phase_transfer_reg=FALSE
number_of_clk_divider=0
use_dqs_enable_ctrl_phasectrlin=FALSE
dqs_delay_chain_delayctrlin_source=DLL
level_dqs_enable=FALSE
dq_input_reg_mode=DDIO
use_dq_ipa=FALSE
io_clock_divider_phase_setting=0
dq_input_reg_power_up=LOW
io_clock_divider_clk_source=CORE
dqs_input_frequency="400.0 MHz"
dqs_dqsn_mode=DIFFERENTIAL
dqs_oe_reg_sync_mode=NONE
oct_reg_mode=NONE
dqs_output_reg_mode=DDIO
dqs_enable_ctrl_invert_phase=FALSE
io_clock_divider_invert_phase=FALSE
use_dqs_enable=TRUE
dq_ipa_invert_phase=FALSE
use_dq_oe_path=TRUE
dq_ipa_phase_setting=0
dqs_output_reg_sync_mode=NONE
use_oct_delay_chain2=FALSE
dqs_ctrl_latches_enable=FALSE
dq_output_reg_sync_mode=NONE
use_dqs_oe_path=TRUE
use_dqs_delay_chain_phasectrlin=FALSE
use_dqs_input_path=TRUE
use_oct_delay_chain1=FALSE
use_dq_input_delay_chain=FALSE
dq_oe_reg_async_mode=NONE
dq_input_reg_use_clkn=FALSE
dq_half_rate_use_dataoutbypass=FALSE
dqs_oe_reg_mode="FF"
number_of_bidir_dq=8
use_half_rate=FALSE
dq_output_reg_power_up=LOW
dq_input_reg_sync_mode=NONE
dqs_oe_reg_async_mode=NONE
use_dq_oe_delay_chain1=FALSE
delay_dqs_enable_by_half_cycle=TRUE
use_dq_oe_delay_chain2=FALSE
use_dqs_input_delay_chain=FALSE
use_io_clock_divider_masterin=FALSE
use_dqs_delay_chain=TRUE
dq_ipa_bypass_output_register=FALSE
dq_output_reg_async_mode=CLEAR
dqs_enable_ctrl_phase_setting=0
dq_input_reg_clk_source=INVERTED_DQS_BUS
dq_ipa_add_input_cycle_delay=FALSE
dqs_phase_shift=9000
device_family=arriaii
use_dq_ipa_phasectrlin=FALSE
dqs_output_reg_async_mode=NONE
number_of_input_dq=0
dll_delay_buffer_mode=HIGH
dq_oe_reg_sync_mode=NONE
delay_buffer_mode=HIGH
dqs_offsetctrl_enable=FALSE
dq_output_reg_mode=DDIO
use_dqs=TRUE
dq_oe_reg_power_up=LOW
dqs_delay_chain_phase_setting=2
use_dqsbusout_delay_chain=FALSE
dqs_oe_reg_power_up=LOW
dqs_enable_ctrl_add_phase_transfer_reg=FALSE
bidir_dq_areset
bidir_dq_input_data_in
bidir_dq_input_data_out_high
bidir_dq_input_data_out_low
bidir_dq_oe_in
bidir_dq_oe_out
bidir_dq_output_data_in_high
bidir_dq_output_data_in_low
bidir_dq_output_data_out
dll_delayctrlin
dq_input_reg_clk
dq_output_reg_clk
dqs_enable_ctrl_in
dqs_enable_ctrl_clk
dqs_input_data_in
dqsn_oe_in
dqsn_oe_out
dqs_oe_in
dqs_oe_out
dqs_output_data_in_high
dqs_output_data_in_low
dqs_output_data_out
dqs_output_reg_clk
output_dq_oe_in
output_dq_oe_out
output_dq_output_data_in_high
output_dq_output_data_in_low
output_dq_output_data_out
