--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:13:33 10/16/2011
-- Design Name:   
-- Module Name:   /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/test/monostable_test.vhd
-- Project Name:  CTDAH
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: monostable
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
 
ENTITY monostable_test IS
END monostable_test;
 
ARCHITECTURE behavior OF monostable_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT monostable
    PORT(
         rst : IN  std_logic;
         clk : IN  std_logic;
         pulse_len : IN UNSIGNED(15 downto 0);
         input : IN  std_logic;
         output : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal rst : std_logic := '0';
   signal clk : std_logic := '0';
   signal pulse_len : unsigned(15 downto 0) := X"0000";
   signal input : std_logic := '0';

 	--Outputs
   signal output : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: monostable PORT MAP (
          rst => rst,
          clk => clk,
          pulse_len => pulse_len,
          input => input,
          output => output
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '1';
		wait for clk_period/2;
		clk <= '0';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		

      rst   <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      rst        <= '0';
      pulse_len  <= X"0FFF";
      input      <= '1';
      wait for clk_period*256;

      input      <= '0';
      wait for clk_period*1024;

      -- insert stimulus here 

      wait;
   end process;

END;
