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\begin{document}
\title{I2C Slave to Wishbone Master module}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{February 23, 2012}
\maketitle

\begin{abstract}
An I2C Slave to Wishbone Master module is depicted in this document. The module
is targeted for Spartan 6 devices and written in VHDL.\\
The following subjects are addressed:
\begin{itemize}
  \item The registers to control the module.
  \item Step-by-step instructions for proper use.
  access.
\end{itemize}
\end{abstract}

\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & I2C slave & February 23, 2012\\
\hline
\end{tabular}
\end{center}

\pagebreak

\tableofcontents

\pagebreak
\section{Structure}
The i2c module contains several blocks related the following way:\\

--  i2c\_slave\_top.vhd 

----- i2c\_regs.vhd

----- i2c\_slave\_core.vhd

--------- FIFO\_dispatcher.vhd

--------- FIFO\_stack.vhd

--------- gc\_counter.vhd

--------- gc\_ff.vhd

--------- i2c\_bit.vhd


\section{Interrupting lines offered}

\subsection{ind\_wb\_addr}
This interrupting signal issues when a \textit{indirect wishbone address} has
been received. It is notified right after the first CTR0[BIA] + 1 bytes upon the
reception of the I2C byte address packet.
This signal is vital for correctly prefetching when a I2C read operation is
requested.

\subsection{inst\_rd}
This signal is issued when a read operation directed by an external master over
the HDL slave core is finished. That means it will be generated after the last
data byte has been sent by the HDL core.

\subsection{inst\_wr}
This signal is issued when a write operation directed by an external master over
the HDL slave core is finished. That means it will be generated after the last
data byte has been received.

\section{Registers}

\subsection{STA}
The STA register is a read-only register. It control the general enable and
reset of the module. It also contains the current value of the finite state
machine of the i2c modue (useful for easy debugging).\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & RST & General ReSeT\\
\hline
2 & RD\_WRN\_INST & Reserved\\
\hline
3 & A\_RX &\\
\hline
4 & A\_TX &\\
\hline
8-5 & x & Reserved\\
\hline
15-9 & i2c\_sla\_fsm & i2c fsm\\
\hline
31-16 & Not used\\
\hline
\end{tabular}

\subsection{PRE}
The PRE register is a write-read register. Right now it is not used.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & PRE & PREscaler value\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}


\subsection{CTR0}
The CTR0 register is a write-read register. It controls the indirect addres
and holds the I2C address (which in the case of \textit{CONV-TTL-BLO} will be
connected to VME64x geographical address pins).\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & general ENable\\
\hline
1 & RST & general ReSeT\\
\hline
2 & PEN & Prescaler ENable\\
\hline
5-3 & x & Reserved\\
\hline
7-6 & BIA & Bytes Indirect Addressing\\
\hline
14-8 & A[6:0] & I2C address\\
\hline
15 & x & Reserved\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}

\subsection{CTR1}
The CTR1 register is a write-read register. It shows the fsm of the separate
\textit{read} and \textit{write} fsms.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & RDS & fsm status: ReaD Status\\
\hline
15-8 & WDS & fsm status: WRite Status\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}

\subsection{DRXA}
The DRXA register is a read-only register. It holds the last four received
bytes through the I2C. DRX0 has the most recent byte received from the serial
interface. DRX3 has the oldest byte received.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & DRX0 & Data RX register 0\\
\hline
15-8 & DRX1 & Data RX register 1\\
\hline
23-16 & DRX2 & Data RX register 2\\
\hline
31-24 & DRX3 & Data RX register 3\\
\hline
\end{tabular}

\subsection{DRXB}
The DRXB register is a read-only register. It holds the fifth and sixth latest
received bytes, respectively.
\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & DRX4 & Data RX register 0\\
\hline
15-8 & DRX5 & Data RX register 1\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}


\subsection{DTX}
The DTX register is a write-read register. It shows the fsm of the separate
\textit{read} and \textit{write} fsms.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & RDS & fsm status: ReaD Status\\
\hline
15-8 & WDS & fsm status: WRite Status\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}

\section{Internal Memory Mapping}
The internal registers map is as follow:\\

\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{STA} & Read-only\\
\hline
\textbf{0x1} & \textit{PRE} & Write-read\\
\hline
\textbf{0x2} & \textit{CTR0} & Write-read\\
\hline
\textbf{0x3} & \textit{CTR1} & Write-read\\
\hline
\textbf{0x4} & \textit{DRXA} & Read-only\\
\hline
\textbf{0x5} & \textit{DRXB} & Read-only\\
\hline
\textbf{0x6} & \textit{DTX} & Write-read\\
\hline
\end{tabular} 

\section{How to use it}
\subsection{Initialization}

\begin{enumerate}
\item Perform a reset of the module while module is not enabled:\\
\textit{CTR0: write 0 to EN and 1 to RST.} 
\item Load the prescaler:\\
\textit{PRE: set a new value.}
\item  Set the I2C address of the slave module:\\
\textit{CTR0[A]: set the I2C address.}
\item  Set the rest of bits of CTR0, including EN:\\
\textit{CTR0: set rest of bits.}
\end{enumerate}

\subsection{Indirect Write from Master to Slave}

It is a one-phase transaction: one indirect writing is achieved
by signaling only one I2C start condition by the master.

\begin{enumerate}
  \item The Master I2C device starts an I2C transaction. In the first byte it
specifies the type of transaction issued as a write.
  \item Then, two bytes are received in the slave. At the end of the reception
  of the last bit of this second byte (third since the I2C start condition), the
  finite state machine in \textit{i2c\_slave\_core.vhd} launches the interrupt
  \textit{inst\_wb\_addr}.
 
  \textbf{Address prefetching}: at this point, the Wishbone Address can be
  stored.
  It is found in \textit{DRX0} and \textit{DRX1} registers:
  
  \begin{itemize}
    \item \textit{DRX0}: holds the Wishbone Address Lowest Byte
    \item \textit{DRX1}: holds the Wishbone Address Highest Byte
  \end{itemize}
  
  \item Following the reception of the two bytes corresponding to the Wishbone
  Address, four more bytes will be received. They are the data bytes. Once the
  last bit of this fourth byte is received (seventh byte since the I2C start
  condition), the finite state machine in \textit{i2c\_slave\_core.vhd} launches
  the interrupt \textit{inst\_wr}.
  
  \textbf{Address and Data fetching}: at this point, the \textit{Wishbone
  Address} and the \textit{Data} to be written in that address can be both
  fetched through the \textit{DRX} registers:
  
  \begin{itemize}
    \item \textit{DRX0}: holds the Data Lowest Byte
    \item \textit{DRX1}: holds the Data 2$^{nd}$ Lowest Byte
    \item \textit{DRX2}: holds the Data 2$^{nd}$ Highest Byte
    \item \textit{DRX3}: holds the Data Highest Byte
    \item \textit{DRX4}: holds the Wishbone Address Lowest Byte
    \item \textit{DRX5}: holds the Wishbone Address Highest Byte
  \end{itemize}
  
  \item The Master I2C device stops the I2C transaction. 
\end{enumerate}

\subsection{Indirect Read from Master to Slave}

It is a two-phases transaction: one indirect read is achieved
by signaling only two I2C start conditions by the master.\\

\textbf{FIRST PHASE}

\begin{enumerate}
  \item The Master I2C device starts an I2C transaction. In the first byte it
specifies the type of transaction issued as a write.
  \item Then, two bytes are received in the slave. At the end of the reception
  of the last bit of this second byte (third since the I2C start condition), the
  finite state machine in \textit{i2c\_slave\_core.vhd} launches the interrupt
  \textit{inst\_wb\_addr}.
 
  \textbf{Address Prefetching}: at this point, the Wishbone Address can be
  stored.
  It is found in \textit{DRX0} and \textit{DRX1} registers:
  
  \begin{itemize}
    \item \textit{DRX0}: holds the Wishbone Address Lowest Byte
    \item \textit{DRX1}: holds the Wishbone Address Highest Byte
  \end{itemize}
  
    \textbf{Data Prefetching}: it is a good practice to do the \textit{data
  prefetching} of the Wishbone Address (in case this is accessible). The control
  logic attached to the \textit{i2c\_slave\_wb} module should perform a
  wishbone write to the four \textit{DTX[X]} registers:
  
  \begin{itemize}
    \item \textit{DTX0}: holds the Data Lowest Byte
    \item \textit{DTX1}: holds the Data 2$^{nd}$ Lowest Byte
    \item \textit{DTX2}: holds the Data 2$^{nd}$ Highest Byte
    \item \textit{DTX3}: holds the Data Highest Byte
  \end{itemize}
  
  so that the data in the transmission registers is up-to-date, in order to be
  sent through I2C.
  
\end{enumerate}\\
\pagebreak
\textbf{SECOND PHASE}

\begin{enumerate}
  

  \item The Master I2C device (re)starts an I2C transaction. In the first byte
  it specifies the type of transaction issued as a read. At the end of the
  reception of the last bit on the first byte of this \textit{second phase}
  (third byte sinc the I2C start condition from the \textit{first phase}), the
  finite state machine in \textit{i2c\_slave\_core.vhd} launches the interrupt
  \textit{inst\_wb\_addr}.
  
  \item The \textit{i2c\_slave\_wb} module sends the four data bytes in the
  following order:
  
    \begin{enumerate}
    \item Data Lowest Byte
    \item Data 2$^{nd}$ Lowest Byte
    \item Data 2$^{nd}$ Highest Byte
    \item Data Highest Byte
  \end{enumerate}
  
  \item Once the last byte has been already send,  the finite state machine in
  \textit{i2c\_slave\_core.vhd} launches the interrupt \textit{inst\_rd\_addr}.
\end{enumerate}
\end{document}
