--
--	Package File Template
--
--	Purpose: This package defines supplemental types, subtypes, 
--		 constants, and functions 
--
--   To use any of the example code shown below, uncomment the lines and modify as necessary
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package ctdah_pkg is

   component gc_clk_divider is
      generic( g_clk_division_logSize : NATURAL := 8);
      port (
              clk_i      : in  STD_LOGIC;
              rst_i      : in  STD_LOGIC;
              oe_n_i     : in  STD_LOGIC;
              clk_o      : out STD_LOGIC;
              divider_i  : in  STD_LOGIC_VECTOR (g_clk_division_logSize - 1 downto 0) --Divides by twice the value specified
           );
   end component;

   component gc_counter is
      generic(
      g_data_width: NATURAL
   );
   port (
           clk_i  : in  STD_LOGIC;
           rst_i  : in  STD_LOGIC;
           en_i   : in  STD_LOGIC;
           cnt_o  : out  STD_LOGIC_VECTOR (g_data_width-1 downto 0)
        );
   end component;

   component gc_ff is
     port(
             Q   : out STD_LOGIC;
             C   : in  STD_LOGIC;
             CLR : in  STD_LOGIC;
             D   : in  STD_LOGIC
                   );
   end component;
                
   component FIFO_dispatcher is
      generic(
                g_data_width       : NATURAL := 8;
                g_dispatcher_depth : NATURAL := 4
             );
      port (
              reg_i  : in  STD_LOGIC_VECTOR (g_dispatcher_depth*g_data_width-1 downto 0);
              clk    : in  STD_LOGIC;
              load   : in  STD_LOGIC;
              flush  : in  STD_LOGIC;
              oen_i  : in  STD_LOGIC;
              reg_o  : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
           );
   end component;

   component FIFO_stack is
      generic(
                g_data_width  : NATURAL := 8;
                g_stack_depth : NATURAL := 8
             );
      port (
              reg_i  : in   STD_LOGIC_VECTOR (g_data_width-1 downto 0);
              clk    : in   STD_LOGIC;
              push   : in   STD_LOGIC;
              flush  : in   STD_LOGIC;
              reg_o  : out  STD_LOGIC_VECTOR (g_stack_depth*g_data_width - 1 downto 0)
           );
   end component;

   component FIFO_simple is
      generic(
                g_data_width  : NATURAL := 8
             );
      port (
              reg_i  : in   STD_LOGIC_VECTOR (g_data_width-1 downto 0);
              clk    : in   STD_LOGIC;
              push   : in   STD_LOGIC;
              flush  : in   STD_LOGIC;
              reg_o  : out  STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
           );
   end component;


end ctdah_pkg;

package body ctdah_pkg is
end ctdah_pkg;
