----------------------------------------------------------------------------------
-- Company:        CERN, BE-CO-HT
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    09:58:06 10/12/2011 
-- Design Name:    HDL trigger
-- Module Name:    trigger - Behavioral 
-- Project Name:   CTDAH
-- Target Devices: Spartan 6
-- Tool versions: 
-- Description:    This is the wishbone trigger which receives a debounced input
--                 and outputs a trigger signal for the pulse converter
-- Dependencies:   none
--
-- Revision: 
-- Revision 0.1
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity trigger_core is
  port (
         pulse_i    : in   STD_LOGIC;
         pulse_o    : out  STD_LOGIC;

         led_o      : out  STD_LOGIC;

         wb_clk     : in   STD_LOGIC;
         wb_rst_i   : in   STD_LOGIC;

         write_tt_o : out  STD_LOGIC;

         STATUS_i   : in   STD_LOGIC_VECTOR (31 downto 0);
         CTR0_i     : in   STD_LOGIC_VECTOR (31 downto 0);
         CTR1_i     : in   STD_LOGIC_VECTOR (31 downto 0);
         RAM0_i     : in   STD_LOGIC_VECTOR (31 downto 0);
         RAM1_i     : in   STD_LOGIC_VECTOR (31 downto 0);
         RAM2_i     : in   STD_LOGIC_VECTOR (31 downto 0)
       );

end trigger_core;

architecture Behavioral of trigger_core is

  constant c_MAX_GLITCH_STAGES : INTEGER := 6;

  signal deglitched_input   : STD_LOGIC;

  signal deglitched_input_s : STD_LOGIC;
  signal monostable_input_s : STD_LOGIC;
  signal count_s            : STD_LOGIC_VECTOR(15 downto 0);

  signal pulse_i_controlled : STD_LOGIC;

  component debouncer
    generic(
    g_LENGTH  : INTEGER := c_MAX_GLITCH_STAGES
  );
  port(
        rst       : in  STD_LOGIC;
        clk       : in  STD_LOGIC;
        input     : in  STD_LOGIC;
        output    : out STD_LOGIC;
        glitch_mask  : in std_logic_vector(g_LENGTH - 1 downto 0)
      );
  end component;

  component monostable
    port(
          rst         : in  STD_LOGIC;
          clk         : in  STD_LOGIC;
          pulse_len   : in  STD_LOGIC_VECTOR(31 downto 0);
          write_tt_o  : out STD_LOGIC;
          input       : in  STD_LOGIC;
          output      : out STD_LOGIC
        );
  end component;


begin


  count_s              <= CTR0_i(30 downto 16) & '0';
  pulse_i_controlled   <= pulse_i and CTR0_i(0);


  inst_debo: debouncer
  port map(
            rst         => wb_rst_i,
            clk         => wb_clk,
            input       => pulse_i_controlled,
            output      => deglitched_input,
            glitch_mask => CTR0_i(c_MAX_GLITCH_STAGES - 1 + 8 downto 8)
          );

  inst_mono: monostable
  port map(
            rst         => wb_rst_i,
            clk         => wb_clk,
            pulse_len(31 downto 16)   => X"0000",
            pulse_len(15 downto  0)   => STATUS_i(31 downto 16),
            write_tt_o  => write_tt_o,
            input       => deglitched_input,
            output      => pulse_o
          );

  led_mono: monostable
  port map(
   rst         => wb_rst_i,
   clk         => wb_clk,
   pulse_len   => X"00989680",  -- 500ms
--   write_tt_o  => 'Z',
   input       => deglitched_input,
   output      => led_o       
          );

  process(wb_clk)

  begin

    if rising_edge(wb_clk) then

      if STATUS_i(0) = '1' then
        deglitched_input_s <= deglitched_input;
      else
      end if;

    end if;

  end process;

end Behavioral;
