----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
-- 
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company:        CERN, BE-CO-HT 
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    17:10:27 06/15/2012 
-- Design Name:     
-- Module Name:    spi_master_top - Behavioral 
-- Project Name:   CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions:  Xilinx ISE 13.4
-- Description:    This is a spi_master with programable field length and progra
--                 mable setup and hold chip select times.
--
-- Dependencies: 
--
-- Revision: 0.1
--   0.01          + File Created
--   0.1           - Alpha version. Able to write and output data correctly at
--                   different configurations.
-- Additional Comments: 
--
----------------------------------------------------------------------------------

library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use work.spi_master_pkg.ALL;


entity spi_master_top is
   port(
          wb_clk       : in  STD_LOGIC;
          wb_rst_i     : in  STD_LOGIC;

          wb_stb_i     : in  STD_LOGIC;
          wb_cyc_i     : in  STD_LOGIC;
          wb_sel_i     : in  STD_LOGIC_VECTOR(3  downto 0);
          wb_we_i      : in  STD_LOGIC;
          wb_data_i    : in  STD_LOGIC_VECTOR(31 downto 0);
          wb_data_o    : out STD_LOGIC_VECTOR(31 downto 0);
          wb_addr_i    : in  STD_LOGIC_VECTOR(3  downto 0);
          wb_ack_o     : out STD_LOGIC;
          wb_rty_o     : out STD_LOGIC;
          wb_err_o     : out STD_LOGIC;

          inst_i       : in  STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
          addr_i       : in  STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
          data_i       : in  STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);

          spi_mosi_o   : out STD_LOGIC;
          spi_miso_i   : in  STD_LOGIC;
          spi_clk_o    : out STD_LOGIC;
          spi_cs_n_o   : out STD_LOGIC

       );
end spi_master_top;

architecture Behavioral of spi_master_top is

   component spi_master_core is
   generic(
             g_INST_LENGTH  : NATURAL := c_INST_LENGTH;
             g_ADDR_LENGTH  : NATURAL := c_ADDR_LENGTH;
             g_DATA_LENGTH  : NATURAL := c_DATA_LENGTH;
             g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
   port(
          rst_i         : in  STD_LOGIC;
          clk_i         : in  STD_LOGIC;

          inst_i        : in  STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
          addr_i        : in  STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
          data_i        : in  STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);

          SPI0_i        : in  STD_LOGIC_VECTOR (31 downto 0);
          SPI1_i        : in  STD_LOGIC_VECTOR (31 downto 0);
          SPI2_o        : out STD_LOGIC_VECTOR (15 downto 0);

          spi_mosi_o    : out STD_LOGIC;
          spi_miso_i    : in  STD_LOGIC;
          spi_clk_o     : out STD_LOGIC;
          spi_cs_n_o    : out STD_LOGIC
       );
   end component;

   component spi_master_regs is
      port(
      wb_rst_i   : in  STD_LOGIC;
      wb_clk_i   : in  STD_LOGIC;
                       
      wb_stb_i   : in  STD_LOGIC;
      wb_cyc_i   : in  STD_LOGIC;
      wb_sel_i   : in  STD_LOGIC_VECTOR (3  downto 0);
      wb_we_i    : in  STD_LOGIC;
      wb_data_i  : in  STD_LOGIC_VECTOR (31 downto 0);
      wb_data_o  : out STD_LOGIC_VECTOR (31 downto 0);
      wb_addr_i  : in  STD_LOGIC_VECTOR (3  downto 0);
      wb_ack_o   : out STD_LOGIC;
      wb_rty_o   : out STD_LOGIC;
      wb_err_o   : out STD_LOGIC;
                       
      SPI0_o     : out STD_LOGIC_VECTOR (31 downto 0);
      SPI1_o     : out STD_LOGIC_VECTOR (31 downto 0);
      SPI2_i     : in  STD_LOGIC_VECTOR (15 downto 0)
   );

   end component;

signal s_SPI0 : STD_LOGIC_VECTOR (31  downto 0); 
signal s_SPI1 : STD_LOGIC_VECTOR (31  downto 0); 
signal s_SPI2 : STD_LOGIC_VECTOR (15  downto 0); 

begin

   inst_spi_master_core: spi_master_core 
   port map(
              rst_i       => wb_rst_i, 
              clk_i       => wb_clk, 

              inst_i      => inst_i, 
              addr_i      => addr_i, 
              data_i      => data_i, 
              SPI0_i      => s_SPI0, 
              SPI1_i      => s_SPI1, 
              SPI2_o      => s_SPI2, 

              spi_mosi_o  => spi_mosi_o, 
              spi_miso_i  => spi_miso_i, 
              spi_clk_o   => spi_clk_o, 
              spi_cs_n_o  => spi_cs_n_o 
              );

   inst_spi_master_regs: spi_master_regs
   port map(
              wb_rst_i    => wb_rst_i, 
              wb_clk_i    => wb_clk,

              wb_stb_i    => wb_stb_i, 
              wb_cyc_i    => wb_cyc_i, 
              wb_sel_i    => wb_sel_i, 
              wb_we_i     => wb_we_i, 
              wb_data_i   => wb_data_i, 
              wb_data_o   => wb_data_o, 
              wb_addr_i   => wb_addr_i, 
              wb_ack_o    => wb_ack_o, 
              wb_rty_o    => wb_rty_o, 
              wb_err_o    => wb_err_o, 

              SPI0_o      => s_SPI0, 
              SPI1_o      => s_SPI1,
              SPI2_i      => s_SPI2
           );

end Behavioral;

