--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   21:05:27 10/08/2011
-- Design Name:   
-- Module Name:   /media/BACKUP/Xilinx/CTDAH/CTDAH/debouncer_test.vhd
-- Project Name:  CTDAH
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: debouncer
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

library UNISIM;
use UNISIM.VComponents.all;
 
ENTITY debouncer_test IS
END debouncer_test;
 
ARCHITECTURE behavior OF debouncer_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT debouncer
    PORT(
         rst     : IN   std_logic;
         clk     : IN   std_logic;
         input   : IN   std_logic;
         output  : OUT  std_logic;
         glitch_mask : in STD_LOGIC_VECTOR(5 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal rst   : std_logic := '0';
   signal clk   : std_logic := '0';
   signal input : std_logic := '0';
   signal glitch_mask : STD_LOGIC_VECTOR(5 downto 0) := "111111";
 	--Outputs
   signal output : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: debouncer 
      PORT MAP (
          rst => rst,
          clk => clk,
          input => input,
          output => output,
          glitch_mask => glitch_mask
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;

      rst <= '1';
      wait for clk_period*10;		

      rst <= '0';
      wait for clk_period*10;		

      input <= '1';
      wait for clk_period*10;

      input <= '0';
      

      -- insert stimulus here 

      wait;
   end process;

END;
