----------------------------------------------------------------------------------
-- Company:        CERN
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    17:26:32 15/03/2012 
-- Design Name:    16 bit counter 
-- Module Name:    gc_counter16 - Behavioral 
-- Project Name:   CTDAH
-- Target Devices: Spartan 6
-- Tool versions: 
-- Description:    a basic 16 bit counter pin-to-pin compatible with Xilinx
--                 IP core
--
-- Dependencies:   none 
--
-- Revision: 
-- Revision 0. 1 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity gc_counter16 is
  port(
         clk      : in  STD_LOGIC;
         ce       : in  STD_LOGIC;
         sclr     : in  STD_LOGIC;
         sset     : in  STD_LOGIC;
         q        : out STD_LOGIC_VECTOR(15 downto 0)
      );
end gc_counter16;

architecture Behavioral of gc_counter16 is

signal counter  : UNSIGNED(15 downto 0);
signal q_s      : STD_LOGIC_VECTOR(15 downto 0);

begin

   reg_proc: process(clk)
   begin
      if rising_edge(clk) and ce = '1' then
         q      <= STD_LOGIC_VECTOR(counter);
         q_s    <= STD_LOGIC_VECTOR(counter);
         if sclr = '1' then
            counter     <= (others => '0');
         elsif sset =  '1' then
            counter     <= (others => '1');
         else
            if q_s = X"FFFF" then
               counter  <= (others => '0');
            else
               counter  <= counter + 1;
            end if;
         end if;
      else
      end if;
   end process;

end Behavioral;
