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\begin{document}
\title{Trigger control module for pulse repetition in CONV-TTL-BLO}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{February 6, 2012}
\maketitle

\begin{abstract}
The task of this HDL core is controlling the pulse replication.
Firstly, after a debouncing stage, it detects an input pulse . Once the input is
validated, an output signal if generated within the FPGA. This output signal
directly controls the pulse generation of the Blocking drivers in CONV-TTL-BLO.

This document shows:
\begin{itemize}
  \item Parameters used as \textit{generic}
  \item The registers to control the module.
  \item Step-by-step instructions for proper use.
\end{itemize}
\end{abstract}

\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & Trigger & February 6, 2012\\
\hline
\end{tabular}
\end{center}


\pagebreak

\tableofcontents

\pagebreak

\section{Structure}

The trigger module contains several blocks related the following way:\\

--  trigger\_top.vhd 

----- trigger\_regs.vhd

----- trigger\_core.vhd

--------- debouncer.vhd

--------- monostable.vhd

----- TT\_RAMhandler.vhd

--------- gc\_RAM.vhd (for IDs)

--------- gc\_RAM.vhd (for TTs)

\subsection{ HDL cores}

\subsubsection{\textit{trigger\_top.vhd}}

The top module interconnects the three basic building blocks: registers, core
and generic RAM. Each \textit{trigger\_top.vhd} module will control
one output Blocking driver.

Inside \textit{trigger\_top.vhd} there are some constant that are used as
\textit{generic} in both the registers and generic RAMs. The constants are
explained later in the section 'Parameters' and are the following:
\begin{itemize}
  \item \textit{c\_RAM\_SIZE }
  \item \textit{c\_MAX\_GLITCH\_STAGES }
  \item \textit{c\_DEFAULT\_GLITCH\_MASK }
  \item \textit{c\_MIN\_PULSE\_LENGTH }
  \item \textit{c\_MAX\_PULSE\_LENGTH }
  \item \textit{c\_DEFAULT\_PULSE\_LENGTH }
  \item \textit{c\_TAGS\_DATA\_WIDTH } 
\end{itemize}

\subsubsection{\textit{trigger\_regs.vhd}}

It consist of a core that can be accessed via Wishbone and that contains all the
registers which control this trigger core. The minimum and maximum values and
proceeding for configuring them will be explained in the two next following
sections.

\subsubsection{\textit{TT\_RAMhandler.vhd}}

The TT\_RAMhandler is the component that control reads and writes into the RAM
space used for time-tagging pulses. It is subdivided into two separated blocks
of RAM: one for identification of the input and output pulse shape (so called
''ID Block'') and the other one for time-tagging (''TT Block'').

The idea behind seperating the block memories lies in ease the task of updating
the code in case different widths for the ID and TT fields are decided.

\subsection{Behaviour}

Once a pulse has been deglitched, which translates into a delay of
\textit{wb\_clk * cycles to match c\_DEFAULT\_GLITCH\_MASK }, a monostable
will reproduce a pulse with a length determined by the CPL field in CTR0
register. The duration of the output pulse will be hence, \textit{CTR0[CPL] *
wb\_clk}. After this time, a preventive action has been taken to not damage the
coupled inductors in \textbf{CONV-TTL-BLO}. A timeout will be run in which no
input pulse will be replicated. The value of this timeout corresponds to
\textit{CTR0[CPL] * wb\_clk}, which is the same as the outputted pulse.

\begin{description}
\item[Min. Deglitch Mask delay] \textit{wb\_clk * 1}
\item[Max. Deglitch Mask delay] \textit{wb\_clk * bits of
c\_DEFAULT\_GLITCH\_MASK }
\item[Min. input pulse length] \textit{c\_DEFAULT\_GLITCH\_MASK * wb\_clk}
\item[Output pulse length] \textit{CTR0[CPL] * wb\_clk}
\item[Inactivity timeout upon output pulse is done] \textit{CTR0[CPL] * wb\_clk}
\end{description}

\section{Parameters}


\subsection{ \textit{g\_MAX\_GLITCH\_STAGES} }

It specifies the maximum stages used for debouncing an input signal. The input
signal is validated by bit 0 in CTR0. If CRT0[0] is set to 0. Inputs won't be
replicated (it won't even be deglitched).

The value of this parameters express the length in bits of the parameter that
holds the deglitching mask. The value of the Current deGlitching Mask can be
found in CGM in CTR0 register.

\subsection{ \textit{g\_DEFAULT\_GLITCH\_MASK} }

It specifies the default value that it is used for the Current deGlitching Mask
for the CGM field in CTR0 register. Only the lower CGM bits specified by the
values of \textit{g\_MAX\_GLITCH\_STAGES} will be used as deglitching mask. It
should be remarked that the input will be validated against a mask, so values
not monotonical can be accepted. Examples are shown at the end of this document.

\subsection{ \textit{g\_MIN\_PULSE\_LENGTH} }

It specifies the default value that it is used for the Minimum Pulse Length
for the MinPL field in CTR1 register.

This field overrides the value of CPL in CTR0 in case the user tries to
configure an output pulse with a width lower than MinPL. Therefore CTR0 will be
MinPL.\\

\textbf {\textit {BOUNDING MUST BE IMPLEMENTED}}


\subsection{ \textit{g\_MAX\_PULSE\_LENGTH} }

It specifies the default value that it is used for the Maximum Pulse Length
for the MaxPL field in CTR1 register.

This field overrides the value of CPL in CTR0 in case the user tries to
configure an output pulse with a width longer than MaxPL. Therefore CTR0 will be
MaxPL.\\

\textbf {\textit {BOUNDING MUST BE IMPLEMENTED}}

\subsection{ \textit{g\_DEFAULT\_PULSE\_LENGTH} }

It specifies the default value that it is used for the Current Pulse Length
for the CPL field in CTR0 register.

It should be noted that its value is bounded by MinPL and MaxPL fields of CTR1
register.\\

\textbf {\textit {BOUNDING MUST BE IMPLEMENTED}}

\section{Registers}

\subsection{STATUS}
The STATUS register is a read-only register. It shows the basic configuration of
the trigger HDL core and the status of the trigger core RAM blocks.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
 0 & EN & General ENable\\
 \hline
 1 & CLR & General CLeaR\\
 \hline
 3-2 & x & Reserved\\
 \hline
 4 & EN\_TT & Enable Time-Tagging\\
 \hline
 5 & CLR\_TT & CLeaR Time-Tagging\\
 \hline
 7-6 & x & Reserved\\
 \hline
 8 & EMPTY & RAM empty flag\\
 \hline
 9 & FULL & RAM full flag\\
 \hline
 10 & WA & RAM wrapped around\\
 \hline
 15-11 & x & Reserved\\
 \hline
 31-16 & CPL & Current Pulse Length\\
\hline
\end{tabular}

\subsection{CTR0}
The CTR0 register is a read-write register. It allows setting up the basic
configuration of the trigger HDL core, its RAM blocks and both the deglitching
mask and output pulse length to be used.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & CLR & General CLeaR\\
\hline
3-2 & x & Reserved\\
\hline
4 & EN\_TT & Enable Time-Tagging\\
\hline
5 & CLR\_TT & Clear Time-Tagging\\
\hline
7-6 & RDM & time-tagging ReaD Mode\\
\hline
15-8 & CGM & Current Glitch Mask\\
\hline
31-16 & CPL & Current Pulse Length\\
\hline
\end{tabular}

\subsection{CTR1}
The CTR1 register is a read-write register. It allows setting up the boundaries
that override invalid values of CPL field in CTR0.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & MinPL & Minimum Pulse Length\\
\hline
31-16 & MaxPL & Maximum Pulse Length\\
\hline
\end{tabular}

\subsection{RAM0}
The RAM0 register is a read-write register. It allows setting up the RAM
and the read request to it.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN\_TT & Enable Time-Tagging \\
\hline
1 & CLR\_TT & Clear Time-Tagging \\
\hline
3-2 & RDM & time-tagging ReaD mode\\
\hline
4 & EMPTY & RAM empty\\
\hline
5 & FULL & RAM full\\
\hline
6 & WA & RAM Wrapped Around\\
\hline
7 & RQT & ReQuesT read\\
\hline
31-8 & x & Reserved\\ 
\hline
\end{tabular}

\subsection{RAM1}
The RAM1 register is a read-only register. It shows the current read and write
address configured to be accessed.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & CRA & Current Read Address\\
\hline
31-16& CWA & Current Write Address\\
\hline
\end{tabular}

\subsection{RAM2}
The RAM2 register is a read-write register. It allows setting up the RAM adress
range to be read.\\

\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & SA & Starting read Address\\
\hline
31-16 & EA & Ending read Address\\
\hline
\end{tabular}

\pagebreak

\section{Internal Memory Mapping}
The internal registers map is as follow:\\

\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{STATUS} & Read-only\\
\hline
\textbf{0x1} & \textit{CTR0} & Read-write\\
\hline
\textbf{0x2} & \textit{CTR1} & Read-write\\
\hline
\textbf{0x3} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x4} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x5} & \textit{RAM0} & Read-write\\
\hline
\textbf{0x6} & \textit{RAM1} & Read-only\\
\hline
\textbf{0x7} & \textit{RAM2} & Read-write\\
\hline
\end{tabular} 


\section{How to use it}
\subsection{Initialization}

\begin{enumerate}
  \item Disable trigger core before configuring:
  
\textit{CTR0: write 0 to EN and EN\_TT}\\

  \item Set the minimum and maximum pulse lengths:

\textit{CTR1: writes into MinPL and MaxPL}\\

  \item Set the deglitching mask and pulse length to be used:
  
\textit{CTR0: set CGM and CPL}\\

\item Clearing RAM block up before starting:

\textit{RAM0: write 1 to CLR\_TT}\\

\item Disable RAM clearup and enable module:

\textit{CTR0: write 1 to EN and EN\_TT, write 0 to CLR\_TT}\\
 
\end{enumerate}

\subsection{Changing the deglitch mask and stages length}

Three examples are given.\\

\begin {enumerate}
\item[\textbf{Example A}]\\
\begin{itemize}
  \item \textbf{ \textit{g\_MAX\_GLITCH\_STAGES} }: 6
  \item \textbf{ CTR0[CGM] }: 0x0BAA  
\end{itemize}
In this case, only the six less significant bits of CGM field will be used as
mask: ''11 1010''. This mask signal is checked against the sampled input signal.
If it matches, it is considered as a pulse and it will be replicated.\\


\item[\textbf{Example B}]\
The common use will be in the form:
\begin{itemize}
\item \textbf{ \textit{g\_MAX\_GLITCH\_STAGES} }: 6
\item \textbf{ CTR0[CGM] }: 0xFFFF
\end{itemize}

Which translates into \textit{pulses of length \textbf{6 * wb\_clk } or greater should
be replicated}.\\

\item[\textbf{Example C}]\
Reducing the Deglitch Mask delay is achieved by configuring CGM
properly:
\begin{itemize}
\item \textbf{ \textit{g\_MAX\_GLITCH\_STAGES} }: 6
\item \textbf{ CTR0[CGM] }: 0x0007
\end{itemize}

which means \textit{pulses of length \textbf{3 * wb\_clk} or greater should be
replicated}.
\end{enumerate}

\subsubsection{Register writes step-by-step}
\begin{enumerate}
  \item Disable trigger core before configuring:
  
\textit{CTR0: write 0 to EN and EN\_TT}\\

  \item Set the minimum and maximum pulse lengths:

\textit{CTR1: writes into MinPL and MaxPL}\\

  \item Set the deglitching mask and pulse length to be used:
  
\textit{CTR0: set CGM and CPL}\\

\item Reenable module:

\textit{CTR0: write 1 to EN and EN\_TT}\\
\end{enumerate}

\subsection{Changing the pulse width}

\begin{enumerate}
  \item Disable trigger core before configuring:
  
\textit{CTR0: write 0 to EN and EN\_TT}\\

  \item Check/set the minimum and maximum pulse lengths:

\textit{CTR1: read/write into MinPL and MaxPL}\\

  \item Set the pulse length to be used:
  
\textit{CTR0: set CPL}\\

\item Reenable module:

\textit{CTR0: write 1 to EN and EN\_TT}\\
\end{enumerate}

\end{document}
