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\begin{document}

\title{\textbf{CONV-TTL-BLO \\ User Guide}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
    \begin{center}
      \includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
    \end{center}
\end{figure}

\begin{abstract}
This document describes the CONV-TTL-BLO board, a Blocking pulse repetitor
board in double height VME format. It replaces all the following boards:
\begin{itemize}
  \item 8 channel repeater
  \item 16 channel repeater
  \item CTDAC
  \item LA-BLO-TTL
  \item LAF-BLO-TTL
  \item LASB-TTL-BLO
  \item LA-GATE
  \item LA-TTL-BLO
  \item LAPF-TTL-BLO\footnote{For replacing this board a pulse width of 4us
  must be set.}
\end{itemize}
\end{abstract}

\maketitle{}
\pagebreak

\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak

\listoffigures
\listoftables
\pagebreak

\pagenumbering{arabic}
\setcounter{page}{1}
\pagebreak
\section{Introduction}

CONV-TTL-BLO is a board intended for replicating Blocking Pulses, offering six
totally independent replication channels. The shape of the pulses is defined in
\cite{StandardBlocking}. CONV-TTL-BLO works together with two more boards:
CONV-TTL-RTM and CONV-TTL-RTM-BLO.\\

CONV-TTL-BLO holds all the active circuitry
and it is connected as a Front Module to a VME64 backplane. The ports offered
in the Front Panel are explained in the next section.\\

\begin{figure}[!htdp]
    \begin{center}
      \includegraphics[scale=0.55, keepaspectratio]{Figures/BLOschema.png}
      \caption{Pulse Repetition system}
      \label{prs}
    \end{center}
\end{figure}

CONV-TTL-RTM and CONV-TTL-RTM-BLO are both connected to the rear part of the
crate and provide, in the rear panel, the connectivity of the I/O Blocking
lines.
Every channel offers, in the Rear Panel, three Blocking Pulse outputs and one
Blocking Pulse input.\\


CONV-TTL-RTM is a motherboard attached to the Rear Transition Module of the P2
VME64 connector. It connects CONV-TTL-BLO to CONV-TTL-RTM-BLO and
provides overvoltage protection for all the I/Os of all the channels.\\

CONV-TTL-RTM-BLO is a piggyback board mounted on CONV-TTL-RTM. It holds all the
LEMO 00 connectors and channel LEDs that are offered in the Rear Panel.

\begin{table}[htdp]
\begin{center}
%\begin{turn}{90}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Board} & \textbf{Connection}& \textbf{Ports}\\
\hline
\hline
\textit{CONV-TTL-BLO} & Front & SFP\\
  &  & TTL Blocking triggers\\
  &  & TTL Blocking output replica\\
  &  & inverters \\
\hline
\textit{CONV-TTL-RTM} & Back & - \\
\hline
\textit{CONV-TTL-RTM-BLO} & Back & Blocking Pulse input\\
&& Blocking Pulse outputs\\
\hline
\end{tabular}
\caption{Boards for Blocking repetition}
\label{boards}
%\end{turn}
\end{center}
\end{table}

\pagebreak
\section{Board Ports}
CONV-TTL-BLO consist of several ports, divided in three sections (from top to
bottom as shown in Figure~\ref{fp}):
\begin{itemize}
  \item SFP connector: \textbf{[A]}.
  \item Blocking connectors: \textbf{[B]} and \textbf{[C]}.
  \item General Purpose connectors: \textbf{[D]} and \textbf{[E]}.
\end{itemize}


\subsection{TTL-triggers}
They correspond to the block \textbf{[B]} in Figure~\ref{fp}. The connectors are
LEMO 00.
By connecting an external trigger source to one of the connectors a pulse can be
replicated, either in a Blocking Pulse level in the Rear Panel or in a TTL panel
in the Front Panel.

\begin{table}[htdp]
\begin{center}
\begin{tabular}{|l|l|l|c|c|}
\hline
\textbf{Name} & \textbf{Type} & \textbf{Level} & \textbf{Internal} &
\textbf{Location}\\
&&&\textbf{Termination} &\\
\hline
\hline
CH1 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B] \\
\hline
CH2 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH3 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH4 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH5 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH6 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
\end{tabular}
\caption{TTL-triggers Front Panel inputs}
\label{trigFP}
\end{center}
\end{table}

\subsection{TTL-level Blocking pulses replica}
They correspond to the block \textbf{[C]} in Figure~\ref{fp}. The connectors are
LEMO 00.
From these connectors a TTL-level Blocking Pulse replica of the Rear Panel
outputs if offered to the Front Panel. The pulse width of this output is
similar to the pulse outputted in the Rear Panel; however, the rise time and top
pulse level are obviously different from the Blocking output.\\
Once pulse is outputted, the LED of the corresponding channel blinks for 500
ms.\\
A summary of all the connector of this kind is found in Figure~\ref{replicaFP}.

\begin{table}[htdp]
\begin{center}
\begin{tabular}{|l|l|l|c|c|}
\hline
\textbf{Name} & \textbf{Type} & \textbf{Level} & \textbf{Internal} &
\textbf{Location}\\
&&&\textbf{Termination} &\\
\hline
\hline
CH1 OUT & Pulsed & TTL & No & [C]\\
\hline
CH2 OUT & Pulsed & TTL & No & [C]\\
\hline
CH3 OUT & Pulsed & TTL & No & [C]\\
\hline
CH4 OUT & Pulsed & TTL & No & [C]\\
\hline
CH5 OUT & Pulsed & TTL & No & [C]\\
\hline
CH6 OUT & Pulsed & TTL & No & [C]\\
\hline
\end{tabular}
\caption{TTL-level Blocking pulses Front Panel output}
\label{replicaFP}
\end{center}
\end{table}

\subsection{SFP connector}
It is marked in Figure~\ref{fp} as \textbf{[A]}. If the cable is plugged-in the
socket, \textit{White Rabbit} precise time-stamping can be obtained in
CONV-TTL-BLO. Three LEDs above the connector show the status of the
\textit{White Rabbit} link.
\subsection{General pupose}
In the lower part of the Front Panel (\textbf{[D]} and \textbf{[E]} in
Figure~\ref{fp}) can be found four dedicated inverters. The output is a TTL inverted version of
the TTL input.

\begin{table}[htdp]
\begin{center}
\begin{tabular}{|l|l|l|c|c|}
\hline
\textbf{Name} & \textbf{Type} & \textbf{Level} & \textbf{Internal} &
\textbf{Location}\\
&&&\textbf{Termination} &\\
\hline
\hline
\multicolumn{5}{|c|}{\textbf{General Purpose Inputs}}\\
\hline
INV A IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
INV B IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
INV C IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
INV D IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
\hline
\multicolumn{5}{|c|}{\textbf{General Purpose Inverted Outputs}}\\
\hline
INV A OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
INV B OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
INV C OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
INV D OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
\end{tabular}
\caption{General pupose Front Panel IOs}
\label{gpFP}
\end{center}
\end{table}


\pagebreak
\subsection{Front Panel}
\begin{figure}[!htdp]
    \begin{center}
      \includegraphics[scale=0.75, keepaspectratio]{Figures/FrontPanel.png}
      \caption{CONV-TTL-BLO Front Panel}
      \label{fp}
    \end{center}
\end{figure}


\pagebreak
\section{Board Addressing}

Communication with the FPGA is done via I2C interface through SERA and SERB pins
in P1 VME64x connectors. In order to access one card inside a certain crate, it
is necessary to set:

\begin{itemize}
  \item An \textbf{I2C address}. Every CONV-TTL-BLO has an I2C address that
  equals the Geographical Address of the slot according to VME64x specifications. It is
  7 bits width.
  \item An \textbf{internal CONV-TTL-BLO address}. It is a short integer (16
  bits) in big endian format.
\end{itemize}

%\subsection{Write command}

%\begin{table}[htdp]

%\begin{tabular}{|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|}
%\hline
%7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%\multicolumn{7}{|c|}{I2C ADDRESS} & RD\textbackslash\\
%\multicolumn{7}{|c|}{} & WRN\\
%\hline
%\end{tabular}

%\vspace{12pt}

%\begin{tabular}{|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|}
%\hline
%7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%\multicolumn{7}{|c|}{I2C ADDRESS} & RD\textbackslash\\
%\multicolumn{7}{|c|}{} & WRN\\
%\hline
%\end{tabular}

%\vspace{12pt}

%\begin{tabular}{|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|}
%\hline
%7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%\multicolumn{7}{|c|}{I2C ADDRESS} & RD\textbackslash\\
%\multicolumn{7}{|c|}{} & WRN\\
%\hline
%\end{tabular}

%\caption{General pupose Front Panel IOs}
%\label{gpFP}
%\end{table}

\pagebreak
\section{Functional Description}

The task of CONV-TTL-BLO is to output a Blocking Pulse upon a reception of a
trigger is received.

As stated before, CONV-TTL-BLO works together with
CONV-TTL-RTM and CONV-TTL-RTM-BLO which are both in the rear part of the crate.
The system formed by this three boards offers three independent channels for
outputting Blocking Pulses. Refer to Figure~\ref{prs} for a visual,
whole-system, description.

CONV-TTL-BLO allows the user to set propierties for the pulse replication
and receive information above the latest events logged in the board.

\subsection{Trigger sources}
There are two sources for triggering in every channel: one coming from the
Front Panel (CONV-TTL-BLO) and other coming from the Rear Panel
(CONV-TTL-RTM through CONV-TTL-RTM-BLO).

The trigger policy is that \emph{a Blocking pulse will be outputted whenever
either a trigger in the Front Panel or the Rear Panel is detected}:\\

\begin{table}[htdp]
\begin{center}
\begin{tabular}{|c|c|c|}
\hline
\textbf{Trigger} & \textbf{Board} & \textbf{Connection}\\
\hline
\hline
TTL & CONV-TTL-BLO & Front Panel\\
\hline
Blocking & CONV-TTL-RTM-BLO & Rear Panel\\
\hline
\end{tabular}

\vspace{0.5cm}

\begin{tabular}{|c|}
\hline
\textbf{Global trigger is OR function of the two sources above}\\
\hline
\end{tabular}
\caption{Trigger sources}
\label{ts}
\end{center}
\end{table}




\pagebreak
\section{Memory Map}

\begin{table}[!htpd]
\begin{center}
\begin{turn}{90}
\begin{tabular}{|p{2cm}|p{2cm}|p{2cm}|p{3cm}|p{6cm}|}
\hline
\textbf{Channel} & \textbf{Address} & \textbf{Data type} & \textbf{Name} &
\textbf{Comment}\\
\hline
\hline
\multirow{2}{*}{Access} & 0x0101 & Bit pattern & CTR0\_ACCESS & Control device
access 0\\\cline{2-5}
&0x0102 & Bit pattern & ACTR1 & Control device access 1 \\
\hline
\hline
\multirow{2}{*}{I2C} & 0x0202 & Bit pattern & CTR0\_I2C & I2C control
0\\\cline{2-5} & 0x0203 & Bit pattern & I2C\_CTR1 & I2C control 1\\
\hline
\hline
\multirow{5}{*}{Ch 1} & 0x0301 & Bit pattern & CTR0\_CH1 & Channel 1
control\\\cline{2-5}
& 0x0302 & Integers & CTR1\_CH1 & Channel 1 min/max Pulse
length\\\cline{2-5}
& 0x0305 & Bit pattern & RAM0\_CH1 & RAM control Channel 1\\\cline{2-5}
& 0x0306 & Bit pattern & RAM1\_CH1 & Current read/write Address
pointers\\\cline{2-5}
& 0x0307 & Bit pattern & RAM2\_CH1 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 2} & 0x0401 & Bit pattern & CTR0\_CH2 & Channel 
control\\\cline{2-5}
& 0x0402 & Integers & CTR1\_CH2 & Channel 2 min/max Pulse
length\\\cline{2-5}
& 0x0405 & Bit pattern & RAM0\_CH2 & RAM control Channel 2\\\cline{2-5}
& 0x0406 & Bit pattern & RAM1\_CH2 & Current read/write Address
pointers\\\cline{2-5}
& 0x0407 & Bit pattern & RAM2\_CH2 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 3} & 0x0501 & Bit pattern & CTR0\_CH3 & Channel 3
control\\\cline{2-5}
& 0x0502 & Integers & CTR1\_CH3 & Channel 3 min/max Pulse
length\\\cline{2-5}
& 0x0505 & Bit pattern & RAM0\_CH3 & RAM control Channel 3\\\cline{2-5}
& 0x0506 & Bit pattern & RAM1\_CH3 & Current read/write Address
pointers\\\cline{2-5}
& 0x0507 & Bit pattern & RAM2\_CH3 & Start/end read address\\
\hline
\end{tabular}
\end{turn}
\end{center}
\caption{CONV-TTL-BLO Memory map I/II}
\label{mmap1}
\end{table}

\begin{table}[!htpd]
\begin{center}
\begin{turn}{-90}
\begin{tabular}{|p{2.25cm}|p{2cm}|p{2cm}|p{3cm}|p{6cm}|}
\hline
\textbf{Channel} & \textbf{Address} & \textbf{Data type} & \textbf{Name} &
\textbf{Comment}\\
\hline
\hline
\multirow{5}{*}{Ch 4} & 0x0601 & Bit pattern & CTR0\_CH4 & Channel 4
control\\\cline{2-5}
& 0x0602 & Integers & CTR1\_CH4 & Channel 4 min/max Pulse
length\\\cline{2-5}
& 0x0605 & Bit pattern & RAM0\_CH4 & RAM control Channel 4\\\cline{2-5}
& 0x0606 & Bit pattern & RAM1\_CH4 & Current read/write Address
pointers\\\cline{2-5}
& 0x0607 & Bit pattern & RAM2\_CH4 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 5} & 0x0701 & Bit pattern & CTR0\_CH5 & Channel 5
control\\\cline{2-5}
& 0x0702 & Integers & CTR1\_CH5 & Channel 5 min/max Pulse
length\\\cline{2-5}
& 0x0705 & Bit pattern & RAM0\_CH5 & RAM control Channel 5\\\cline{2-5}
& 0x0706 & Bit pattern & RAM1\_CH5 & Current read/write Address
pointers\\\cline{2-5}
& 0x0707 & Bit pattern & RAM2\_CH5 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 6} & 0x0801 & Bit pattern & CTR0\_CH6 & Channel 6
control\\\cline{2-5}
& 0x0802 & Integers & CTR1\_CH6 & Channel 6 min/max Pulse
length\\\cline{2-5}
& 0x0805 & Bit pattern & RAM0\_CH6 & RAM control Channel 6\\\cline{2-5}
& 0x0806 & Bit pattern & RAM1\_CH6 & Current read/write Address
pointers\\\cline{2-5}
& 0x0807 & Bit pattern & RAM2\_CH6 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Multiboot} & 0x0901 & Bit pattern & CTRL0 & Multiboot operation
control\\\cline{2-5}
& 0x0904 & Integer & GENERAL1 & Lower bits 1$^{st}$ bitstream
address\\\cline{2-5} & 0x0905 & Bit pattern & GENERAL2 & Lower bits 1$^{st}$
bitstream address\\\cline{2-5}
& 0x0906 & Integer & GENERAL3 & Higher bits 2$^{nd}$ bitstream
address\\\cline{2-5}
& 0x0907 & Bit pattern & GENERAL4 & Higher bits 2$^{nd}$ bitstream
address\\\cline{2-5}
\hline
\hline
\multirow{2}{*}{EEPROM} &&&&\\\cline{2-5}
&&&&\\
\hline
\multirow{2}{*}{White Rabbit} &&&&\\\cline{2-5}
&&&&\\
\hline
\end{tabular}
\end{turn}
\end{center}
\caption{CONV-TTL-BLO Memory map II/II}
\label{mmap2}
\end{table}


\pagebreak
\section{Register Description}

\subsection{Access Registers}
\subsubsection{CTR0\_ACCESS}

The \textit{CTR0} register is a read-write register that enable and disable
access to Wishbone devices in the memory map.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | l |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR0\_ACCESS}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0  & EN0  &  ENable access to device 0  in memory map\\
\hline
1  & EN1  &  ENable access to device 1  in memory map\\
\hline
2  & EN2  &  ENable access to device 2  in memory map\\
\hline
3  & EN3  &  ENable access to device 3  in memory map\\
\hline
4  & EN4  &  ENable access to device 4  in memory map\\
\hline
5  & EN5  &  ENable access to device 5  in memory map\\
\hline
6  & EN6  &  ENable access to device 6  in memory map\\
\hline
7  & EN7  &  ENable access to device 7  in memory map\\
\hline
8  & EN8  &  ENable access to device 8  in memory map\\
\hline
9  & EN9  &  ENable access to device 9  in memory map\\
\hline
10 & EN10 &  ENable access to device 10 in memory map\\
\hline
11 & EN11 &  ENable access to device 11 in memory map\\
\hline
31-13 & x &  Reserved \\
\hline
\end{tabular}\\
\caption{CTR0\_ACCESS Register}
\label{ctr0access}
\end{center}
\end{table}

\subsubsection{CTR1\_ACCESS}

The \textit{CTR1} register is a read-write register that enable and disable
read and write permissions to Wishbone devices in the memory map.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | l |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR1\_ACCESS}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0  & GWR & General write permissions\\
\hline                    
1  & GRD & General read  permissions\\
\hline
2  & WR0 & WRite permissions in memory map 0\\
\hline
3  & RD0 &  ReaD permissions in memory map 0\\
\hline
4  & WR1 & WRite permissions in memory map 1\\
\hline
5  & RD1 &  ReaD permissions in memory map 1\\
\hline
6  & WR2 & WRite permissions in memory map 2\\
\hline
7  & RD2 &  ReaD permissions in memory map 2\\
\hline
8  & WR3 & WRite permissions in memory map 3\\
\hline
9  & RD3 &  ReaD permissions in memory map 3\\
\hline
10 & WR4 & WRite permissions in memory map 4\\
\hline
11 & RD4 &  ReaD permissions in memory map 4\\
\hline
12 & WR5 & WRite permissions in memory map 5\\
\hline
13 & RD5 &  ReaD permissions in memory map 5\\
\hline
14 & WR6 & WRite permissions in memory map 6\\
\hline
15 & RD6 &  ReaD permissions in memory map 6\\
\hline
16 & WR7 & WRite permissions in memory map 7\\
\hline
17 & RD7 &  ReaD permissions in memory map 7\\
\hline
18 & WR8 & WRite permissions in memory map 8\\
\hline
19 & RD8 &  ReaD permissions in memory map 8\\
\hline
20 & WR9 & WRite permissions in memory map 9\\
\hline
21 & RD9 &  ReaD permissions in memory map 9\\
\hline
22 & WR10 & WRite permissions in memory map 10\\
\hline
23 & RD10 &  ReaD permissions in memory map 10\\
\hline
24 & WR11 & WRite permissions in memory map 11\\
\hline
25 & RD11 &  ReaD permissions in memory map 11\\
\hline
31-26 & x & Reserved\\
\hline
\end{tabular}
\caption{CTR1\_ACCESS Register}
\label{ctr1access}
\end{center}
\end{table}

\pagebreak
\subsection{I2C Registers}
\subsubsection{CTR0\_I2C}

The CTR0 register is a write-read register. It controls the indirect addres
and holds the I2C address (which in the case of \textit{CONV-TTL-BLO} will be
connected to VME64x geographical address pins).\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR0\_I2C}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & general ENable\\
\hline
1 & RST & general ReSeT\\
\hline
2 & PEN & Prescaler ENable\\
\hline
5-3 & x & Reserved\\
\hline
7-6 & BIA & Bytes Indirect Addressing\\
\hline
14-8 & A[6:0] & I2C address\\
\hline
15 & x & Reserved\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\caption{CTR0\_I2C Register}
\label{ctr0I2C}
\end{center}
\end{table}

\subsubsection{CTR1\_I2C}

The CTR1 register is a write-read register. It shows the fsm of the separate
\textit{read} and \textit{write} fsms.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR1\_I2C}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & RDS & fsm status: ReaD Status\\
\hline
15-8 & WDS & fsm status: WRite Status\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\caption{CTR1\_I2C Register}
\label{ctr1I2C}
\end{center}
\end{table}

\pagebreak
\subsection{Channel Registers}
\subsubsection{CTR0\_CH[x]}

The CTR0\_CH[x] register is a read-write register. It allows setting up the
basic configuration of the trigger HDL core, its RAM blocks and both the deglitching
mask and output pulse length to be used.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR0\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & CLR & General CLeaR\\
\hline
3-2 & x & Reserved\\
\hline
4 & EN\_TT & Enable Time-Tagging\\
\hline
5 & CLR\_TT & Clear Time-Tagging\\
\hline
7-6 & RDM & time-tagging ReaD Mode\\
\hline
15-8 & CGM & Current Glitch Mask\\
\hline
31-16 & CPL & Current Pulse Length\\
\hline
\end{tabular}
\caption{CTR0\_CH[x] Register}
\label{ctr0ch}
\end{center}
\end{table}

\subsubsection{CTR1\_CH[x]}

The CTR1\_CH[x] register is a read-write register. It allows setting up the
boundaries that override invalid values of CPL field in CTR0.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR1\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & MinPL & Minimum Pulse Length\\
\hline
31-16 & MaxPL & Maximum Pulse Length\\
\hline
\end{tabular}
\caption{CTR1\_CH[x] Register}
\label{ctr1ch}
\end{center}
\end{table}

\subsubsection{RAM0\_CH[x]}

The RAM0 register is a read-write register. It allows setting up the RAM
and the read request to it.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{RAM0\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN\_TT & Enable Time-Tagging \\
\hline
1 & CLR\_TT & Clear Time-Tagging \\
\hline
3-2 & RDM & time-tagging ReaD mode\\
\hline
4 & EMPTY & RAM empty\\
\hline
5 & FULL & RAM full\\
\hline
6 & WA & RAM Wrapped Around\\
\hline
7 & RQT & ReQuesT read\\
\hline
31-8 & x & Reserved\\ 
\hline
\end{tabular}
\caption{RAM0\_CH[x] Register}
\label{ram0ch}
\end{center}
\end{table}


\subsubsection{RAM1\_CH[x]}

The RAM1 register is a read-only register. It shows the current read and write
address configured to be accessed.\\


\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{RAM1\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & CRA & Current Read Address\\
\hline
31-16& CWA & Current Write Address\\
\hline
\end{tabular}
\caption{RAM1\_CH[x] Register}
\label{ram1ch}
\end{center}
\end{table}

\subsubsection{RAM2\_CH[x]}

The RAM2 register is a read-write register. It allows setting up the RAM adress
range to be read.\\

\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{RAM2\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & SA & Starting read Address\\
\hline
31-16 & EA & Ending read Address\\
\hline
\end{tabular}
\caption{RAM2\_CH[x] Register}
\label{ram2ch}
\end{center}
\end{table}

\subsection{Multiboot Registers}

\subsection{White Rabbit Registers}

\pagebreak
\section{Installation}

\bibliographystyle{unsrt}
\bibliography{userGuide}
\end{document}
