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\title{\textbf{{\LARGE CONV-TTL-BLO\\\textit{Standard Blocking Repeater in
VME64x Format}\\\Large
Functional Specifications}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
   \begin{center}
      \includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
   \end{center}
\end{figure}

\begin{abstract}
The present document gathers the functional specifications of the CONV-TTL-BLO
project, EDA-02446.\\

\textbf{History of changes}\\

This document version has been checked by:\\

This document version has been approved by:\\
\begin{center}
\begin{tabular}{|p{3.5cm}|p{2.5cm}|p{5cm}|}
\hline
\textbf{Date} & \textbf{Pages} & \textbf{Changes}\\ 
\hline
\hline
 September 14, 2011 & All & Initial submission.\\
 \hline
 September 21, 2011 & All & Added references to Standard Blocking.\\
 \hline
 August 21, 2012    & All & Specifications up-to-date.\\
                    &     & Namings corrected.\\
\hline
\end{tabular}
\end{center}
\end{abstract}

\pagebreak


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\paragraph{Acknowledgements}
This document agregates the functional specifications of the
TTL, inverted-TTL and Standard Blocking \cite{StandardBlocking} to Standard
Blocking output repeater, \textbf{CONV-TTL-BLO}, for the substitution of the following boards:  8 and 16 Channel Repeaters, Level
Converter and LASB-TTL-BLO.
\paragraph{System Description and Purpose}
The Standard Blocking Pulse Converter is a set of two VME64x boards which has
6 channel repeaters. Each channel repeater is a device able to translate TTL and inverted-TTL signals
into Standard Blocking pulses and regenerate Standard Blocking ones. Differing
from previous versions, a FPGA is included in the Pulse Converter to add control to the
repeater and communication through a serial interface in the VME64x connector. 
The aim of this document is setting the specifications needed for the
renovation of these devices due to the difficulties faced when it comes to maintenance and
repairing.

\pagebreak

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\tableofcontents
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\section{General schema}
\subsection{CERN Repetitors needs}
The main goal in the design of the Standard Blocking Repeater is fulfulling the
needs of replacing Blocking Repetitors in CERN. According to the documentation
provided by Emmanuel Said, the following number of repetitors are currently installed at
CERN:\\

\begin{center}
\begin{tabular}{|c|c|}
\hline
\textbf{input} & \textbf{amount}\\
\hline
\hline
\multicolumn{2}{|c|}{\textbf{8 Channel Repeaters}}\\
\hline
TTL & 19\\
\hline
inverted-TTL & 202\\
\hline
Blocking $t_P = 1   \mu{}s $ & 7\\
\hline
Blocking $t_P = 1.2 \mu{}s $ & 141\\
\hline
LA-GATE & 11\\
\hline
\multicolumn{2}{|c|}{\textbf{16 Chanel Repeaters}}\\
\hline
Blocking & 60\\
\hline
\end{tabular}
\end{center}

\subsection{Front and Rear boards}
The Standard Blocking Pulse Converter consists of three boards: CONV-TTL-BLO,
CONV-TTL-RTM and CONV-TTL-RTM-BLO . The decision of splitting up the Pulse
Converter lies in easing substition and repairing of damaged parts and help the
operator in interconnecting the inputs and the outputs.\\

A Pulse Converter can host a maximum of 6 channel repeaters due to the size
limitations of the Rear Panel dimensions.\\

The Front Board, CONV-TTL-BLO is the board that holds the major part of active
components, such as the FPGA and the Pulse Converter Units. This board is
responsible of controlling and monitoring the Pulse Converter activity.\\

\begin{figure}[htb]
    \begin{center}
      \includegraphics[scale=0.57, keepaspectratio]{Figures/BLOschema.png}
      \caption{Functional block schema}
    \end{center}
\end{figure}
\pagebreak

The Rear Board system is composed of a Rear Transistion Module (CONV-TTL-RTM)
which acts as a completely passive motherboard to the mezzanine for the Rear Panel
(CONV-TTL-RTM-BLO) which holds all the inputs and outputs.\\

\begin{center}
   \begin{tabular}{|c|c|c|c|}
      \hline
      \textbf{Board} & \textbf{Location} & \textbf{Parts} &
      \textbf{Connectivity}\\
      \hline
      \hline
      \textbf{CONV-TTL-} &&&\\
      \textbf{BLO}     & FRONT & Active  & VME64x Serial Control Lines\\
      \hline
      \textbf{CONV-TTL-} &&&\\
      \textbf{RTM}     & REAR  & Passive & Motherboard\\
      \hline
      \textbf{CONV-TTL-}    &&&\\
      \textbf{RTM-BLO}& ubindexEAR & Passive & Input\textbackslash Output Connectors\\
      \hline
   \end{tabular}
\end{center}

\section{Panels}
\subsection{Front Panel: CONT-TTL-BLO}
The front board, CONV-TTL-BLO, offers in the Front Panel:
\begin{itemize}
  \item Power OK, System Fail LEDs and input signal (TTL or TTL\_N) indicator.
  \item An SFP connector to allow precise timestamping via White Rabbit.
  \item Three White Rabbit Status LEDs.
  \item For every channel: a pulse activity indicator and TTL level input/output
  connectors.
\end{itemize}
\subsection{Rear Panel: CONV-TTL-RTM-BLO}
The Rear Board, CONV-TTL-RTM-BLO, offers in the Rear Panel:
\begin{itemize}
  \item The Rear Panel must hold six channels. Each channel has four
  connectors: one input, three outputs.
  \item Every channels has a LED indicator, in the fashion as in the front
  panel.
\end{itemize}

\pagebreak

\section{Power-up and System Monitoring}
The System Monitor Unit consists on a HDL core that control critical parts of
both the front and rear boards.
\subsection{Power Supplies}
The power supply domains must be monitored by the FPGA trough a DAC and a
power-up sequence must be specified so as to improve reliability. Reports must
be available through VME64x serial lines.
\subsection{Board Temperature}
The board temperature must be monitored by the FPGA.  Reports must
be available through VME64x serial lines.


\pagebreak
\section{FPGA Control and Pulse Converter Unit}
FPGA control will handle all the system logs of the input pulses and parameters
of the output ones: pulse width and time between pulses.
The configuration of this two paramters is important in two aspects:
\begin{description}
\item[Pulse width] Initially the output pulse width is set to 1.2 $\mu$$s$,
following the Standard Blocking definition \cite{StandardBlocking}. Input pulses
wider than 1.2 $\mu$$s$ will be cropped to 1.2 $\mu$$s$ output ones. However, as
different applications could require different pulse width, a configuration
register in the FPGA will be used to add this functionality.\\In electrical
terms, changing the pulse width out of bounds will produce that the current in
the transformer will be higher than the saturation current. In this case,
irreversible damage will be produced. HDL control must take care of this issue.
\item[Time between pulses] Initially the time between pulses is set to 
2 $\mu$$s$. Any pulse received within this time frame after a pulse was
outputted will not be regenerated and registered as "Time between pulses violation" in the HDL control.\\It is
important to monitor this parameter because it can produce physical damage to
the transformer. Due to the remaining magnetizing current built up during the
pulse on state, the circuit needs time to draining it off thanks
to a snubber circuit. Subsequently, time between pulses is dependent of the
pulse width and must be set so as to not leave too much remaining current in the
transformer. If the remaining current is not low and input pulses are received
too often, the transformer current can build above the saturation one producing
irreversible damage.

\end{description}
\subsection{Board ID}
A Board ID must be specified to distinguish between different hardware versions
of the Front and Read Board. By reading the value of the board ID, different
approaches can be taken in the HDL control. For instance, if we consider that a
manufacturer is not able to dispatch a 1m$H$ primary inductance transformer so
that it must be replaced for a 470 $\mu$$H$ one, both the \textit{pulse width}
and \textit{time between pulses} parameters must be adapted to this different
part.
\subsection{HDL control}
The FPGA control is governed by a HDL core which must calculate the bounds of
the \textit{pulse width} and \textit{time between pulses} parameters
depending on the Board ID.\\ Then, as previously stated, it must monitor 
the \textit{input pulse width} and eventually correct the \textit{time between
pulses} so as to avoid damage to the output pulse transformer due to the
remaining magnetizing current.\\
Furthermore, an event log should be carried out so that it can be reported back
through either serial VME64x P1 lines or front USB connector.
\subsection{Pulse Converter Unit}
The Pulse Converter Unit is the part of the circuit that receives and
adapt the input signal to the FPGA and converts a control signal from the FPGA
to Standard Blocking output -it goes to the Rear Panel- and TTL --it goes to the
Front Panel.
\subsubsection{Input}
TTL, inverter-TTL and Standard Blocking levels must be translated to pass the
signal to the FPGA. \emph{Due to attenuation produced for the long distance
connections made, signals that were outputted as Standard Blocking levels will
be accepted if the received high level is above 10V}. Protection
Circuitry must be used. External line termination should be placed.
\subsubsection{Output}
The output circuity must generate a Standard Blocking signal
\cite{StandardBlocking} compliant:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Pulse Width} & \textbf{Pulse Height} & \textbf{Rise Time} & \textbf{Fall
Time}\\
\hline
1.2 $\mu{}s$ & 24V & 150 $\pm$ 75 $ns$ & 150 $\pm$ 75 $ns$\\
\hline
\end{tabular}
\end{center}
it should be noted that the \textit{Pulse Width} can be configured within the
Standard Blocking pulse width range.
\pagebreak
\section{On board memory and FPGA reprogramming}
A PROM memory must be installed to hold the FPGA bitstream. The size of the PROM
memory should be at least the required to install two uncompressed FPGA
bitstreams.\\
FPGA can be reprogrammed through the external JTAG interface or by means of the
VME64x serial connection.
\pagebreak
\section{Testing methodologies}
The testing process of the FPGA should cover the following areas:
\begin{itemize}
  \item Testbench of the HDL power-up related code --power domains, daisy-chain
  configuration.
  \item Testbench of the HDL control circuit.
  \item Verification of the input reflection.
  \item Verification of the output pulse shape.
\end{itemize}
\pagebreak

\pagebreak
\bibliographystyle{unsrt}
\bibliography{Functional}
\end{document}
