----------------------------------------------------------------------------------
-- Company:        CERN, BE-CO-HT 
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    10:33:33 31/06/2012
-- Design Name:    FIFO, fixed depth to one
-- Module Name:    FIFO_simple - Behavioral 
-- Project Name:   CTDAH
-- Target Devices: Spartan 6
-- Tool versions: 
-- Description:    This module implements a generic FIFO of lenght one.
--
--    input--->    
--             |   REG 0  | ---> reg_o LSB
--             |__________|
--          
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity FIFO_simple is
   generic(
      g_data_width  : NATURAL := 8
   );
   port (
      reg_i  : in   STD_LOGIC_VECTOR (g_data_width - 1 downto 0);
      clk    : in   STD_LOGIC;
      push   : in   STD_LOGIC;
      flush  : in   STD_LOGIC;
      reg_o  : out  STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
   );
end FIFO_simple;

architecture Behavioral of FIFO_simple is

begin
  
   reg_proc: process(clk)
   begin

      if rising_edge(clk) then
         if flush = '1' then
            reg_o      <= (others => '0');
         elsif push = '1' then
            reg_o      <= reg_i;
         else
         end if;
      end if;

   end process;

end Behavioral;
