---------------------------------------------------------------------------------
-- Company:        CERN, BE-CO-HT
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    09:58:06 10/12/2011 
-- Design Name:    HDL trigger
-- Module Name:    trigger - Behavioral 
-- Project Name:   CTDAH
-- Target Devices: Spartan 6
-- Tool versions: 
-- Description:    This is the wishbone trigger which receives a debounced input
--                 and outputs a trigger signal for the pulse converter
-- Dependencies:   none
--
-- Revision: 
-- Revision 0.1
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.ctdah_pkg.ALL;

entity basic_trigger_core is
  port (
         wb_rst_i       : in  STD_LOGIC;
         wb_clk_i       : in  STD_LOGIC;

         pulse_i        : in  STD_LOGIC;
         pulse_o        : out STD_LOGIC;
         pulse_n_o      : out STD_LOGIC;

         crop_o         : out STD_LOGIC;

         led_o          : out STD_LOGIC
      );
end basic_trigger_core;

architecture Behavioral of basic_trigger_core is

   signal s_pulse               : STD_LOGIC;

   signal s_deglitched_pulse    : STD_LOGIC;
   signal s_deglitched_pulse_d0 : STD_LOGIC;

   signal s_pulse_parity        : STD_LOGIC;

begin

   s_pulse        <= pulse_i;

  inst_debo: gc_debouncer
  generic map( g_LENGTH  => 2)
  port map(rst         => wb_rst_i,
           clk         => wb_clk_i,
           input       => s_pulse,
           output      => s_deglitched_pulse,
           glitch_mask => "11");

  pulse_monostable : gc_simple_monostable
  generic map (g_PULSE_LENGTH => 195) --! Produce 1us sharp at the output
  port map (rst      => wb_rst_i, 
            clk      => wb_clk_i, 
            input    => s_deglitched_pulse, 
            output   => pulse_o,
            output_n => pulse_n_o);

  led_monostable : gc_simple_monostable
  generic map (g_PULSE_LENGTH => 10000000) --! 250ms
  port map (
          rst      => wb_rst_i, 
          clk      => wb_clk_i, 
          input    => s_deglitched_pulse, 
          output   => led_o);
  --output_n not connected

end Behavioral;
