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CONV-TTL-BLO v2 schematics review 16.10.2012
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MEETING SUMMARY

  + DATE           10.10.2012    15:30 - 17:00
                   18.10.2012
                   19.10.2012
  + PLACE          CERN Prevessin, Building 864, Room 2-A15
  + SUBJECT        CONV-TTL-BLO v2 Review
  + SVN            http://www.ohwr.org/projects/conv-ttl-blo/wiki 
  + REVISION       0
  + PARTICIPANTS:
      Van der Bij, Erik          EVB    Erik.van.der.Bij@cern.ch 
      Cattin, Matthieu           MC     matthieu.cattin@cern.ch
      Gousiou, Evangelia         EG     evangelia.gousiou@cern.ch     
      Wlostowski, Tomasz         TW     tomasz.wlostowski@cern.ch      
      Gil Soriano, Carlos        CGS    carlos.gil.soriano@cern.ch  
  + SUMMARY
     The goal of the meeting is to correct the errors found in CONV-TTL-BLO
     v1 to set a new board for be built by DEM.
      -+ SCHEMATICS
          All the issues found have been written down in a document handed in
          electronically to the participants.
     Several ways of jitter reduction has been discussed. As a consequence, the
     trigger connections have been rearranged in the FPGA so as they all connect
     to _P. Furthermore, external deglitching circuitry has been added to improve
     jitter by removing the sampling uncertainity introduced by synchronous repe
     tition through the FPGA.
===============================================================================
                    |         ! : fatal                 |  
                    |         + : important             |  
                    |         - : minor                 |   
                    |         ? : question              |  
                    |         * : note                  |  
===============================================================================

===============================================================================
SCHEMATICS

+ ConvTtlBlo_TOP.SchDoc
--+ FPGAps.SchDoc
--+ PowerSupplyBlocking.SchDoc 
--+ FPGAbank.SchDoc
--+ Clocks&Monitor.SchDoc 
--+ Communication.SchDoc 
--+ JTAG&Button.SchDoc 
--+ VME64xConn.SchDoc 
--+ InputBlocking.SchDoc 
----+ InputBlockingUnit.SchDoc 
--+ BlockingOutput.SchDoc 
----+ BlockingUnit.SchDoc 
--+ FrontPanelLeds.SchDoc 
--+ FrontTTL.SchDoc 

--> BOM
===============================================================================

--------------------------------------
General:
--------------------------------------
[EVB]  + Please, check out the correct naming of the signal levels (add _N
         where applicable).
         [CGS] --> Done.
[EVB] - Update Copyright year to 2012 in all the OHL textboxes.
         [CGS] --> Done.
[TW]  + We can improve jitter perfomance by rearranging connections in the FPGA
        (Advanced SelectIO uses by subsampling I/O at x8 clock frequency).
         [CGS] --> Done.
[CGS] + Another way of improving jitter performance is by adding an RC in the
        inputs and bypass the pulse (when it gets synchronous it will get
        correctly trimmed).
         [CGS] --> Done.
--------------------------------------

--------------------------------------
ConvTtlBlo_TOP.SchDoc
--------------------------------------
--------------------------------------

--------------------------------------
FPGAps.SchDoc
--------------------------------------
[EVB] - Some cleanup in test point area will be good.
         [CGS] --> Done.
[MC]  - Place GTP comment over the correct net and move it to
        Communication.SchDoc page
         [CGS] --> Done.
--------------------------------------

--------------------------------------
PowerSupplyBlocking.SchDoc 
--------------------------------------
[EVB] + Reduce BOM in Rhigh and Rcomp.
         [CGS] --> Done.
--------------------------------------

--------------------------------------
FPGAbank.SchDoc
--------------------------------------
[TW] ! Rearrange trigger inputs and outputs to be able to use
       fast time-tagging in the FPGA. See Xilinx's SelectIO document.
         [CGS] --> Read and done.
--------------------------------------

--------------------------------------
Clocks&Monitor.SchDoc 
--------------------------------------
[EVB] + Placing another ferrite can lower the voltage in the 3V3 pins.
        Measure the current voltage in pin 16 of IC13.
         [CGS] --> Measured: 3.28V
[MC]  + It will be good to clean DAC supplies as well. Use the output
        of the filter instead.
         [CGS] --> Done.
[MC]  - Remove textbox
         [CGS] --> Done.
--------------------------------------


--------------------------------------
Communication.SchDoc 
--------------------------------------
[EVB] + Add new SFP connector.
         [CGS] --> Done.
[EVB] - Comment on Spartan's MGTX is a little bit misleading.
         [CGS] --> Fine for layout engineer.
--------------------------------------

--------------------------------------
JTAG&Button.SchDoc 
--------------------------------------
[MC]  - "Addedd" typo in textbox. 
         [CGS] --> Removed.
[MC]  - Remove PROM Memory textbox. 
         [CGS] --> Done.
--------------------------------------

--------------------------------------
VME64xConn.SchDoc 
--------------------------------------
--------------------------------------

--------------------------------------
InputBlocking.SchDoc 
--------------------------------------
[EVB] ! We should add an Schmitt trigger with a
        low pass filter before it. The input of
        the low pass comes directly from the
        optocoupler.
         [CGS] --> Done.
[MC] + Add more description of Blocking signal.
         [CGS] --> Done.
--------------------------------------

--------------------------------------
InputBlockingUnit.SchDoc 
--------------------------------------
--------------------------------------

--------------------------------------
BlockingOutput.SchDoc 
--------------------------------------
[MC] + Remove textbox. 
         [CGS] --> Done.
[MC] + One pull-up is enogh for ANTIGLITCH_OE_N
         [CGS] --> Done.
--------------------------------------

--------------------------------------
BlockingUnit.SchDoc 
--------------------------------------
[MC] ? One diode is reversed from V1
         [CGS] --> For improving rise time not fall one, just in case.
--------------------------------------

--------------------------------------
FrontTTL.SchDoc 
--------------------------------------
[TW] + To improve fall time connect P3V3 to P5V to the protection
       diodes.
         [CGS] --> Done.
--------------------------------------

--------------------------------------
FrontPanelLeds.SchDoc 
--------------------------------------
[EVB] ? Should we change the value of the resistor that connect to the
        square LED array?
         [CGS] --> No, it is fine to place a lower valued resistor because
                   in other boards the LED array is dimmed.
--------------------------------------

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
BOM
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
[EVB] +  Reduce BOM as much as possible (resistors in Blocking PS, i.e.).
          [CGS] --> Done.
[MC]  ?  Why using different 100nF capacitors?
          [CGS] --> Different voltage ratings.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
