----------------------------------------------------------------------------------
-- Company:        CERN, BE-CO-HT
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    16:55:00 04/04/2012 
-- Design Name:    CONV_TTL_BLO image 0
-- Module Name:    image0_top - Behavioral 
-- Project Name:   CONV_TTL_BLO
-- Target Devices: Spartan 6 SLX45T
-- Tool versions: 
-- Description:    image0_top.vhd comprises the integration of four vhdl modules:
--                 1.- Trigger
-- Dependencies: 
--
-- Revision: 
-- Revision 1.00 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity image0_top is
   generic(
             g_NUMBER_OF_CHANNELS : INTEGER := 6
          );
   port(
          LED_SYS_PW        : out STD_LOGIC;
          LED_SYS_ERROR     : out STD_LOGIC;
          LED_TTL           : out STD_LOGIC;

          LED_LINK_UP       : out STD_LOGIC; 
          LED_PPS           : out STD_LOGIC; 
          LED_WR_OK         : out STD_LOGIC; 

          ---------------------------------------
          --  EXTRA_SWITCH
          --   
          --   1            rst 
          --   2            general OE and TTL
          --   3            OE blocking
          --------------------------------------

          EXTRA_SWITCH      : in  STD_LOGIC_VECTOR(3  downto 1);
          TTL               : in  STD_LOGIC;
          CLK20_VCXO        : in  STD_LOGIC;

          FPGA_OE           : out STD_LOGIC; 
          FPGA_BLO_OE       : out STD_LOGIC;  
          FPGA_TRIG_TTL_OE  : out STD_LOGIC; 
          FPGA_INV_OE       : out STD_LOGIC;

          FPGA_TRIG_BLO     : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
          PULSE_REAR_LED    : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);

          FPGA_INPUT_TTL    : in  STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
          FPGA_OUT_TTL      : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
          PULSE_FRONT_LED   : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);

          INV_OUT           : out STD_LOGIC_VECTOR(4  downto 1);

          FPGA_HEADER_OUT   : out STD_LOGIC_VECTOR(6  downto 1)
       );
end image0_top;

architecture Behavioral of image0_top is

   component trigger_top is
      port (
              pulse_i    : in  STD_LOGIC;
              pulse_o    : out STD_LOGIC;
              led_o      : out STD_LOGIC;
              utc_i      : in  STD_LOGIC_VECTOR(95 downto 0);
              wb_rst_i   : in  STD_LOGIC;		
              wb_clk     : in  STD_LOGIC;		
              wb_stb_i   : in  STD_LOGIC;
              wb_cyc_i   : in  STD_LOGIC;
              wb_ack_o   : out STD_LOGIC;
              wb_err_o   : out STD_LOGIC;
              wb_rty_o   : out STD_LOGIC;
              wb_we_i    : in  STD_LOGIC;		
              wb_sel_i   : in  STD_LOGIC_VECTOR(3  downto 0);
              wb_data_i  : in  STD_LOGIC_VECTOR(31 downto 0);
              wb_data_o  : out STD_LOGIC_VECTOR(31 downto 0);
              wb_addr_i  : in  STD_LOGIC_VECTOR(2  downto 0)
           );
   end component;

signal s_wb_ack_o        : STD_LOGIC; 
signal s_wb_err_o        : STD_LOGIC; 
signal s_wb_rty_o        : STD_LOGIC; 
signal s_wb_data_o       : STD_LOGIC_VECTOR(31  downto 0); 

signal s_PULSE_FRONT_LED : STD_LOGIC_VECTOR(6 downto 1);
signal s_FPGA_INPUT_TTL  : STD_LOGIC_VECTOR(6 downto 1);

signal s_pulse_i         : STD_LOGIC_VECTOR(6  downto 1);
signal s_pulse_o         : STD_LOGIC_VECTOR(6  downto 1);
signal s_led_o           : STD_LOGIC_VECTOR(6  downto 1);

signal clock_n           : STD_LOGIC;

begin

   -- IO Logic is inverted
   LED_SYS_PW       <= '0';
   LED_SYS_ERROR    <= '1'; 
   LED_TTL          <= '1'; 

   LED_LINK_UP      <= '1' ; 
   LED_PPS          <= '1' ; 
   LED_WR_OK        <= '1' ; 

   FPGA_INV_OE      <= '0'; 

   -- This assignments have not to be clocked
   FPGA_TRIG_BLO    <= s_pulse_o;
   PULSE_REAR_LED   <= not(s_led_o);

   s_pulse_i        <= not(FPGA_INPUT_TTL);
   FPGA_OUT_TTL     <= s_pulse_o;
   PULSE_FRONT_LED  <= not(s_led_o);

--   INV_OUT(1)          <= CLK20_VCXO;
   INV_OUT(4 downto 1) <= (others => '1');

   FPGA_HEADER_OUT     <= (others => '1');

   trigger_channels_loop: for i in 0 to g_NUMBER_OF_CHANNELS - 1 generate
   begin
      trigger_inst: trigger_top
      port map(
                 pulse_i    => s_pulse_i (1+i), 
                 pulse_o    => s_pulse_o (1+i),
                 led_o      => s_led_o   (1+i),
                 utc_i      => (others => '0'), 
                 wb_rst_i   => EXTRA_SWITCH(1), 
                 wb_clk     => CLK20_VCXO, 
                 wb_stb_i   => '0', 
                 wb_cyc_i   => '0', 
                 wb_ack_o   => s_wb_ack_o, 
                 wb_err_o   => s_wb_err_o, 
                 wb_rty_o   => s_wb_rty_o, 
                 wb_we_i    => '0', 
                 wb_sel_i   => (others => '0'), 
                 wb_data_i  => (others => '0'), 
                 wb_data_o  => s_wb_data_o, 
              -- TODO: possibleslave_ to leave only one common wb_addr_s
                 wb_addr_i  => (others => '0') 
              );
   end generate trigger_channels_loop;

   ttl_out: process (CLK20_VCXO)
   begin
      if rising_edge (CLK20_VCXO) then
         if EXTRA_SWITCH(2) = '1' then
            FPGA_OE          <= '0'; 
            FPGA_TRIG_TTL_OE <= '0'; 
         else
            FPGA_OE          <= '1'; 
            FPGA_TRIG_TTL_OE <= '1'; 
         end if;
      else

      end if;
   end process;


   blo_out: process(CLK20_VCXO)
   begin
      if rising_edge (CLK20_VCXO) then
         if EXTRA_SWITCH(3) = '1'  then
            FPGA_BLO_OE      <= '1';
         else
            FPGA_BLO_OE      <= '0';
         end if;
   else
   end if;
   end process;

end Behavioral;
