----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
-- 
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
---------------------------------------------------------------------------------
--
-- Company:        CERN, BE-CO-HT 
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    09:30:00 08/05/2012 
-- Design Name:    Wishbone core
-- Module Name:    Wisbhone core with Etherbone
-- Project Name:   Level Converters
-- Target Devices: Spartan 6
-- Tool versions:  
-- Description:    This a modified version of SPECs demonstator of WR for
--                 CONV-TTL-BLO
--
-- Dependencies: 
--
-- Revision: 
--   Revision 0.1  -08/05/2012- Synthesizable
--   Revision 0.2  -16/08/2012- Clean-up and synthesizable
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.ALL;

library UNISIM;
use UNISIM.vcomponents.all;

library work;
use work.wishbone_pkg.all;


entity wr_ep is
   generic(
      TAR_ADDR_WDTH : integer := 13        -- not used for this project
   );
   port(
      --! 1 rst_i
      --! 2 button1_i      -- What for?
      --! 3 button2_i      -- What for?
      EXTRA_SWITCH           : in  STD_LOGIC_VECTOR (3 downto 1);

      --! UART pins
      --! IN1    is UART RX
      --! OUT1   is UART TX
      FPGA_HEADER_IN         : in  STD_LOGIC_VECTOR (6 downto 1);
      FPGA_HEADER_OUT        : out STD_LOGIC_VECTOR (6 downto 1);

      --! Clocks
      CLK20_VCXO             : in  STD_LOGIC;
      FPGA_CLK_P             : in  STD_LOGIC;
      FPGA_CLK_N             : in  STD_LOGIC;

      --! Dedicated clock for Xilinx GTP transceiver
      FPGAMGTCLK0_P          : in STD_LOGIC;
      FPGAMGTCLK0_N          : in STD_LOGIC;

      --! Font panel LEDs    
      LED_WR_OK              : out STD_LOGIC;
      LED_PPS                : out STD_LOGIC;
      LED_LINK_UP            : out STD_LOGIC;

      --! 1-Wire interface to DS18B20
      THERMOMETER           : inout STD_LOGIC;

      --! DAC control
      FPGA_PLLDAC1_SYNC_N   : out STD_LOGIC;
      FPGA_PLLDAC_SCLK      : out STD_LOGIC;
      FPGA_PLLDAC_DIN       : out STD_LOGIC;
--      dac_clr1_n_o          : out STD_LOGIC;

      FPGA_PLLDAC2_SYNC_N   : out STD_LOGIC;
--      dac_sclk2_o         : out STD_LOGIC;
--      dac_din2_o          : out STD_LOGIC;
--      dac_clr2_n_o        : out STD_LOGIC;

      --! SFP pins
      MGTSFPTX0_P           : out   STD_LOGIC;
      MGTSFPTX0_N           : out   STD_LOGIC;
      MGTSFPRX0_P           : in    STD_LOGIC;
      MGTSFPRX0_N           : in    STD_LOGIC;

      FPGA_SFP_PRESENCE     : in    STD_LOGIC;
      FPGA_SFP_SCL          : inout STD_LOGIC;
      FPGA_SFP_SDA          : inout STD_LOGIC;
      FPGA_SFP_RATE_SELECT  : inout STD_LOGIC;   -- not connected
      SFP_TX_FAULT          : in    STD_LOGIC;   -- not connected 
      SFP_TX_DISABLE        : out   STD_LOGIC;
      FPGA_SFP_LOS          : in    STD_LOGIC;

   --! We add here all the rest of the pins
      LED_SYS_PW            : out   STD_LOGIC;
      LED_SYS_ERROR         : out   STD_LOGIC;
      LED_TTL               : out   STD_LOGIC;
      PULSE_FRONT_LED       : out   STD_LOGIC_VECTOR (6 downto 1);
      PULSE_REAR_LED        : out   STD_LOGIC_VECTOR (6 downto 1);
      FPGA_OUT_TTL          : out   STD_LOGIC_VECTOR (6 downto 1);
      INV_OUT               : out   STD_LOGIC_VECTOR (4 downto 1);
      FPGA_TRIG_BLO         : out   STD_LOGIC_VECTOR (6 downto 1);
      FPGA_OE               : out   STD_LOGIC; 
      FPGA_BLO_OE           : out   STD_LOGIC; 
      FPGA_TRIG_TTL_OE      : out   STD_LOGIC; 
      FPGA_INV_OE           : out   STD_LOGIC 
   );

end wr_ep;

architecture rtl of wr_ep is

   ------------------------------------------------------------------------------
   -- Components declaration
   ------------------------------------------------------------------------------

   component xwr_core is
      generic(
         g_SIMULATION                : INTEGER                     := 0;
         g_PHYS_UART                 : BOOLEAN                     := TRUE;
         g_VIRTUAL_UART              : BOOLEAN                     := FALSE;
         g_WITH_EXTERNAL_CLOCK_INPUT : BOOLEAN                     := FALSE;
         g_AUX_CLKS                  : INTEGER                     := 1;
         g_EP_RXBUF_SIZE             : INTEGER                     := 1024;
         g_DPRAM_INITF               : STRING                      := "";
         --in 32-bit words
         g_DPRAM_SIZE             : INTEGER                        := 20480;  
         g_INTERFACE_MODE         : t_wishbone_interface_mode      := CLASSIC;
         g_ADDRESS_GRANULARITY    : t_wishbone_address_granularity := WORD);
      port(
         clk_sys_i            : in  STD_LOGIC;
         clk_dmtd_i           : in  STD_LOGIC;
         clk_ref_i            : in  STD_LOGIC;
         clk_aux_i            : in  STD_LOGIC_VECTOR(g_AUX_CLKS-1 downto 0)
                                                            := (others => '0');
         clk_ext_i            : in  STD_LOGIC := '0';
         pps_ext_i            : in  STD_LOGIC := '0';
         rst_n_i              : in  STD_LOGIC;

         dac_hpll_load_p1_o   : out STD_LOGIC;
         dac_hpll_data_o      : out STD_LOGIC_VECTOR(15 downto 0);
         dac_dpll_load_p1_o   : out STD_LOGIC;
         dac_dpll_data_o      : out STD_LOGIC_VECTOR(15 downto 0);

         phy_ref_clk_i        : in  STD_LOGIC;
         phy_tx_data_o        : out STD_LOGIC_VECTOR(7 downto 0);
         phy_tx_k_o           : out STD_LOGIC;
         phy_tx_disparity_i   : in  STD_LOGIC;
         phy_tx_enc_err_i     : in  STD_LOGIC;
         phy_rx_data_i        : in  STD_LOGIC_VECTOR(7 downto 0);
         phy_rx_rbclk_i       : in  STD_LOGIC;
         phy_rx_k_i           : in  STD_LOGIC;
         phy_rx_enc_err_i     : in  STD_LOGIC;
         phy_rx_bitslide_i    : in  STD_LOGIC_VECTOR(3 downto 0);
         phy_rst_o            : out STD_LOGIC;
         phy_loopen_o         : out STD_LOGIC;

         led_red_o            : out STD_LOGIC;
         led_green_o          : out STD_LOGIC;
         scl_o                : out STD_LOGIC;
         scl_i                : in  STD_LOGIC;
         sda_o                : out STD_LOGIC;
         sda_i                : in  STD_LOGIC;
         sfp_scl_o            : out STD_LOGIC;
         sfp_scl_i            : in  STD_LOGIC;
         sfp_sda_o            : out STD_LOGIC;
         sfp_sda_i            : in  STD_LOGIC;
         sfp_det_i            : in  STD_LOGIC;
         btn1_i               : in  STD_LOGIC;
         btn2_i               : in  STD_LOGIC;

         uart_rxd_i           : in  STD_LOGIC;
         uart_txd_o           : out STD_LOGIC;

         owr_en_o             : out STD_LOGIC_VECTOR(1 downto 0);
         owr_i                : in  STD_LOGIC_VECTOR(1 downto 0);

         slave_i              : in  t_wishbone_slave_in;
         slave_o              : out t_wishbone_slave_out;

         wrf_src_o            : out t_wrf_source_out;
         wrf_src_i            : in  t_wrf_source_in := c_dummy_src_in;
         wrf_snk_o            : out t_wrf_sink_out;
         wrf_snk_i            : in  t_wrf_sink_in   := c_dummy_snk_in;

         timestamps_o         : out t_txtsu_timestamp;
         timestamps_ack_i     : in  STD_LOGIC := '1';

         tm_dac_value_o       : out STD_LOGIC_VECTOR(23 downto 0);
         tm_dac_wr_o          : out STD_LOGIC;
         tm_clk_aux_lock_en_i : in  STD_LOGIC;
         tm_clk_aux_locked_o  : out STD_LOGIC;
         tm_time_valid_o      : out STD_LOGIC;
         tm_utc_o             : out STD_LOGIC_VECTOR(39 downto 0);
         tm_cycles_o          : out STD_LOGIC_VECTOR(27 downto 0);
         pps_p_o              : out STD_LOGIC;

         dio_o                : out STD_LOGIC_VECTOR(3 downto 0);
         rst_aux_n_o          : out STD_LOGIC);
   end component;

   component wr_gtp_phy_spartan6
      generic(
         g_simulation         : INTEGER;
         g_ch0_use_refclk_out : BOOLEAN := FALSE;
         g_ch1_use_refclk_out : BOOLEAN := FALSE);
      port (
         gtp_clk_i          : in  STD_LOGIC;

         ch0_ref_clk_i      : in  STD_LOGIC;
         ch0_tx_data_i      : in  STD_LOGIC_VECTOR(7 downto 0);
         ch0_tx_k_i         : in  STD_LOGIC;
         ch0_tx_disparity_o : out STD_LOGIC;
         ch0_tx_enc_err_o   : out STD_LOGIC;
         ch0_rx_rbclk_o     : out STD_LOGIC;
         ch0_rx_data_o      : out STD_LOGIC_VECTOR(7 downto 0);
         ch0_rx_k_o         : out STD_LOGIC;
         ch0_rx_enc_err_o   : out STD_LOGIC;
         ch0_rx_bitslide_o  : out STD_LOGIC_VECTOR(3 downto 0);
         ch0_rst_i          : in  STD_LOGIC;
         ch0_loopen_i       : in  STD_LOGIC;

         ch1_ref_clk_i      : in  STD_LOGIC;
         ch1_tx_data_i      : in  STD_LOGIC_VECTOR(7 downto 0) := "00000000";
         ch1_tx_k_i         : in  STD_LOGIC := '0';
         ch1_tx_disparity_o : out STD_LOGIC;
         ch1_tx_enc_err_o   : out STD_LOGIC;
         ch1_rx_data_o      : out STD_LOGIC_VECTOR(7 downto 0);
         ch1_rx_rbclk_o     : out STD_LOGIC;
         ch1_rx_k_o         : out STD_LOGIC;
         ch1_rx_enc_err_o   : out STD_LOGIC;
         ch1_rx_bitslide_o  : out STD_LOGIC_VECTOR(3 downto 0);
         ch1_rst_i          : in  STD_LOGIC := '0';
         ch1_loopen_i       : in  STD_LOGIC := '0';

         pad_txn0_o         : out STD_LOGIC;
         pad_txp0_o         : out STD_LOGIC;
         pad_rxn0_i         : in  STD_LOGIC := '0';
         pad_rxp0_i         : in  STD_LOGIC := '0';
         pad_txn1_o         : out STD_LOGIC;
         pad_txp1_o         : out STD_LOGIC;
         pad_rxn1_i         : in  STD_LOGIC := '0';
         pad_rxp1_i         : in  STD_LOGIC := '0');
   end component;

   component spec_serial_dac_arb
      generic(
         g_invert_sclk    : BOOLEAN;
         g_num_extra_bits : INTEGER);
      port(
         clk_i         : in  STD_LOGIC;
         rst_n_i       : in  STD_LOGIC;
         val1_i        : in  STD_LOGIC_VECTOR(15 downto 0);
         load1_i       : in  STD_LOGIC;
         val2_i        : in  STD_LOGIC_VECTOR(15 downto 0);
         load2_i       : in  STD_LOGIC;
         dac_cs_n_o    : out STD_LOGIC_VECTOR(1 downto 0);
         dac_clr_n_o   : out STD_LOGIC;
         dac_sclk_o    : out STD_LOGIC;
         dac_din_o     : out STD_LOGIC);
   end component;

   component xmini_bone
      generic (
         g_class_mask    : STD_LOGIC_VECTOR(7 downto 0);
         g_our_ethertype : STD_LOGIC_VECTOR(15 downto 0));
      port (
         clk_sys_i    : in  STD_LOGIc;
         rst_n_i      : in  STD_LOGIc;
         src_o        : out t_wrf_source_out;
         src_i        : in  t_wrf_source_in;
         snk_o        : out t_wrf_sink_out;
         snk_i        : in  t_wrf_sink_in;
         master_o     : out t_wishbone_master_out;
         master_i     : in  t_wishbone_master_in);
   end component;


   ------------------------------------------------------------------------------
   -- Signals declaration
   ------------------------------------------------------------------------------
   signal s_led_red                 : STD_LOGIC;
   signal s_led_green               : STD_LOGIC;

   --! Reset signals
   signal s_rst                     : STD_LOGIC;
   signal s_local_reset_n           : STD_LOGIC;

   --! Clock signals
      signal s_fpga_clk             : STD_LOGIC;
      signal s_pllout_clk_fb_pllred : STD_LOGIC;
      signal s_pllout_clk_sys       : STD_LOGIC;
   signal s_clk_sys                 : STD_LOGIC;

   --! PLL clock for the DMTD
      signal s_clk_20M_vcxo_buf     : STD_LOGIC;
      signal s_pllout_clk_fb_DMTD   : STD_LOGIC;
      signal s_pllout_clk_DMTD      : STD_LOGIC;
   signal s_clk_DMTD                : STD_LOGIC;

   --! Dedicated clock for the GTP
   signal s_gtp_dedicated_clk       : STD_LOGIC;

   --! @brief All the signals that appear packed below belong to wrc
   signal s_sfp_scl_o               : STD_LOGIC;
   signal s_sfp_scl_i               : STD_LOGIC;
   signal s_sfp_sda_o               : STD_LOGIC;
   signal s_sfp_sda_i               : STD_LOGIC;
   --! UART pins
   signal s_uart_rxd                : STD_LOGIC;
   signal s_uart_txd                : STD_LOGIC;
   --! Thermometer pins
   signal s_owr_en                  : STD_LOGIC_VECTOR (1 downto 0);
   signal s_owr_i                   : STD_LOGIC_VECTOR (1 downto 0);
   --! DAC control signals from wrc to the DAC arbiter 
   signal s_dac_hpll_load_p1        : STD_LOGIC;
   signal s_dac_dpll_load_p1        : STD_LOGIC;
   signal s_dac_hpll_data           : STD_LOGIC_VECTOR (15 downto 0);
   signal s_dac_dpll_data           : STD_LOGIC_VECTOR (15 downto 0);

   signal s_phy_tx_data             : STD_LOGIC_VECTOR (7 downto 0);
   signal s_phy_tx_k                : STD_LOGIC;
   signal s_phy_tx_disparity        : STD_LOGIC;
   signal s_phy_tx_enc_err          : STD_LOGIC;
   signal s_phy_rx_data             : STD_LOGIC_VECTOR (7 downto 0);
   signal s_phy_rx_rbclk            : STD_LOGIC;
   signal s_phy_rx_k                : STD_LOGIC;
   signal s_phy_rx_enc_err          : STD_LOGIC;
   signal s_phy_rx_bitslide         : STD_LOGIC_VECTOR (3 downto 0);
   signal s_phy_rst                 : STD_LOGIC;
   signal s_phy_loopen              : STD_LOGIC;

   signal s_wrc_slave_i             : t_wishbone_slave_in;
   signal s_wrc_slave_o             : t_wishbone_slave_out;
   signal s_mbone_snk_in            : t_wrf_sink_in;
   signal s_mbone_snk_out           : t_wrf_sink_out;
   signal s_mbone_src_in            : t_wrf_source_in;
   signal s_mbone_src_out           : t_wrf_source_out;
   signal s_dio_out                 : STD_LOGIC_VECTOr(4 downto 0);
   signal s_mbone_rst_n             : STD_LOGIC;

   --! Rest of the signals needed in xmini_bone that are not in wrc
   signal s_mbone_wb_out            : t_wishbone_master_out;
   signal s_mbone_wb_in             : t_wishbone_master_in;

   signal s_dpram_slave2_in         : t_wishbone_master_out;

   signal s_dac_sclk_o              : STD_LOGIC;
   signal s_dac_din_o               : STD_LOGIC;

   signal s_fancy_counter           : UNSIGNED (23 downto 0);
   signal s_front_leds              : STD_LOGIC_VECTOR(6 downto 1);
begin

   LED_SYS_PW       <= '0'; 
   LED_SYS_ERROR    <= '1'; 
   LED_TTL          <= '1';
   FPGA_OUT_TTL     <= (others => '0');
   INV_OUT          <= (others => '0'); 
   FPGA_TRIG_BLO    <= (others => '0');
   FPGA_OE          <= '0'; 
   FPGA_BLO_OE      <= '0'; 
   FPGA_TRIG_TTL_OE <= '0'; 
   FPGA_INV_OE      <= '0';

   p_fancy_leds :process(s_clk_sys)
   begin
      if rising_edge(s_clk_sys) then
         if s_rst = '1' then
            s_fancy_counter           <= (others => '0');
            s_front_leds(6 downto 2)  <= (others => '1');
            s_front_leds(1)           <= '0';
         else
            s_fancy_counter <= s_fancy_counter + 1;
            if s_fancy_counter = X"FFFFFF" then
               s_fancy_counter <= (others => '0'); 
               s_front_leds    <=   s_front_leds(5 downto 1)
                                  & s_front_leds(6);
            else
            end if;
         end if;
         PULSE_FRONT_LED <= not(s_front_leds); 
         PULSE_REAR_LED  <= not(s_front_leds); 
      else
      end if;
   end process;

   LED_WR_OK     <= not(s_led_red); 
   LED_PPS       <= not(s_led_green);
   LED_LINK_UP   <= '1';

   --! L_RST_N is the reset line coming from Gennum linking dependencies
   s_local_reset_n  <= not(EXTRA_SWITCH(1));
   --! Active high reset
   s_rst            <= EXTRA_SWITCH(1);
   --! UART assignements
   s_uart_rxd          <= not(FPGA_HEADER_IN(1)); 
   FPGA_HEADER_OUT(1)  <= not(s_uart_txd);
   FPGA_HEADER_OUT(2)  <= '0';
   FPGA_HEADER_OUT(3)  <= '0';
   FPGA_HEADER_OUT(4)  <= '0';
   FPGA_HEADER_OUT(5)  <= '0';
   FPGA_HEADER_OUT(6)  <= '0';

   --! @brief Differential clock buffer, configured with differential
   --!        termination and low power.
   --!        Differential clock line FPGA_CLK_ must be 125MHz
   cmp_pllrefclk_buf : IBUFGDS
   generic map (
      DIFF_TERM    => true,
      IBUF_LOW_PWR => true,
      IOSTANDARD   => "DEFAULT")
   port map (
      O  => s_fpga_clk,
      I  => FPGA_CLK_P,
      IB => FPGA_CLK_N);

   --! @brief PLL for the system clock
   --!        It receives a 125MHz clock and generates 62.5MHz alligned one.
   cmp_sys_clk_pll : PLL_BASE
   generic map(
      BANDWIDTH          => "OPTIMIZED",
      CLK_FEEDBACK       => "CLKFBOUT",
      COMPENSATION       => "INTERNAL",
      DIVCLK_DIVIDE      => 1,
      CLKFBOUT_MULT      => 8,        CLKFBOUT_PHASE     => 0.000,
      CLKOUT0_DIVIDE     => 16,         -- 62.5 MHz
      CLKOUT0_PHASE      => 0.000,    CLKOUT0_DUTY_CYCLE => 0.500,
      CLKOUT1_DIVIDE     => 16,         -- 62.5 MHz
      CLKOUT1_PHASE      => 0.000,    CLKOUT1_DUTY_CYCLE => 0.500,
      CLKOUT2_DIVIDE     => 16,
      CLKOUT2_PHASE      => 0.000,    CLKOUT2_DUTY_CYCLE => 0.500,
      CLKIN_PERIOD       => 8.0,      REF_JITTER         => 0.016)
   port map(
      CLKFBOUT => s_pllout_clk_fb_pllred,
      CLKOUT0  => s_pllout_clk_sys,
      CLKOUT1  => open,
      CLKOUT2  => open,
      CLKOUT3  => open,
      CLKOUT4  => open,
      CLKOUT5  => open,
      LOCKED   => open,
      RST      => '0',
      CLKFBIN  => s_pllout_clk_fb_pllred,
      CLKIN    => s_fpga_clk);

   --! @brief Clock buffer for the system clock line
   cmp_clk_sys_buf : BUFG
   port map (
               O => s_clk_sys,
               I => s_pllout_clk_sys);



   --! @brief Input clock for the PLL which provides clock for the DMTD
   cmp_clk_vcxo : BUFG
   port map (
               O => s_clk_20M_vcxo_buf,
               I => CLK20_VCXO);

   --! @brief PLL for the DMTD. It works at 125MHz
   cmp_dmtd_clk_pll : PLL_BASE
   generic map(
      BANDWIDTH          => "OPTIMIZED",
      CLK_FEEDBACK       => "CLKFBOUT",
      COMPENSATION       => "INTERNAL",
      DIVCLK_DIVIDE      => 1,
      CLKFBOUT_MULT      => 50,       CLKFBOUT_PHASE     => 0.000,
      CLKOUT0_DIVIDE     => 16,           -- 62.5 MHz
      CLKOUT0_PHASE      => 0.000,    CLKOUT0_DUTY_CYCLE => 0.500,
      CLKOUT1_DIVIDE     => 16,           -- 62.5 MHz
      CLKOUT1_PHASE      => 0.000,    CLKOUT1_DUTY_CYCLE => 0.500,
      CLKOUT2_DIVIDE     => 8,
      CLKOUT2_PHASE      => 0.000,    CLKOUT2_DUTY_CYCLE => 0.500,
      CLKIN_PERIOD       => 50.0,     REF_JITTER         => 0.016)
   port map(
      CLKFBOUT => s_pllout_clk_fb_DMTD,
      CLKOUT0  => s_pllout_clk_DMTD,
      CLKOUT1  => open,
      CLKOUT2  => open,
      CLKOUT3  => open,
      CLKOUT4  => open,
      CLKOUT5  => open,
      LOCKED   => open,
      RST      => '0',
      CLKFBIN  => s_pllout_clk_fb_DMTD,
      CLKIN    => s_clk_20M_vcxo_buf);

   --! @brief Clock buffer for the DMTD clock line
   cmp_clk_dmtd_buf : BUFG
   port map (
      O => s_clk_DMTD,
      I => s_pllout_clk_DMTD);


   --! @brief Dedicated clock for GTP
   --!        It works at 125MHz
   cmp_gtp_dedicated_clk_buf : IBUFDS
     generic map(
       DIFF_TERM    => true,
       IBUF_LOW_PWR => true,
       IOSTANDARD   => "DEFAULT")
     port map (
       O  => s_gtp_dedicated_clk,
       I  => FPGAMGTCLK0_P,
       IB => FPGAMGTCLK0_N
     );

   --! @brief Pins controlled directly by xwr_core
   FPGA_SFP_SCL     <= '0' when s_sfp_scl_o = '0' else 'Z';
   FPGA_SFP_SDA     <= '0' when s_sfp_sda_o = '0' else 'Z';
   s_sfp_scl_i      <= FPGA_SFP_SCL;
   s_sfp_sda_i      <= FPGA_SFP_SDA;
   THERMOMETER      <= '0' when s_owr_en(0) = '1'   else 'Z';
   s_owr_i(0)         <= THERMOMETER;

   U_WR_CORE : xwr_core
   generic map(
      g_simulation                => 0,
      g_phys_uart                 => true,
      g_virtual_uart              => false,
      g_with_external_clock_input => true,
      g_aux_clks                  => 1,
      g_ep_rxbuf_size             => 1024,
      g_dpram_initf               => "../top/wrc.ram",
      g_dpram_size                => 90112/4, --16384 
      g_interface_mode            => PIPELINED,
      g_address_granularity       => BYTE)
   port map(
      clk_sys_i            => s_clk_sys,
      clk_dmtd_i           => s_clk_DMTD,
      clk_ref_i            => s_fpga_clk,
      clk_aux_i            => (others => '0'),
      clk_ext_i            => open, --dio_clk,
      pps_ext_i            => open, --dio_in(3),
      rst_n_i              => s_local_reset_n,

      dac_hpll_load_p1_o   => s_dac_hpll_load_p1,
      dac_hpll_data_o      => s_dac_hpll_data,
      dac_dpll_load_p1_o   => s_dac_dpll_load_p1,
      dac_dpll_data_o      => s_dac_dpll_data,

      phy_ref_clk_i        => s_fpga_clk,
      phy_tx_data_o        => s_phy_tx_data,        
      phy_tx_k_o           => s_phy_tx_k,
      phy_tx_disparity_i   => s_phy_tx_disparity,
      phy_tx_enc_err_i     => s_phy_tx_enc_err,
      phy_rx_data_i        => s_phy_rx_data,
      phy_rx_rbclk_i       => s_phy_rx_rbclk,
      phy_rx_k_i           => s_phy_rx_k,
      phy_rx_enc_err_i     => s_phy_rx_enc_err,
      phy_rx_bitslide_i    => s_phy_rx_bitslide,
      phy_rst_o            => s_phy_rst,
      phy_loopen_o         => s_phy_loopen,

      led_red_o            => s_led_red,
      led_green_o          => s_led_green,
      scl_o                => open,
      scl_i                => '0',
      sda_o                => open,
      sda_i                => '0',
      sfp_scl_o            => s_sfp_scl_o,
      sfp_scl_i            => s_sfp_scl_i,
      sfp_sda_o            => s_sfp_sda_o,
      sfp_sda_i            => s_sfp_sda_i,
      sfp_det_i            => FPGA_SFP_PRESENCE,    -- not used
      btn1_i               => EXTRA_SWITCH(2),      -- not used
      btn2_i               => EXTRA_SWITCH(3),      -- not used

      uart_rxd_i           => s_uart_rxd,
      uart_txd_o           => s_uart_txd,

      owr_en_o             => s_owr_en,
      owr_i                => s_owr_i,

      slave_i              => s_wrc_slave_i,
      slave_o              => s_wrc_slave_o,

      wrf_src_o            => s_mbone_snk_in,
      wrf_src_i            => s_mbone_snk_out,
      wrf_snk_o            => s_mbone_src_in,
      wrf_snk_i            => s_mbone_src_out,

      tm_dac_value_o       => open,
      tm_dac_wr_o          => open,
      tm_clk_aux_lock_en_i => '0',
      tm_clk_aux_locked_o  => open,
      tm_time_valid_o      => open,
      tm_utc_o             => open,
      tm_cycles_o          => open,
      pps_p_o              => open,

      dio_o                => s_dio_out(4 downto 1),
      rst_aux_n_o          => s_mbone_rst_n
   );


   -- Mini-BONE
   U_MiniBone : xmini_bone
   generic map(
      g_class_mask    => x"f0",
      g_our_ethertype => x"a0a0")
   port map(
      clk_sys_i => s_clk_sys,
      rst_n_i   => s_mbone_rst_n,
      src_o     => s_mbone_src_out,
      src_i     => s_mbone_src_in,
      snk_o     => s_mbone_snk_out,
      snk_i     => s_mbone_snk_in,
      master_o  => s_mbone_wb_out,
      master_i  => s_mbone_wb_in);

   U_DPRAM : xwb_dpram
   generic map(
      g_size                  => 2048,
      g_init_file             => "",
      g_must_have_init_file   => false,
      g_slave1_interface_mode => CLASSIC,
      g_slave2_interface_mode => CLASSIC,
      g_slave1_granularity    => WORD,
      g_slave2_granularity    => WORD)
   port map(
      clk_sys_i => s_clk_sys,
      rst_n_i   => s_mbone_rst_n,
      slave1_i  => s_mbone_wb_out,
      slave1_o  => s_mbone_wb_in,
      slave2_i  => s_dpram_slave2_in,
      slave2_o  => open);

   s_dpram_slave2_in.cyc <= '0';
   s_dpram_slave2_in.stb <= '0';

   U_GTP : wr_gtp_phy_spartan6
   generic map(
      g_simulation => 0)
   port map(
      gtp_clk_i          => s_gtp_dedicated_clk,

      ch0_ref_clk_i      => s_fpga_clk,
      ch0_tx_data_i      => s_phy_tx_data,
      ch0_tx_k_i         => s_phy_tx_k,
      ch0_tx_disparity_o => s_phy_tx_disparity,
      ch0_tx_enc_err_o   => s_phy_tx_enc_err,
      ch0_rx_data_o      => s_phy_rx_data,
      ch0_rx_rbclk_o     => s_phy_rx_rbclk,
      ch0_rx_k_o         => s_phy_rx_k,
      ch0_rx_enc_err_o   => s_phy_rx_enc_err,
      ch0_rx_bitslide_o  => s_phy_rx_bitslide,
      ch0_rst_i          => s_phy_rst,
      ch0_loopen_i       => s_phy_loopen,

      ch1_ref_clk_i      => s_fpga_clk,
      ch1_tx_data_i      => x"00",
      ch1_tx_k_i         => '0',
      ch1_tx_disparity_o => open,
      ch1_tx_enc_err_o   => open,
      ch1_rx_rbclk_o     => open,
      ch1_rx_data_o      => open,
      ch1_rx_k_o         => open,
      ch1_rx_enc_err_o   => open,
      ch1_rx_bitslide_o  => open,
      ch1_rst_i          => '1',
      ch1_loopen_i       => '0',

      pad_txn0_o         => MGTSFPTX0_N,
      pad_txp0_o         => MGTSFPTX0_P,
      pad_rxn0_i         => MGTSFPRX0_N,
      pad_rxp0_i         => MGTSFPRX0_P,
      pad_txn1_o         => open,
      pad_txp1_o         => open,
      pad_rxn1_i         => '0',
      pad_rxp1_i         => '0'
   );

   U_DAC_ARB : spec_serial_dac_arb
   generic map(
      g_invert_sclk    => false,
      g_num_extra_bits => 8)
   port map(
      clk_i            => s_clk_sys,
      rst_n_i          => s_local_reset_n,

      val1_i           => s_dac_dpll_data,
      load1_i          => s_dac_dpll_load_p1,

      val2_i           => s_dac_hpll_data,
      load2_i          => s_dac_hpll_load_p1,

      dac_cs_n_o(0)    => FPGA_PLLDAC1_SYNC_N,
      dac_cs_n_o(1)    => FPGA_PLLDAC2_SYNC_N,
      dac_clr_n_o      => open, --dac_clr1_n_o,
      dac_sclk_o       => s_dac_sclk_o,
      dac_din_o        => s_dac_din_o);

   FPGA_PLLDAC_SCLK   <= s_dac_sclk_o;
   FPGA_PLLDAC_DIN    <= s_dac_din_o;
   SFP_TX_DISABLE     <= '0';

end rtl;
