--
--	Package File Template
--
--	Purpose: This package defines supplemental types, subtypes, 
--		 constants, and functions 
--
--   To use any of the example code shown below, uncomment the lines and modify as necessary
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package ctdah_pkg is

   component gc_clk_divider is
      generic( g_CLK_DIVISION_LOGSIZE : NATURAL := 8);
      port (
              clk_i      : in  STD_LOGIC;
              rst_i      : in  STD_LOGIC;
              oe_n_i     : in  STD_LOGIC;
              clk_o      : out STD_LOGIC;
              divider_i  : in  STD_LOGIC_VECTOR (g_CLK_DIVISION_LOGSIZE - 1 downto 0) --Divides by twice the value specified
           );
   end component;

   component gc_counter is
      generic(
         g_DATA_WIDTH : NATURAL);
      port (
           clk_i  : in  STD_LOGIC;
           rst_i  : in  STD_LOGIC;
           en_i   : in  STD_LOGIC;
           cnt_o  : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
        );
   end component;

   component gc_debouncer is
      generic (
         g_LENGTH       : INTEGER := 6);
      port (
         rst         : in  STD_LOGIC;
         clk         : in  STD_LOGIC;
         input       : in  STD_LOGIC;
         output      : out STD_LOGIC;
         glitch_mask : in  STD_LOGIC_VECTOR(g_LENGTH-1 downto 0)
         );
   end component;


   component gc_ff is
     port(
             Q   : out STD_LOGIC;
             C   : in  STD_LOGIC;
             CLR : in  STD_LOGIC;
             D   : in  STD_LOGIC
                   );
   end component;

   component gc_monostable is
     port (
         rst            : in   STD_LOGIC;
         clk            : in   STD_LOGIC;
         pulse_len      : in   STD_LOGIC_VECTOR(31 downto 0);
         write_tt_o     : out  STD_LOGIC;
         input          : in   STD_LOGIC;
         output         : out  STD_LOGIC);
   end component;

   component gc_RAM is
      generic(g_DATA_WIDTH : INTEGER := 32;
              g_ADDR_WIDTH : INTEGER := 8);
      port(clka   : in  STD_LOGIC;
           wea    : in  STD_LOGIC;
           addra  : in  STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
           dina   : in  STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
           clkb   : in  STD_LOGIC;
           rstb   : in  STD_LOGIC;
           addrb  : in  STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
           doutb  : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0));
   end component;

   component FIFO_dispatcher is
      generic(
                g_DATA_WIDTH       : NATURAL := 8;
                g_DISPATCHER_DEPTH : NATURAL := 4);
      port (
              reg_i  : in  STD_LOGIC_VECTOR (g_DISPATCHER_DEPTH*g_DATA_WIDTH - 1 downto 0);
              clk    : in  STD_LOGIC;
              load   : in  STD_LOGIC;
              flush  : in  STD_LOGIC;
              oen_i  : in  STD_LOGIC;
              reg_o  : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
           );
   end component;

   component FIFO_stack is
      generic(
                g_DATA_WIDTH  : NATURAL := 8;
                g_STACK_DEPTH : NATURAL := 8
             );
      port (
              reg_i  : in   STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
              clk    : in   STD_LOGIC;
              push   : in   STD_LOGIC;
              flush  : in   STD_LOGIC;
              reg_o  : out  STD_LOGIC_VECTOR (g_STACK_DEPTH*g_DATA_WIDTH - 1 downto 0)
           );
   end component;

   component FIFO_simple is
      generic(
                g_DATA_WIDTH  : NATURAL := 8
             );
      port (
              reg_i  : in   STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
              clk    : in   STD_LOGIC;
              push   : in   STD_LOGIC;
              flush  : in   STD_LOGIC;
              reg_o  : out  STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
           );
   end component;


end ctdah_pkg;

package body ctdah_pkg is
end ctdah_pkg;
