----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
-- 
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company:        CERN, BE-CO-HT 
-- Engineer:       Carlos Gil Soriano
-- 
-- Create Date:    01:22:27 06/11/2012 
-- Design Name:    m25p32 top level
-- Module Name:    m25p32_top - Behavioral 
-- Project Name:   Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;

entity m25p32_top is
   port ( 
           wb_rst_i       : in  STD_LOGIC;
           wb_clk         : in  STD_LOGIC;

           wb_we_i        : in  STD_LOGIC;
           wb_stb_i       : in  STD_LOGIC;
           wb_cyc_i       : in  STD_LOGIC;
           wb_sel_i       : in  STD_LOGIC_VECTOR (3  downto 0);
           wb_data_i      : in  STD_LOGIC_VECTOR (31 downto 0); 
           wb_data_o      : out STD_LOGIC_VECTOR (31 downto 0); 
           wb_addr_i      : in  STD_LOGIC_VECTOR (3  downto 0); 
           wb_ack_o       : out STD_LOGIC; 
           wb_rty_o       : out STD_LOGIC; 
           wb_err_o       : out STD_LOGIC;

           prom_mosi_o    : out STD_LOGIC;
           prom_cclk_o    : out STD_LOGIC;
           prom_cs0_b_n_o : out STD_LOGIC;
           prom_din_i     : in  STD_LOGIC
        );
end m25p32_top;

architecture Behavioral of m25p32_top is

   signal s_CTR0          : STD_LOGIC_VECTOR (  r_CTR0'a_length - 1 downto 0);
   signal s_FMOH          : STD_LOGIC_VECTOR (  r_FMOH'a_length - 1 downto 0);
   signal s_DBUF          : STD_LOGIC_VECTOR (  r_DBUF'a_length - 1 downto 0);
   signal s_inst_db       : STD_LOGIC_VECTOR (  8*c_INST_LENGTH - 1 downto 0);
   signal s_addr_db       : STD_LOGIC_VECTOR (  8*c_ADDR_LENGTH - 1 downto 0);
   signal s_data_db       : STD_LOGIC_VECTOR (  8*c_DATA_LENGTH - 1 downto 0);

   signal s_inst_core     : STD_LOGIC_VECTOR (  8*c_INST_LENGTH - 1 downto 0);

   signal s_push_i_core   : STD_LOGIC;
   signal s_push_a_core   : STD_LOGIC;
   signal s_push_d_core   : STD_LOGIC;
   signal s_bov_core      : STD_LOGIC;


   component m25p32_core is
      port (
              wb_rst_i      : in  STD_LOGIC;
              wb_clk        : in  STD_LOGIC;

              mosi_o        : out STD_LOGIC;
              miso_i        : in  STD_LOGIC;
              sclk_o        : out STD_LOGIC;
              ss_n_o        : out STD_LOGIC;

              inst_db_i     : in  STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
              addr_db_i     : in  STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
              data_db_i     : in  STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);

              inst_core_o   : out STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);

              push_i_core_o : out STD_LOGIC;
              push_a_core_o : out STD_LOGIC;
              push_d_core_o : out STD_LOGIC;
              bov_core_o    : out STD_LOGIC;

              CTR0_o        : out STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
              FMOH_i        : in  STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
           );
   end component;

   component m25p32_regs is
      generic(
             g_INST_LENGTH : NATURAL := c_INST_LENGTH; 
             g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH; 
             g_DATA_LENGTH : NATURAL := c_DATA_LENGTH);
      port (
              wb_rst_i      : in  STD_LOGIC;
              wb_clk        : in  STD_LOGIC;

              wb_we_i       : in  STD_LOGIC;
              wb_stb_i      : in  STD_LOGIC;
              wb_cyc_i      : in  STD_LOGIC;
              wb_sel_i      : in  STD_LOGIC_VECTOR (3  downto 0);
              wb_data_i     : in  STD_LOGIC_VECTOR (31 downto 0);
              wb_data_o     : out STD_LOGIC_VECTOR (31 downto 0);
              wb_addr_i     : in  STD_LOGIC_VECTOR (3  downto 0);
              wb_ack_o      : out STD_LOGIC;
              wb_rty_o      : out STD_LOGIC;
              wb_err_o      : out STD_LOGIC;

              inst_core_i   : in  STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);

              inst_db_o     : out STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
              addr_db_o     : out STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
              data_db_o     : out STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);

              push_i_core_i : in STD_LOGIC;
              push_a_core_i : in STD_LOGIC;
              push_d_core_i : in STD_LOGIC;
              bov_core_i    : in STD_LOGIC;


              CTR0_i        : in  STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
              FMOH_o        : out STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0)
           );
   end component;

begin

   inst_m25p32_core: m25p32_core
   port map (
               wb_rst_i      => wb_rst_i, 
               wb_clk        => wb_clk, 

               mosi_o        => prom_mosi_o, 
               miso_i        => prom_din_i, 
               sclk_o        => prom_cclk_o, 
               ss_n_o        => prom_cs0_b_n_o, 

               inst_db_i     => s_inst_db,
               addr_db_i     => s_addr_db,
               data_db_i     => s_data_db,

               inst_core_o   => s_inst_core,

               push_i_core_o => s_push_i_core,
               push_a_core_o => s_push_a_core,
               push_d_core_o => s_push_d_core,
               bov_core_o    => s_bov_core,

               CTR0_o        => s_CTR0, 
               FMOH_i        => s_FMOH
            );

   inst_m25p32_regs:   m25p32_regs
   port map (
               wb_rst_i      => wb_rst_i, 
               wb_clk        => wb_clk, 

               wb_we_i       => wb_we_i, 
               wb_stb_i      => wb_stb_i, 
               wb_cyc_i      => wb_cyc_i, 
               wb_sel_i      => wb_sel_i, 
               wb_data_i     => wb_data_i,
               wb_data_o     => wb_data_o,
               wb_addr_i     => wb_addr_i,
               wb_ack_o      => wb_ack_o,
               wb_rty_o      => wb_rty_o,
               wb_err_o      => wb_err_o,

               inst_core_i   => s_inst_core,

               inst_db_o     => s_inst_db, 
               addr_db_o     => s_addr_db, 
               data_db_o     => s_data_db, 

               push_i_core_i => s_push_i_core,
               push_a_core_i => s_push_a_core,
               push_d_core_i => s_push_d_core,
               bov_core_i    => s_bov_core,

               CTR0_i        => s_CTR0,
               FMOH_o        => s_FMOH
            );

end Behavioral;
