-------------------------------------------------------------------------------
-- Title      : Counter with asynchronous reset
-- Project    : CTDAH
-------------------------------------------------------------------------------
-- File       : gc_counter.vhd
-- Author     : Carlos Gil Soriano
-- Company    : CERN BE-CO-HT
-- Created    : 2011-07-11
-- Last update: 2011-07-11
-- Platform   : FPGA-generic
-- Standard   : VHDL '87
------------------------------------------------------------------------------
-- Description: Counter with asynchronous reset
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2010-07-11  1.0      gilsoriano      Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity gc_counter is
   generic(
      g_data_width: NATURAL
   );
   port (
      clk_i  : in  STD_LOGIC;
      rst_i  : in  STD_LOGIC;
      en_i   : in  STD_LOGIC;
      cnt_o  : out  STD_LOGIC_VECTOR (g_data_width-1 downto 0)
   );
end gc_counter;

architecture Behavioral of gc_counter is


begin

   main_proc: process(clk_i, rst_i)

   variable cnt_s : UNSIGNED(g_data_width-1 downto 0);

   begin

      if rst_i  = '1' then
         cnt_s    := (others => '0');
      elsif rising_edge(clk_i) then
	 if en_i = '1' then
            -- Increment the counter if counting is enabled
            cnt_s := cnt_s + 1;
         else
         end if;
      else
      end if;
      cnt_o <= std_logic_vector(cnt_s);

   end process;

end Behavioral;
