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\begin{document}
\title{\textbf{{\LARGE SPI multifield HDL core}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\hypersetup{
  colorlinks   =  true,
  urlcolor     =  blue
  pdftitle     = {SPI multifield HDL core},
  pdfauthor    = {Carlos Gil Soriano},
  pdfsubject   = {Reference guide for SPI multifield HDL core},
  pdfkeywords  = {SPI, VHDL, core, register, mapping}
}
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
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      keepaspectratio]{../../../doc/OHWR/Pictures/Figures/OHRlogo.png}
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      keepaspectratio]{../../../doc/OHWR/Pictures/Figures/CERN-Logo.png}
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\begin{abstract}
  A configurable SPI multifield HDL core is shown. This core is able to
  specify three kind of fields to be sent according to SPI communication and
  been able to configure independently the lenght of every field.\\
  
  The core is targeted for complexer uses of SPI communications, like writing
  blocks of EEPROM memories which typically requiere three fields.\\
  
  The following subjects are addressed:
  \begin{itemize}
  \item The registers to control the module.
  \item Step-by-step instructions for proper use.
  access.
  \end{itemize}
\end{abstract}

  \vspace{2cm}
  \begin{center}
  \begin{tabular}{|p{2.5cm}|p{3.75cm}|p{3cm}|}
  \hline
  \multicolumn{3}{|c|}{\textbf{Revision history}}\\
     \hline
     \hline
     \textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
        \hline
        0.1 & SPI master multifield & July 20, 2012\\
        \hline
  \end{tabular}
  \end{center}

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Copyright CERN 2012.\\

This documentation describes Open Hardware and is licensed under the
CERN OHL v.1.1.\\

You may redistribute and modify this documentation under the terms of the CERN
OHL v.1.1. (\url{http://ohwr.org/cernohl}). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.\\

Please see the CERN OHL variable.1.1 for applicable conditions.\\

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\section{Structure}
  The SPI module contains several blocks related the following way:\\
  
  --  spi\_master\_top.vhd 
  
  ----- spi\_master\_regs.vhd
  
  ----- spi\_master\_slave\_core.vhd
  
  --------- FIFO\_dispatcher.vhd
  
  --------- gc\_counter.vhd
  
  --------- gc\_clk\_divider.vhd\\


The top module combines two components:
\textit{spi\_master\_core} and \textit{spi\_master\_regs}.
The first one can be used independently from thei the top module, saving some
interconnection lines and allowing a direct way of using the module. If access
to the control registers \textit{SPI[X]} through classic Wishbone interface is
desired, then the top module must be used.\\

Due to the target use of this SPI core (block transfers for memory interfaces) all
the three input fields are offered in both the top and the core modules.

Internally, the data in every of the three set of fields is registered by the
control registers, either by directly writing into the \textit{SPI[X]} register
(in the case of \textit{spi\_master\_core}) or through wishbone
(\textit{spi\_master\_top}).

\subsection{Dependencies}

Three components used in this core belongs to general use in CTDAH board.
Due to that they are packed inside \textbf{ctdah\_lib}. The required components
to be imported are:\\

-- FIFO\_dispatcher.vhd

-- gc\_counter.vhd

-- gc\_clk\_divider.vhd

\section{Registers}
\subsection{SPI0}
The SPI0 is a write-read register.\\

  \begin{tabular}{| l | c | c | c |}
    \hline
    \textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
    \hline
    \hline
    0     & \textbf{CPOL}  & Clock POLarity when idle & \textbf{"00000"} \\
    \hline  
    1     & \textbf{CPHA}  & Clock PHAse & \textbf{"00000"} \\
    \hline
    4-2   & x              & Reserved & \textbf{"00000"} \\
    \hline
    13-5  & \textbf{BDATA} & Bytes of DATA to be sent       & \textbf{c\_INST\_LENGTH}\\
    \hline
    22-14 & \textbf{BADDR} & Bytes of ADDRess to be sent    & \textbf{c\_ADDR\_LENGTH}\\
    \hline
    31-23 & \textbf{BINST} & Bytes of INSTruction to be sent& \textbf{c\_DATA\_LENGTH}\\
    \hline
  \end{tabular}

\subsection{SPI1}
The SPI1 is a write-read register.\\

  \begin{tabular}{| l | c | c | c |}
    \hline
    \textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
    \hline
    \hline
          0  & \textbf{PUSH\_DATA}  &  PUSH DATA bytes into       & \textbf{'0'}   \\
             &                      &   internal SPI core memory  & \\ 
    \hline
          1  & \textbf{PUSH\_ADDR}  &  PUSH ADDRess bytes into    & \textbf{'0'}   \\
             &                      &   internal SPI core memory  & \\ 
    \hline
          2  & \textbf{PUSH\_INST}  &  PUSH INSTruction bytes into& \textbf{'0'}   \\
             &                      &   internal SPI core memory  & \\ 
    \hline
        5-3  & x                    &  Reserved                   & \textbf{"000"} \\
    \hline
          6  & \textbf{SEND\_DATA}  &  DATA bytes will be sent in & \textbf{'0'}   \\
             &                      &   a write operation         & \\ 
    \hline
          7  & \textbf{SEND\_ADDR}  &  ADDR bytes will be sent in & \textbf{'0'}   \\
             &                      &   a write operation         & \\
    \hline
          8  & \textbf{SEND\_INST}  &  INST bytes will be sent in & \textbf{'0'}   \\
             &                      &   a write operation         & \\
    \hline
          9  & \textbf{SEND\_OP}    &  perform a SEND OPeration   & \textbf{'0'}   \\
    \hline
      11-10  & y                    & Reserved                    & \textbf{"00"}  \\
    \hline
      15-12  & \textbf{CLK\_DIV}    &  CLocK DIVider              & \textbf{X"0"}  \\
    \hline
      31-16  & z                    & Reserved                    & \textbf{X"0000"}\\
    \hline
  \end{tabular}

\subsection{SPI2}
The SPI2 register is a read-only register.\\

  \begin{tabular}{| l | c | c | c |}
    \hline
    \textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
    \hline
    \hline
    0     & \textbf{SENT\_DATA}   &  DATA was SENT         & \textbf{'0'}   \\ 
    \hline
    1     & \textbf{SENT\_ADDR}   &  ADDRess was SENT      & \textbf{'0'}   \\ 
    \hline
    2     & \textbf{SENT\_INST}   &  INSTruction was SENT  & \textbf{'0'}   \\ 
    \hline
    3     & \textbf{SENT\_OP  }   &  OPeration was SENT    & \textbf{'0'}   \\ 
    \hline
    11-4  & x                     &  Reserved              & \textbf{X"00"} \\ 
    \hline
    15-12 & \textbf{CLK\_DIV}     &  CLocK DIVision        & \textbf{X"0"}  \\ 
    \hline
  \end{tabular}


\section{Internal memory mapping}
The internal registers map is as follow:\\ 
 
 \begin{tabular}{| c | c | c |} 
 \hline 
 \textbf{Address} & \textbf{Register} & \textbf{Access} \\ 
 \hline 
 \hline 
 \textbf{0x0} & \textit{SPI0} & Write-read \\
 \hline 
 \textbf{0x1} & \textit{SPI1} & Write-read \\
 \hline 
 \textbf{0x2} & \textit{SPI2} & Read-only  \\ 
 \hline 
 \end{tabular} 

\section{How to use it}

\subsection{Outputting a stream of data through SPI}
\begin{enumerate}
\item Specify the divider it will be used to construct the SPI clk signal out
       of the general clk signal.
\item Place the values to be sent in \textit{inst\_i}, \textit{addr\_i} and
       \textit{data\_i}.
\item Register their values by one-clock asserting \textit{PUSH\_[X]} bits in
       \textit{SPI1} register.
\item Specify which fields must be sent by asserting \textit{SEND\_[X]} bits in
       \textit{SPI1} register. This bits must keep asserted during the whole
       send operation.
\item Specify the length in bytes of every field by writing \textit{SPI0}.
\item Assert \textit{SEND\_OP} bit field in \textit{SPI1} register. It must be
       keep asserted until \textit{SENT\_OP} is received.
\end{enumerate}

\end{document}
