customize

# Design Rule Verification Report

Date | : | 5/14/2013
Time | : | 12:37:34 PM
Elapsed Time | : | 00:00:00
Filename | : | \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
Warnings | : | 0
Rule Violations | : | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) | 0
Clearance Constraint (Gap=0.17mm) (All),(All) | 0
Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All) | 0
Net Antennae (Tolerance=0mm) (All) | 0
Silk to Silk (Clearance=0.254mm) (All),(All) | 0
Silkscreen Over Component Pads (Clearance=0.1mm) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) | 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) | 0
Hole Size Constraint (Min=0.025mm) (Max=3mm) (All) | 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1mm) (InNet('BLO_C_1_N')) | 0
Total | 0