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\begin{document}

%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}

%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}

\centerline
{
  \begin{tabular}{l c p{.6\textwidth}}
  \hline
  \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
  \hline
  04-07-2013 & 0.1 & First draft \\
  26-07-2013 & 0.2 & Second draft \\
  \hline
  \end{tabular}
}

\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents

%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables

\section*{List of Abbreviations}
\begin{tabular}{l l}
RTM & Rear-Transition Module \\
IC  & Integrated Circuit \\
PLL & Phase-Locked Loop \\
SFP & Small-Form-factor Pluggable (transceiver) \\
\end{tabular}

\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}

%==============================================================================
% SEC: Intro
%==============================================================================
\section{Introduction}
\label{sec:intro}

This document explains in detail the hardware of the TTL to blocking converter
system (Figure~\ref{fig:conv-sys-bd}). A full pulse conversion system consists of
three distinct boards:
\begin{itemize}
  \item CONV-TTL-BLO -- active front module, containing the circuits necessary
  to achieve all functionality of the system
  \item CONV-TTL-RTM -- passive rear-transition module (RTM) motherboard, providing the
  connections   from the CONV-TTL-BLO VME P2 connector to the rear panel
  \item CONV-TTL-RTM-BLO -- piggyback board on the RTM, providing the LEMO connectors,
  pulse LEDs, and the screws to fix the rear panel
\end{itemize}

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/conv-sys-bd}}
  \caption{TTL to blocking pulse conversion system}
  \label{fig:conv-sys-bd}
\end{figure}

The CONV-TTL-BLO can be used standalone without any RTM, if no blocking pulse replication
is needed. This board contains all active circuitry needed to implement the functionalty of
the system, from blocking pulse detection and generation, to communication over I$^2$C and
time-tagging via White Rabbit \cite{white-rabbit}.

An RTM system usually consists of both motherboard and piggyback and provide the
connections to input blocking pulses to the CONV-TTL-BLO.

%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\pagebreak
\subsection*{Additional documentation}

%\textcolor{red}{\textbf{!!!}}

\begin{itemize}
  \item CONV-TTL-BLO User Guide \cite{ctb-ug}
  \item CONV-TTL-BLO HDL Guide \cite{ctb-hdlguide}
\end{itemize}

%==============================================================================
% SEC: CONV-TTL-BLO
%==============================================================================
\section{Front module}
\label{sec:ctb}

A block diagram of the CONV-TTL-BLO front module is shown in Figure~\ref{fig:conv-ttl-blo-bd}.
The board contains all active circuitry needed within a converter system. The various blocks in
Figure~\ref{fig:conv-ttl-blo-bd} are presented in subsections that follow.

The schematics of the CONV-TTL-BLO board can be found at \cite{conv-ttl-blo-sch}.

\begin{figure}[h]
  \centerline{\includegraphics[width=.65\textwidth]{fig/conv-ttl-blo-bd}}
  \caption{Block diagram of CONV-TTL-BLO board}
  \label{fig:conv-ttl-blo-bd}
\end{figure}

%------------------------------------------------------------------------------
% SEC: VME conn
%------------------------------------------------------------------------------
\subsection{VME connector}
\label{sec:vme}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 8 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent

The VME backplane consists in two connectors, P1 and P2. The following connections
provided by the P1 connector are used on the CONV-TTL-BLO:
\begin{itemize}
  \item the VME power supply pins (3.3~V, 5~V and 12~V)
  \item \textit{SERCLK} and \textit{SERDAT} pins, for I$^2$C communication
  \item the geographical addressing pins, also necessary for I$^2$C communication
  \item the active-low system reset line, connected to the FPGA for resetting the
  logic implemented therein
\end{itemize}

Serial communication lines, geographical addressing lines and the system reset line
are isolated from the FPGA by means of a Texas Instruments SN74VMEH22501DGGR bus
transceiver. Their use is based on the SVEC design \cite{svec} and is due to their
compatibility to the VME standard.

Apart from the bus grant and IACK lines, which are daisy-chained, the rest of the
VME signals are not used on the CONV-TTL-BLO board.

The user-defined part of the P2 connector is used for carrying signals from the
CONV-TTL-BLO to the RTM and ultimately the piggyback. The following signals are
routed via the VME P2 connector:

\begin{itemize}
  \item blocking input signals (Section~\ref{sec:blo-inp})
  \item blocking output signals (Section~\ref{sec:blo-outp})
  \item RTM detection and rear panel pulse LED signals (Section~\ref{sec:rmtdet})
\end{itemize}

%------------------------------------------------------------------------------
% SUBSEC: Power
%------------------------------------------------------------------------------
\subsection{Power supplies}
\label{sec:ctb-power}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 2, 3 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent Various power levels are needed on the CONV-TTL-BLO board. They are listed in
Table~\ref{tbl:voltage-levels}. All power supplies on the board are derived
in some way from the 3.3~V, 5~V and 12~V VME power supplies.

\begin{table}[h]
\caption{Voltage levels on CONV-TTL-BLO}
\label{tbl:voltage-levels}
\centerline{
  \begin{tabular}{l p{.5\textwidth}}
  \hline
  \multicolumn{1}{c}{\textbf{Level}} & \multicolumn{1}{c}{\textbf{Description}} \\
  \hline
  1.2~V & Low-voltage power supply for the FPGA logic \\
  3.3~V & V$_{CC}$ for most of the devices on the board \\
  5~V   & Power supply for some circuits on-board (blocking input optocouplers, blocking
          output buffers, etc.) \\
  24~V  & Blocking-level power supply \\
  \hline
  \end{tabular}
}
\end{table}

First, the 5~V and 3.3~V VME supplies arriving on the VME connectors are filtered using
two PI filters (schematic page 2). These filters assure noise immunity in the 50~MHz to
150~MHz band. The filtered power supplies are used throughout the logic.

The 1.2~V logic power supply is generated by a Texas Instruments TPS54312PWP Buck converter.
This circuit can be found in page 2 of the schematics.

Finally, the 24~V blocking power supply (schematics page 3) uses a Texas Instruments
TPS40210DGQR boost converter. The values various components around the converter were calculated
using the first design example in the datasheet of the device~\cite{blo-ps-datasheet}.

%------------------------------------------------------------------------------
% SUBSEC: Clocks
%------------------------------------------------------------------------------
\subsection{Clock circuits}
\label{sec:clocks}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 5 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent There are multiple clock signals on the CONV-TTL-BLO (Table~\ref{tbl:clocks}).
A 20~MHz clock for the FPGA is generated directly from a tunable VCXO (OSC3). The
second FPGA clock is a 125~MHz signal generated from a 25~MHz VCXO by means of a Texas
Instruments CDCM61004RHBT PLL IC. Two of the other PLL's output channels are used
to output dedicated 125~MHz dedicated clocks to the SFP and FPGA transceiver.

\begin{table}[h]
\caption{Clocks on CONV-TTL-BLO}
\label{tbl:clocks}
\centerline
{
  \begin{tabular}{l r l}
  \hline
  \multicolumn{1}{c}{\textbf{Clock}} & \multicolumn{1}{c}{\textbf{Frequency}} & \multicolumn{1}{c}{\textbf{Description}} \\
  \hline
  CLK20\_VCXO &  20~MHz & FPGA clock (from VCXO) \\
  FPGA\_CLK   & 125~MHz & FPGA clock (from PLL IC) \\
  SFP\_CLK    & 125~MHz & Dedicated SFP clock \\
  FPGA\_MGT\_CLK & 125~MHz & Dedicated clock for FPGA transceiver \\
  \hline
  \end{tabular}
}
\end{table}

Both VCXOs can be tuned by means of two Analog Devices DACs (IC17 and IC18), that
can be controlled by the FPGA via a 3-wire SPI interface.

The 3.3~V power supply used by ICs on the clock generation part is a cleaner version
of the board-wide 3.3~V supply. The cleaning is done by a four-pole LC filter.

The design of the clock circuits is based on the SPEC board design \cite{spec}.

%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
%------------------------------------------------------------------------------
\subsection{FPGA}
\label{sec:fpga}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 4 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent A Xilinx XC6SLX45T Spartan-6 FPGA is present on the CONV-TTL-BLO board. It is the
core part of the blocking conversion system, since it is the device controlling
all the components on the board.

The intended functionality of the FPGA is:

\begin{itemize}
  \item generating output pulses as response to input pulse
  \item pulse logging
  \item clock conditioning
  \item remote reprogramming
  \item controlling the various panel LEDs to inform the user either of pulse
  arrival, or the status of the system.
\end{itemize}

For more details on the FPGA firmware and functionality, refer to the CONV-TTL-BLO
HDL Guide~\cite{ctb-hdlguide}.

%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
%------------------------------------------------------------------------------
\subsection{TTL pulse repetition}
\label{sec:ttl}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 13 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent TTL and TTL-BAR pulses may arrive on front panels of CONV-TTL-BLO boards. The two
signal types are described in Sections~4.1~and~4.2 of~\cite{ctb-ug}. Signals
arriving on an input channel go through an input stage consisting of Schmitt
trigger circuits; they are then input to the FPGA, where the pulse gets regenerated
and passed to the output stage.

%------------------------------------------------------------------------------
\subsubsection{TTL input stage}

The input stage on a TTL pulse channel is shown in Figure~\ref{fig:ttl-inp}.
Pulses go through a Texas Instruments SN74LVC14AD Schmitt trigger inverter which
isolates the FPGA from the channel input. The inverter is 5~V tolerant at the
input, so TTL signals may be up to 5~V high. Anything above 5.6~V opens the BAR66
diode to the 5~V and protects the Schmitt trigger.

The input stage is 50~$\Omega$ terminated (the three 150~$\Omega$ resistors in parallel).
Note that when no wire is plugged into the LEMO connector, the termination pulls the line low
which becomes a continuous high-level when it comes out of the Schmitt trigger.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/ttl-inp}}
  \caption{TTL pulse input stage}
  \label{fig:ttl-inp}
\end{figure}

This input stage is repeated on each of the six TTL pulse replication channels of
the CONV-TTL-BLO, as well as the four inverter channels.

%------------------------------------------------------------------------------
\subsubsection{TTL output stage}

The output stage consists of Texas Instruments SN64BCT25244DW tri-state buffers
driven by the FPGA. These buffers assure a high-impedance output on startup and
assure the line can drive a 50~$\Omega$ load. Pull-down resistors at the output
of the tri-state buffers assure a continuous low level at the output when the
buffers are not enabled. Combined with the guaranteed tri-state output on startup,
these resistors assure a continuous low-level at the output on startup.

The buffers' enable signals are controlled by two signals from the FPGA.
These signals are NANDed together (IC10 NAND gate) and connected to the output
enable active-low signals. When the FPGA does not drive the output enable line,
it is pulled high by a pull-up resistor, to safeguard against spurious signals on the
output of the channel.

%------------------------------------------------------------------------------
% SUBSEC: Blocking pulse rep
%------------------------------------------------------------------------------
\subsection{Blocking pulse repetition}
\label{sec:blo}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 9-12 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent Blocking pulses arrive through the LEMO connectors on the rear panel. Through the
RTM and the P2 connector, they arrive at the blocking input stage on the CONV-TTL-BLO,
where an optocoupler is used to isolate the input signal from the logic levels of
the FPGA. The input pulse then goes into the FPGA, where the pulse is regenerated
in the same manner as TTL pulses. The regenerated pulse signal goes through a flyback
converter output stage, where the logic levels of the FPGA are converted back into
blocking level.

%The blocking input stage can be found on pages~9~and~10 of the schematics; the blocking
%output stage can be found on pages~11~and~12.

%------------------------------------------------------------------------------
\subsubsection{Blocking input stage}
\label{sec:blo-inp}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 9, 10 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent The blocking input stage (Figure~\ref{fig:blo-inp-nodots}) contains the 50~$\Omega$ termination,
a transient voltage suppressor diode to protect against high-voltage spikes from the RTM, a
high-pass RC filter which prevents DC signals from passing to the Avago optocoupler. The optocoupler
isolates the blocking-level stage from the logic stage on the FPGA side. Since the
optocoupler is powered from 5~V, a Schmitt trigger (not shown in Figure~\ref{fig:blo-inp-nodots})
adapts the 5~V level to the 3.3~V level needed by the FPGA.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/blo-inp-nodots}}
  \caption{Blocking input stage}
  \label{fig:blo-inp-nodots}
\end{figure}

The minimum pulse level for this circuit is 3.8~V (see Appendix~\ref{app:blo-min-level}).

The maximum 24~V pulse width that can be safely sustained by the input stage is 3.9~$\mu$s
with a minimum period of 4.8~${\mu}$s (see Appendix~\ref{app:blo-max-width}).

%------------------------------------------------------------------------------
\subsubsection{Blocking output stage}
\label{sec:blo-outp}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 11, 12 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent The blocking output stage is a flyback converter design with a 1:1 conversion
ratio, shown in Figure~\ref{fig:blo-outp-nodots}. The core part of the output stage is
the flyback transformer assuring galvanic isolation at the output. The transformer is
driven straight from the 24~V blocking supply and controlled via the BSH103 power MOSFET.
The snubber circuit next to the transformer formed by the BAR66 diode and the Zener diode
provides a means to dissipate the energy stored in the leakage inductance of the transformer
when the MOSFET is on.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/blo-outp-nodots}}
  \caption{Blocking output stage}
  \label{fig:blo-outp-nodots}
\end{figure}

Upstream of the MOSFET's grid pin is a circuit similar to that in the TTL output stage.
This circuit is shown in Figure~\ref{fig:blo-outp-tristate}. The tri-state buffers'
outputs are high-impedance on startup, thus avoidiing spurious signals on blocking outputs.
The pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid
on startup.

The tri-state buffers are enabled by means of two signals from the FPGA: the output enable
signal common with the TTL output enable, and a separate, blocking output enable signal.
These two signals go through the IC10 NAND gate to enable the buffers. When the FPGA does
not drive either of these signals, the output enable input of the buffers is kept high via
the pull-up resistor.

\begin{figure}[h]
  \centerline{\includegraphics[scale=1]{fig/blo-outp-tristate}}
  \caption{Blocking output tri-state buffers}
  \label{fig:blo-outp-tristate}
\end{figure}


%The maximum pulse width that can be sustained without damaging the MOSFET is
%14~$\mu$s with a recommended minimum period of 140~$\mu$s (see Appendix~\ref{app:blo-max-pw}).

The maximum pulse frequency that can be sustained without damaging the MOSFET
is 210~kHz, with nominal blocking pulse widths of 1.2~$\mu$s \cite{blo-std}.
%(see Appendix~\ref{app:blo-max-freq}).

\vspace*{11pt}

\noindent \textbf{\textit{Note that if the FPGA is improperly configured, a DC high-level signal
on the power MOSFET's grid pin will yield a too high current passing through the MOSFET,
which will lead to its failure. Make sure the FPGA pins driving the blocking output stage
are properly configured to drive time-limited pulses or a DC low-level at the power
MOSFET's grid, or that the blocking output enable signal from the FPGA is low, so as to
keep the outputs of the tri-state buffers in high-impedance.}}

%\textcolor{red}{\textbf{details about output circuit}}
%
%\textcolor{red}{\textbf{galvanic isolation}}
%
%\textcolor{red}{\textbf{max outp. PW calculation}}
%
%\textcolor{red}{\textbf{danger in case of no firmware}}

%------------------------------------------------------------------------------
% SEC: Blocking pulse rep
%------------------------------------------------------------------------------
\subsection{SFP connector}
\label{sec:sfp}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 6 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent The small form-factor pluggable (SFP) connector on the CONV-TTL-BLO front panel
can be used to input an optic fiber cable that may be used for pulse time-tagging
using White Rabbit.

%------------------------------------------------------------------------------
% SEC: Thermo, flash
%------------------------------------------------------------------------------
\subsection{Thermometer and flash chip}
\label{sec:thermo-flash}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 7 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent A DS18B20U+ thermometer chip is provided on board. This chip can be used to provide
a unique ID for the board and measure on-board temperature. It communicates to the
FPGA via a Dallas one-wire interface and is powered from 3.3~V.

The Flash chip on-board is used to store FPGA configuration data. It is a Micron
M25P32 SPI Flash memory chip with 32~Mbits storage capability.

%------------------------------------------------------------------------------
% SEC: RTM det
%------------------------------------------------------------------------------
\subsection{RTM detection}
\label{sec:rmtdet}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 8 \\
\hline
\end{tabular}

\vspace*{11pt}

\noindent 

The RTM detection circuitry is shown in Figure~\ref{fig:rtmdet}. It works by
connecting the RTM motherboard or piggyback detection lines to ground, based
on the motherboard or piggyback used. Lines not connected to ground are pulled
up to V$_{CC}$ by the pull-up resistor, which yields a low value after
the Schmitt triggers. The outputs of the Schmitt triggers are connected directly
to the FPGA inputs.

An up-to-date list of boards and their RTM detection line connections can be found
at \cite{rtmdet}.

\begin{figure}[h]
  \centerline{\includegraphics[scale=1]{fig/rtmdet}}
  \caption{RTM detection circuit}
  \label{fig:rtmdet}
\end{figure}

%------------------------------------------------------------------------------
% SEC: LEDs, status and pulse
%------------------------------------------------------------------------------
\subsection{Status and pulse LEDs}
\label{sec:leds}

\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 14 \\
\hline
\end{tabular}

\vspace*{11pt}

The circuit for driving the bicolor status LEDs is based on the SVEC design \cite{svec}.
It consists of the same Texas Instruments SN74VMEH22501DGGR bus buffer chip used
for buffering the VME signals. The control and data lines of the chip are driven
by logic within the FPGA, which controls lighting of each of the LEDs. An example
of how the LEDs can be driven using the FPGA is given in Section~5 of~\cite{ctb-hdlguide}.

TTL (front panel) and blocking (rear panel) pulse LEDs are driven by the FPGA
via a SN7414 Schmitt trigger. In the case of the blocking LEDs, the output of
the Schmitt trigger is connected directly to the VME P2 connector and through
the RTM to the piggyback, where the current-limiting resistor and the LEDare located.

%==============================================================================
% SEC: RTM, RTMP
%==============================================================================
\section{Rear-Transition Module}
\label{sec:rtm}

Rear transition modules (RTMs) are located on the rear side of the VME crate.
An RTM in TTL to blocking converter systems is made up of two boards, the
motherboard and the piggyback, containing only passive components. The two boards
are detailed in the next subsections.

%------------------------------------------------------------------------------
% SUBSEC: RTMM
%------------------------------------------------------------------------------
\subsection{RTM Motherboard}

The CONV-TTL-RTM motherboard~\cite{rtmm-sch} is the interface between the VME P2
connector and the RTM piggyback board. It provides a female connector to the VME
backplane P2 connector and links the blocking and pulse LED signals from the
CONV-TTL-BLO to the piggyback via a 100-pin connector.

RTM motherboards are used in both CONV-TTL-BLO and CONV-TTL-RS485 systems, with
different piggybacks.

The motherboard also contains 47~V transient voltage suppressor diodes that inhibit
high-voltage pulses arriving on piggyback LEMO connectors.

%------------------------------------------------------------------------------
% SUBSEC: RTMP
%------------------------------------------------------------------------------
\subsection{RTM Piggyback}

The CONV-TTL-RTM-BLO piggyback~\cite{rtmp-sch}, provides the
actual connectors on rear panels of TTL to blocking converter systems. On each of the
six blocking channels, there are four LEMO connectors (one input and three outputs)
and one LED together with its corresponding current-limiting resistor. The connections
for each of the LEMOs and LEDs are made via the 100-pin male connector, through the RTM
motherboard, to the CONV-TTL-BLO.


%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}

%==============================================================================
% APP: Block inp stage calc
%==============================================================================
\section{Blocking input stage calculations}
\label{app:blo-inp}

Figure~\ref{fig:blo-inp} shows the blocking input stage, as a reference for the
calculations below.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/blo-inp}}
  \caption{Blocking input stage}
  \label{fig:blo-inp}
\end{figure}


%------------------------------------------------------------------------------
% SUBSEC: min pulse level
%------------------------------------------------------------------------------
\subsection{Minimum blocking pulse level}
\label{app:blo-min-level}

The optocoupler LED has a forward voltage of 1.5~V and therefore when the LED is on,
the voltage in point 2 of Figure~\ref{fig:blo-inp} is

 \begin{equation}
  V_2 = 1.5V
\end{equation}

This means that for the LED to turn on, only

\begin{equation}
V_2 = \frac{R_{152}}{R_{152} + R_{147}}{V_1}
\end{equation}

\begin{equation}
V_1 = \frac{R_{152} + R_{147}}{R_{152}}{V_2}
\end{equation}

\begin{equation}
V_1 = \frac{5k7}{4k7} \times 1.5 = 1.82 V
\end{equation}

\noindent are needed at the blocking input. However, the LED needs to reach a certain
intensity level before it triggers the output of the optocoupler. This translates into
a threshold current for the LED, which is given in the optocoupler datasheet \cite{opto-ds}
to have a typical value of

\begin{equation}
I_{TH} = 2mA
\end{equation}

Inputting this into the circuit calculation above, and knowing that when the LED is on
a 0.31~mA current passes through $R_{152}$ (1.5~V / 4k7~$\Omega$), this yields a
current of 2.31~mA passing through $R_{147}$ ($I_{LED} + I_{R_{152}}$).
This results in a minimum pulse level of

\begin{equation}
V_1 - V_2 = 2.31mA \times 1k{\Omega}
\end{equation}

\begin{equation}
V_{1,min} = 3.8V
\end{equation}

This value has been verified in practice to be the minimum input pulse level for which
a pulse is generated at the output.

%------------------------------------------------------------------------------
% SUBSEC: max pulse width
%------------------------------------------------------------------------------
\subsection{Maximum blocking pulse width calculation}
\label{app:blo-max-width}

Considering 24~V pulses at the blocking input (point 1 in Figure~\ref{fig:blo-inp})
and the fact that the forward voltage of the LED when conducting is 1.5~V ($V_2 =$ 1.5~V),
this yields a 22.5~mA current going through $R_{147}$

\begin{equation}
I_{R_{147}} = \frac{24-1.5}{1k} = 22.5mA
\end{equation}

Since this current is divided among $R_{152}$ and the optocoupler LED and the current
through $R_{152}$ is

\begin{equation}
I_{R_{152}} = \frac{V_2}{R_{152}} = \frac{1.5}{4k7} = 0.31mA
\end{equation}

\noindent the current through the LED is

\begin{equation}
I_{LED} = I_{R_{147}} - I_{R_{152}} \cong 22.2mA
\end{equation}

Now, by considering the maximum input RMS current of 20~mA obtained from the
optocoupler's datasheet \cite{opto-ds}, and knowing that the RMS current for the pulse wave is

\begin{equation}
I_{LED,RMS} = I_{LED} \sqrt{\delta}
\end{equation}

\noindent this gives a maximum duty cycle of

\begin{equation}
\delta \cong 0.81
\end{equation}

With the minimum 4.8~$\mu$s pulse period at the output, this gives a maximum input pulse
width of

\begin{equation}
t_{p,max} \cong 3.9 {\mu}s
\end{equation}


\end{appendices}

%==============================================================================
% APP: Block inp stage calc
%==============================================================================
%\pagebreak
%\section{Blocking output stage calculations}
%\label{app:blo-outp}
%
%Figure~\ref{fig:blo-outp} shows the blocking output stage, as a reference for the
%calculations below.
%
%\begin{figure}[h]
%  \centerline{\includegraphics[width=\textwidth]{fig/blo-outp}}
%  \caption{Blocking output stage}
%  \label{fig:blo-outp}
%\end{figure}
%
%%%------------------------------------------------------------------------------
%%% SUBSEC: max. pulse width
%%%------------------------------------------------------------------------------
%%\subsection{Maximum pulse width}
%%\label{app:blo-max-pw}
%%
%%The maximum current through the inductor is
%%
%%\begin{equation}
%%I_L = I_{max} \times (1 - e^{\frac{t}{\tau}})
%%\end{equation}
%
%%------------------------------------------------------------------------------
%% SUBSEC: max. pulse freq
%%------------------------------------------------------------------------------
%\subsection{Maximum blocking pulse frequency}
%\label{app:blo-max-freq}
%
%The maximum blocking pulse frequency will be calculated in this section, considering
%the nominal (1.2~$\mu$s) and maximum (2~$\mu$s) blocking pulse widths \cite{blo-std}.
%All calculations made here are for operation at 25~$^\circ$C.
%
%Power MOSFETs can withstand high currents on their inputs as long as these currents
%arrive as short pulses. What is important is for the MOSFET's temperature to not
%increase above 175~$^\circ$C. The MOSFET temperature rise is \cite{nxp-an11158}
%
%\begin{equation}
%T_{j(rise)max} = P_{av} * Z_{th}
%\end{equation}
%
%\noindent where $Z_{th}$ is the thermal impedance of the MOSFET. The thermal impedance
%varies depending on duty cycle, with a maximum of 140~K/W in the case of the BSH103
%present on the CONV-TTL-BLO. The thermal impedance curve based on duty cycle can be found
%in the BSH103 datasheet \textcolor{red}{\textbf{cite datasheet}}.
%
%When the MOSFET is turned on, it introduces its R$_{DS(on)}$ resistance into the
%circuit. Together with the transformer primary, this forms an RL circuit through which
%after 1.2~$\mu$s will pass a current of
%
%\begin{align}
%I_D & = \frac{V_{BLO}}{R_{DS(on)}} \left(( 1 - e^{-t\frac{R}{L}} \right) \nonumber \\
%    & = \frac{24}{0.5} \left( 1 - e^{-1.2{\mu} \frac{0.5}{100{\mu}}} \right) \nonumber \\
%    & \cong 0.3 A
%\end{align}
%
%%\begin{equation}
%%I_D =  
%%\end{equation}
%
%After the same time, the voltage across the inductor will be
%
%\begin{align}
%V_L &= V_{BLO} \times e^{-\frac{R}{L}} \nonumber \\
%    &= 24 \times e^{-\frac{0.5}{100{\mu}}} \nonumber \\
%    &= 23.85 V
%\end{align}
%
%\noindent and so, the drain-to-source voltage of the MOSFET
%
%\begin{equation}
%V_{DS} = V_{BLO} - V_L = 0.15 V
%\end{equation}
%
%With this, the power of the pulse can be calculated
%
%\begin{equation}
%P = I_D \times V_{DS} = 0.045 W
%\end{equation}
%
%In order for the MOSFET to function properly, its temperature must not be more
%than 175~$^\circ$C. The temperature rise on the MOSFET is 
%
%\noindent which in our case, starting from 25~$^\circ$C, is 150~$^\circ$C.
%
%To calculate the maximum pulse frequency, the pulse duty cycle which corresponds


%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{hwguide-conv-ttl-blo}

\end{document}