Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/trigger_top_tb |
PROP_Simulator=Modelsim-SE VHDL |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-10-08T16:26:30 |
PROP_intWbtProjectID=EF41633B9B530BE50A9AA6E385725EA0 |
PROP_intWbtProjectIteration=3 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.trigger_top_tb |
PROP_xilxBitgCfg_GenOpt_ASCIIFile=true |
PROP_xilxBitgCfg_PlaceMultiBoot_spartan6=true |
PROP_xilxBitgCfg_Rate_spartan6=10 |
PROP_xilxBitgCfg_Unused=Pull Up |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_xilxBitgCfg_MultiBootStartAddress_spartan6=0x00100000 |
PROP_xilxBitgCfg_MultiBootStartingAddrForGoldenConfig_spartan6=0x00200000 |
PROP_xilxBitgCfg_MultiBootUseNewMode_spartan6=false |
PROP_DevDevice=xc6slx45t |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=fgg484 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=7 |