| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| LD_LIBRARY_PATH | /opt/Xilinx/13.3/ISE_DS/ISE//lib/lin | /opt/Xilinx/13.3/ISE_DS/ISE//lib/lin | /opt/Xilinx/13.3/ISE_DS/ISE//lib/lin | /opt/Xilinx/13.3/ISE_DS/ISE//lib/lin |
| PATH | /opt/Xilinx/13.3/ISE_DS/ISE//bin/lin: /usr/lib/lightdm/lightdm: /usr/local/sbin: /usr/local/bin: /usr/sbin: /usr/bin: /sbin: /bin: /usr/games: /opt/modelsim_10/bin: /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/: /opt/Xilinx/13.3/ISE_DS/PlanAhead/bin/: /media/BACKUP/scripts |
/opt/Xilinx/13.3/ISE_DS/ISE//bin/lin: /usr/lib/lightdm/lightdm: /usr/local/sbin: /usr/local/bin: /usr/sbin: /usr/bin: /sbin: /bin: /usr/games: /opt/modelsim_10/bin: /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/: /opt/Xilinx/13.3/ISE_DS/PlanAhead/bin/: /media/BACKUP/scripts |
/opt/Xilinx/13.3/ISE_DS/ISE//bin/lin: /usr/lib/lightdm/lightdm: /usr/local/sbin: /usr/local/bin: /usr/sbin: /usr/bin: /sbin: /bin: /usr/games: /opt/modelsim_10/bin: /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/: /opt/Xilinx/13.3/ISE_DS/PlanAhead/bin/: /media/BACKUP/scripts |
/opt/Xilinx/13.3/ISE_DS/ISE//bin/lin: /usr/lib/lightdm/lightdm: /usr/local/sbin: /usr/local/bin: /usr/sbin: /usr/bin: /sbin: /bin: /usr/games: /opt/modelsim_10/bin: /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/: /opt/Xilinx/13.3/ISE_DS/PlanAhead/bin/: /media/BACKUP/scripts |
| XILINX | /opt/Xilinx/13.3/ISE_DS/ISE/ | /opt/Xilinx/13.3/ISE_DS/ISE/ | /opt/Xilinx/13.3/ISE_DS/ISE/ | /opt/Xilinx/13.3/ISE_DS/ISE/ |
| XILINXD_LICENSE_FILE | /home/carlos/.Xilinx/xilinx.lic | /home/carlos/.Xilinx/xilinx.lic | /home/carlos/.Xilinx/xilinx.lic | /home/carlos/.Xilinx/xilinx.lic |
| XIL_PAR_DESIGN_CHECK_VERBOSE | 1 | 1 | 1 | 1 |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | basic_trigger_top.prj | ||
| -ofn | basic_trigger_top | ||
| -ofmt | NGC | NGC | |
| -p | xc6slx45t-3-fgg484 | ||
| -top | basic_trigger_top | ||
| -opt_mode | Optimization Goal | Speed | Speed |
| -opt_level | Optimization Effort | 1 | 1 |
| -power | Power Reduction | NO | No |
| -iuc | Use synthesis Constraints File | NO | No |
| -keep_hierarchy | Keep Hierarchy | No | No |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
| -rtlview | Generate RTL Schematic | Yes | No |
| -glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
| -read_cores | Read Cores | YES | Yes |
| -write_timing_constraints | Write Timing Constraints | NO | No |
| -cross_clock_analysis | Cross Clock Analysis | NO | No |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100 |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100 |
| -dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100 |
| -reduce_control_sets | Auto | Auto | |
| -fsm_extract | YES | Yes | |
| -fsm_encoding | Auto | Auto | |
| -safe_implementation | No | No | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | Yes | |
| -ram_style | Auto | Auto | |
| -rom_extract | Yes | Yes | |
| -shreg_extract | YES | Yes | |
| -rom_style | Auto | Auto | |
| -auto_bram_packing | NO | No | |
| -resource_sharing | YES | Yes | |
| -async_to_sync | NO | No | |
| -use_dsp48 | Auto | Auto | |
| -iobuf | YES | Yes | |
| -max_fanout | 100000 | 100000 | |
| -bufg | 16 | 16 | |
| -register_duplication | YES | Yes | |
| -register_balancing | No | No | |
| -optimize_primitives | NO | No | |
| -use_clock_enable | Auto | Auto | |
| -use_sync_set | Auto | Auto | |
| -use_sync_reset | Auto | Auto | |
| -iob | Auto | Auto | |
| -equivalent_register_removal | YES | Yes | |
| -slice_utilization_ratio_maxmargin | 5 | 0 | |
| Translation Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -intstyle | ise | None | |
| -dd | _ngo | None | |
| -p | xc6slx45t-fgg484-3 | None | |
| -uc | /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/FPGAbank.ucf | None | |
| Map Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ol | Place & Route Effort Level (Overall) | high | high |
| -xt | Extra Cost Tables | 0 | 0 |
| -ir | Use RLOC Constraints | OFF | OFF |
| -t | Starting Placer Cost Table (1-100) Map | 1 | 0 |
| -r | Register Ordering | 4 | 4 |
| -intstyle | ise | None | |
| -lc | LUT Combining | off | off |
| -o | basic_trigger_top_map.ncd | None | |
| -w | true | false | |
| -pr | Pack I/O Registers/Latches into IOBs | off | off |
| -p | xc6slx45t-fgg484-3 | None | |
| Place and Route Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -intstyle | ise | ||
| -mt | Enable Multi-Threading | off | off |
| -ol | Place & Route Effort Level (Overall) | high | std |
| -w | true | false | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz/1199.000 MHz | Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz/1199.000 MHz | Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz/2534.000 MHz | Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz/1199.000 MHz |
| Host | carlos-VAIO | carlos-VAIO | carlos-VAIO | carlos-VAIO |
| OS Name | Ubuntu | Ubuntu | Ubuntu | Ubuntu |
| OS Release | Ubuntu 11.10 | Ubuntu 11.10 | Ubuntu 11.10 | Ubuntu 11.10 |