basic_trigger_top Project Status (10/24/2012 - 11:36:01)
Project File: basic_trigger.xise Parser Errors: No Errors
Module Name: basic_trigger_top Implementation State: Programming File Generated
Target Device: xc6slx45t-3fgg484
  • Errors:
No Errors
Product Version:ISE 13.3
  • Warnings:
592 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 249 54,576 1%  
    Number used as Flip Flops 249      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 596 27,288 2%  
    Number used as logic 572 27,288 2%  
        Number using O6 output only 320      
        Number using O5 output only 180      
        Number using O5 and O6 72      
        Number used as ROM 0      
    Number used as Memory 8 6,408 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 8      
            Number using O6 output only 8      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 16      
        Number with same-slice register load 4      
        Number with same-slice carry load 12      
        Number with other load 0      
Number of occupied Slices 199 6,822 2%  
Nummber of MUXCYs used 384 13,644 2%  
Number of LUT Flip Flop pairs used 618      
    Number with an unused Flip Flop 377 618 61%  
    Number with an unused LUT 22 618 3%  
    Number of fully used LUT-FF pairs 219 618 35%  
    Number of unique control sets 17      
    Number of slice register sites lost
        to control set restrictions
23 54,576 1%  
Number of bonded IOBs 59 296 19%  
    Number of LOCed IOBs 59 59 100%  
Number of RAMB16BWERs 0 116 0%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of GTPA1_DUALs 0 2 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 4 25%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.84      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Nov 21 11:49:56 20120592 Warnings (0 new)20 Infos (0 new)
Translation ReportCurrentWed Nov 21 11:50:02 2012000
Map ReportCurrentWed Nov 21 11:50:22 2012005 Infos (0 new)
Place and Route ReportCurrentWed Nov 21 11:50:44 2012003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Nov 21 11:50:52 2012003 Infos (0 new)
Bitgen ReportCurrentWed Nov 21 11:51:34 2012000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Nov 21 11:51:36 2012
WebTalk Log FileCurrentWed Nov 21 11:51:36 2012

Date Generated: 01/17/2013 - 12:24:42