Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
283 |
54,576 |
1% |
|
Number used as Flip Flops |
283 |
|
|
|
Number used as Latches |
0 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
0 |
|
|
|
Number of Slice LUTs |
649 |
27,288 |
2% |
|
Number used as logic |
625 |
27,288 |
2% |
|
Number using O6 output only |
342 |
|
|
|
Number using O5 output only |
181 |
|
|
|
Number using O5 and O6 |
102 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
8 |
6,408 |
1% |
|
Number used as Dual Port RAM |
0 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
8 |
|
|
|
Number using O6 output only |
8 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
0 |
|
|
|
Number used exclusively as route-thrus |
16 |
|
|
|
Number with same-slice register load |
4 |
|
|
|
Number with same-slice carry load |
12 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
222 |
6,822 |
3% |
|
Nummber of MUXCYs used |
416 |
13,644 |
3% |
|
Number of LUT Flip Flop pairs used |
673 |
|
|
|
Number with an unused Flip Flop |
399 |
673 |
59% |
|
Number with an unused LUT |
24 |
673 |
3% |
|
Number of fully used LUT-FF pairs |
250 |
673 |
37% |
|
Number of unique control sets |
19 |
|
|
|
Number of slice register sites lost to control set restrictions |
29 |
54,576 |
1% |
|
Number of bonded IOBs |
65 |
296 |
21% |
|
Number of LOCed IOBs |
65 |
65 |
100% |
|
Number of RAMB16BWERs |
0 |
116 |
0% |
|
Number of RAMB8BWERs |
0 |
232 |
0% |
|
Number of BUFIO2/BUFIO2_2CLKs |
0 |
32 |
0% |
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
4 |
16 |
25% |
|
Number used as BUFGs |
4 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
0 |
8 |
0% |
|
Number of ILOGIC2/ISERDES2s |
0 |
376 |
0% |
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
376 |
0% |
|
Number of OLOGIC2/OSERDES2s |
0 |
376 |
0% |
|
Number of BSCANs |
0 |
4 |
0% |
|
Number of BUFHs |
0 |
256 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
0 |
58 |
0% |
|
Number of GTPA1_DUALs |
0 |
2 |
0% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
0 |
2 |
0% |
|
Number of PCIE_A1s |
0 |
1 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
1 |
4 |
25% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
2.83 |
|
|
|