Adding .ucf for V2

0341f17e · Carlos Gil Soriano · f1fe4077 · 0341f17e · 0341f17e · 0341f17e
Commit 0341f17e authored Dec 12, 2012 by Carlos Gil Soriano
12 changed files
--- a/hdl/IMAGES/image1/constraints/V1/EDA-02446-V1-0_sch.pdf
+++ b/hdl/IMAGES/image1/constraints/V1/EDA-02446-V1-0_sch.pdf
--- a/hdl/IMAGES/image1/constraints/FPGAbank.ucf
+++ b/hdl/IMAGES/image1/constraints/FPGAbank.ucf
--- a/hdl/IMAGES/image1/constraints/V2/BloV2.NET
+++ b/hdl/IMAGES/image1/constraints/V2/BloV2.NET
--- a/hdl/IMAGES/image1/constraints/V2/BloV2.XNET
+++ b/hdl/IMAGES/image1/constraints/V2/BloV2.XNET
+NetIC14_C3
+NetIC14_Y4
+SFP_VCCT
+SFP_VCCR
+P1V2
+P3V3
+NetIC14_E9
+FPGA_MGTAVCC
--- a/hdl/IMAGES/image1/constraints/V2/BloV2.ucf
+++ b/hdl/IMAGES/image1/constraints/V2/BloV2.ucf
--- a/hdl/IMAGES/image1/constraints/V2/EDA-02446-V2-0_sch.pdf
+++ b/hdl/IMAGES/image1/constraints/V2/EDA-02446-V2-0_sch.pdf
--- a/hdl/IMAGES/image1/constraints/V2/net2ucf.py
+++ b/hdl/IMAGES/image1/constraints/V2/net2ucf.py
+#!/usr/bin/python
+
+## @package net2ucf.py
+#  @author  Matthieu Cattin, Carlos Gil Soriano.
+
+#  This is a modified net2ucf.py by Carlos Gil Soriano,
+#  previously done by Matthieu Cattin.
+
+import re
+
+## @class net2ucf class able to extract ucf files from an Altium NET files
+class NET2UCF:
+
+   ## @brief                        Constructor of the ucf extractor
+   #  @param path_ucfFile           Path to be written the ucf file
+   #  @param path_excludedNetsFile  A path with the nets files to be excluded
+   #  @param ICid                   IC identificator to extract the ucf from
+   def __init__(self, path_netFile, path_ucfFile, path_excludedNetsFile, ICid):
+      if path_netFile.endswith('.NET'):
+         try:
+            self.netFile       = open(path_netFile, "r")
+         except IOError as e:
+            print '.NET file does not exist!'
+      else:
+         raise Exception('Bad extension of the net file')
+
+      if path_ucfFile.endswith('.ucf'):
+         try:
+            self.ucfFile       = open(path_ucfFile, "w")
+         except IOError as e:
+            print '.ucf file does not exist!'
+      else:
+         raise Exception('Bad extension of the ucf file')
+
+      if path_excludedNetsFile.endswith('.XNET'):
+         try:
+            self.excludedNetsFile  = open(path_excludedNetsFile, "r")
+         except IOError as e:
+            print '.XNET file does not exist!'
+
+         print "I'm here!"
+         self.listExcludedNets = []
+         for line in self.excludedNetsFile:
+            ln = line.split()
+            self.listExcludedNets.append(ln[0])
+         print 'Excluded nets:\n' + str(self.listExcludedNets)
+      else:
+         raise Exception('Bad extension of the excluded nets file')
+
+      self.ICid = ICid
+
+   ## @fn generateUCF(self)
+   #  @brief  Function that process the NET file and generates the UCF one.
+   def generateUCF(self):
+      for line in self.netFile:
+         ln   = line.split()
+         skip = False
+         for item in self.listExcludedNets:
+            if ln[0].startswith(str(item)):
+               print str(ln[0])+'Omitted because is a excluded net'
+               skip = True
+         if skip == False:
+            try:
+               print ln;
+               if ln[1].startswith('IC14'):
+                  self.ucfFile.write("NET \""+ln[0]+"\" LOC = "+ln[1].split('-')[1]+";\n")
+            except IOError as e:
+              print 'Bad line in FPGA.NET'
+
+print '-------------------------------------'
+print '--------   NET2UCF program   --------'
+print '-------------------------------------\n'
+print 'Case sensitive!\n'
+path_NetFile = raw_input('Insert the path of the NET file. Format is \n'+'-- [PATH]/[name].NET:\t')
+path_ucfFile = raw_input('Insert path of the ucf file. Format is \n'+'-- [PATH]/[name].ucf:\t')
+path_excludedNetsFile = raw_input('Insert path of the file containing nets not to be included'+ '-- [PATH]/[name].XNET:\t')
+ICid    = raw_input('Insert which IC to get the ucf file from:\t')
+
+net2ucf_inst = NET2UCF(path_NetFile, path_ucfFile, path_excludedNetsFile, ICid)
+net2ucf_inst.generateUCF()
--- a/hdl/IMAGES/image1/project/image1.gise
+++ b/hdl/IMAGES/image1/project/image1.gise
@@ -152,7 +152,7 @@
      <outfile xil_pn:name="../test/image1_top_tb.vhd"/>
      <outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
    </transform>
-    <transform xil_pn:end_ts="1355240544" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1355240543">
+    <transform xil_pn:end_ts="1355302790" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1355302789">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="image1_top_tb.fdo"/>

--- a/hdl/IMAGES/image1/test/log/i2c_master_driver.txt
+++ b/hdl/IMAGES/image1/test/log/i2c_master_driver.txt
@@ -73,96 +73,3 @@
 14	  OK	 READ	    WISHBONE LOW
 14	  OK	 READ	     [ADDRESS|0]
 15	  OK	WRITE	     [ADDRESS|0]
-15	  OK	WRITE	   WISHBONE HIGH
-15	  OK	WRITE	    WISHBONE LOW
-15	  OK	WRITE	     READ DATA 0
-15	  OK	WRITE	     READ DATA 1
-15	  OK	WRITE	     READ DATA 2
-15	  OK	WRITE	     READ DATA 3
-16	  OK	 READ	     [ADDRESS|0]
-16	  OK	 READ	   WISHBONE HIGH
-16	  OK	 READ	    WISHBONE LOW
-16	  OK	 READ	     [ADDRESS|0]
-17	  OK	WRITE	     [ADDRESS|0]
-17	  OK	WRITE	   WISHBONE HIGH
-17	  OK	WRITE	    WISHBONE LOW
-17	  OK	WRITE	     READ DATA 0
-17	  OK	WRITE	     READ DATA 1
-17	  OK	WRITE	     READ DATA 2
-17	  OK	WRITE	     READ DATA 3
-18	  OK	 READ	     [ADDRESS|0]
-18	  OK	 READ	   WISHBONE HIGH
-18	  OK	 READ	    WISHBONE LOW
-18	  OK	 READ	     [ADDRESS|0]
-19	  OK	WRITE	     [ADDRESS|0]
-19	  OK	WRITE	   WISHBONE HIGH
-19	  OK	WRITE	    WISHBONE LOW
-19	  OK	WRITE	     READ DATA 0
-19	  OK	WRITE	     READ DATA 1
-19	  OK	WRITE	     READ DATA 2
-19	  OK	WRITE	     READ DATA 3
-20	  OK	 READ	     [ADDRESS|0]
-20	  OK	 READ	   WISHBONE HIGH
-20	  OK	 READ	    WISHBONE LOW
-20	  OK	 READ	     [ADDRESS|0]
-21	  OK	WRITE	     [ADDRESS|0]
-21	  OK	WRITE	   WISHBONE HIGH
-21	  OK	WRITE	    WISHBONE LOW
-21	  OK	WRITE	     READ DATA 0
-21	  OK	WRITE	     READ DATA 1
-21	  OK	WRITE	     READ DATA 2
-21	  OK	WRITE	     READ DATA 3
-22	  OK	 READ	     [ADDRESS|0]
-22	  OK	 READ	   WISHBONE HIGH
-22	  OK	 READ	    WISHBONE LOW
-22	  OK	 READ	     [ADDRESS|0]
-23	  OK	WRITE	     [ADDRESS|0]
-23	  OK	WRITE	   WISHBONE HIGH
-23	  OK	WRITE	    WISHBONE LOW
-23	  OK	WRITE	     READ DATA 0
-23	  OK	WRITE	     READ DATA 1
-23	  OK	WRITE	     READ DATA 2
-23	  OK	WRITE	     READ DATA 3
-24	  OK	 READ	     [ADDRESS|0]
-24	  OK	 READ	   WISHBONE HIGH
-24	  OK	 READ	    WISHBONE LOW
-24	  OK	 READ	     [ADDRESS|0]
-25	  OK	WRITE	     [ADDRESS|0]
-25	  OK	WRITE	   WISHBONE HIGH
-25	  OK	WRITE	    WISHBONE LOW
-25	  OK	WRITE	     READ DATA 0
-25	  OK	WRITE	     READ DATA 1
-25	  OK	WRITE	     READ DATA 2
-25	  OK	WRITE	     READ DATA 3
-26	  OK	 READ	     [ADDRESS|0]
-26	  OK	 READ	   WISHBONE HIGH
-26	  OK	 READ	    WISHBONE LOW
-26	  OK	 READ	     [ADDRESS|0]
-27	  OK	WRITE	     [ADDRESS|0]
-27	  OK	WRITE	   WISHBONE HIGH
-27	  OK	WRITE	    WISHBONE LOW
-27	  OK	WRITE	     READ DATA 0
-27	  OK	WRITE	     READ DATA 1
-27	  OK	WRITE	     READ DATA 2
-27	  OK	WRITE	     READ DATA 3
-28	  OK	 READ	     [ADDRESS|0]
-28	  OK	 READ	   WISHBONE HIGH
-28	  OK	 READ	    WISHBONE LOW
-28	  OK	 READ	     [ADDRESS|0]
-29	  OK	WRITE	     [ADDRESS|0]
-29	  OK	WRITE	   WISHBONE HIGH
-29	  OK	WRITE	    WISHBONE LOW
-29	  OK	WRITE	     READ DATA 0
-29	  OK	WRITE	     READ DATA 1
-29	  OK	WRITE	     READ DATA 2
-29	  OK	WRITE	     READ DATA 3
-30	  OK	 READ	     [ADDRESS|0]
-30	  OK	 READ	   WISHBONE HIGH
-30	  OK	 READ	    WISHBONE LOW
-30	  OK	 READ	     [ADDRESS|0]
-31	  OK	WRITE	     [ADDRESS|0]
-31	  OK	WRITE	   WISHBONE HIGH
-31	  OK	WRITE	    WISHBONE LOW
-31	  OK	WRITE	     READ DATA 0
-31	  OK	WRITE	     READ DATA 1
-31	  OK	WRITE	   
\ No newline at end of file
--- a/hdl/bicolor_led_ctrl/README
+++ b/hdl/bicolor_led_ctrl/README
+Taken from:
+
+http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
+
+Revision: 220c7837
--- a/hdl/bicolor_led_ctrl/bicolor_led_ctrl.vhd
+++ b/hdl/bicolor_led_ctrl/bicolor_led_ctrl.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- Bi-color LED controller
+-- http://www.ohwr.org/projects/svec
+--------------------------------------------------------------------------------
+--
+-- unit name: bicolor_led_ctrl
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 11-07-2012
+--
+-- version: 1.0
+--
+-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
+--              The FPGA ouputs for the columns (C) are connected to buffers
+--              and serial resistances and then to the LEDs. The FPGA outputs
+--              for lines (L) are connected to tri-state buffers and the to
+--              the LEDs. The FPGA outputs for lines output enable (L_OEN) are
+--              connected to the output enable of the tri-state buffers.
+--
+--   Example with three lines and two columns:
+--
+--              |<refresh period>|
+--
+--   L1/L2/L3   __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
+--
+--   L1_OEN     -----|___________|-----|___________|-----|___________|-----|___________|--
+--
+--   L2_OEN     _____|-----|___________|-----|___________|-----|___________|-----|________
+--
+--   L3_OEN     ___________|-----|___________|-----|___________|-----|___________|-----|__
+--
+--   Cn         __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
+--
+--   LED Ln/Cn         OFF       |     color_1     |     color_2     |   both_colors   |
+--
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+library work;
+use work.bicolor_led_ctrl_pkg.all;
+
+
+entity bicolor_led_ctrl is
+  generic(
+    g_NB_COLUMN    : natural := 4;
+    g_NB_LINE      : natural := 2;
+    g_CLK_FREQ     : natural := 125000000;  -- in Hz
+    g_REFRESH_RATE : natural := 250         -- in Hz
+    );
+  port
+    (
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+
+      led_intensity_i : in std_logic_vector(6 downto 0);
+
+      led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
+
+      column_o   : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
+      line_o     : out std_logic_vector(g_NB_LINE - 1 downto 0);
+      line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
+      );
+end bicolor_led_ctrl;
+
+
+
+architecture rtl of bicolor_led_ctrl is
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- Constants declaration
+  ------------------------------------------------------------------------------
+  constant c_REFRESH_CNT_INIT     : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
+  constant c_REFRESH_CNT_NB_BITS  : natural := log2_ceil(c_REFRESH_CNT_INIT);
+  constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
+
+
+  ------------------------------------------------------------------------------
+  -- Signals declaration
+  ------------------------------------------------------------------------------
+  signal refresh_rate_cnt   : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
+  signal refresh_rate       : std_logic;
+  signal line_ctrl          : std_logic;
+  signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
+  signal intensity_ctrl     : std_logic;
+  signal line_oen_cnt       : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
+  signal line_oen           : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
+  signal led_state          : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
+
+
+begin
+
+  ------------------------------------------------------------------------------
+  -- Refresh rate counter
+  ------------------------------------------------------------------------------
+  p_refresh_rate_cnt : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        refresh_rate_cnt <= (others => '0');
+        refresh_rate     <= '0';
+      elsif refresh_rate_cnt = 0 then
+        refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
+        refresh_rate     <= '1';
+      else
+        refresh_rate_cnt <= refresh_rate_cnt - 1;
+        refresh_rate     <= '0';
+      end if;
+    end if;
+  end process p_refresh_rate_cnt;
+
+
+  ------------------------------------------------------------------------------
+  -- Intensity control
+  ------------------------------------------------------------------------------
+  p_intensity_ctrl_cnt : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        intensity_ctrl_cnt <= (others => '0');
+      elsif refresh_rate = '1' then
+        intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
+      else
+        intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
+      end if;
+    end if;
+  end process p_intensity_ctrl_cnt;
+
+  p_intensity_ctrl : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        intensity_ctrl <= '0';
+      elsif refresh_rate = '1' then
+        intensity_ctrl <= '1';
+      elsif intensity_ctrl_cnt = 0 then
+        intensity_ctrl <= '0';
+      end if;
+    end if;
+  end process p_intensity_ctrl;
+
+
+  ------------------------------------------------------------------------------
+  -- Lines ouput
+  ------------------------------------------------------------------------------
+  p_line_ctrl : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        line_ctrl <= '0';
+      elsif refresh_rate = '1' then
+        line_ctrl <= not(line_ctrl);
+      end if;
+    end if;
+  end process p_line_ctrl;
+
+  f_line_o : for I in 0 to g_NB_LINE - 1 generate
+    line_o(I) <= line_ctrl and intensity_ctrl;
+  end generate f_line_o;
+
+  ------------------------------------------------------------------------------
+  -- Lines output enable
+  ------------------------------------------------------------------------------
+  p_line_oen_cnt : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        line_oen_cnt <= (others => '0');
+      elsif line_ctrl = '1' and refresh_rate = '1' then
+        if line_oen_cnt = 0 then
+          line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
+        else
+          line_oen_cnt <= line_oen_cnt - 1;
+        end if;
+      end if;
+    end if;
+  end process p_line_oen_cnt;
+
+  p_line_oen_decode : process(line_oen_cnt)
+    variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
+    variable v_index  : integer range 0 to (2**line_oen_cnt'length)-1;
+  begin
+    v_onehot := (others => '0');
+    v_index  := 0;
+    for i in line_oen_cnt'range loop
+      if (line_oen_cnt(i) = '1') then
+        v_index := 2*v_index+1;
+      else
+        v_index := 2*v_index;
+      end if;
+    end loop;
+    v_onehot(v_index) := '1';
+    line_oen          <= v_onehot;
+  end process p_line_oen_decode;
+
+  line_oen_o <= line_oen(line_oen_o'left downto 0);
+
+
+  ------------------------------------------------------------------------------
+  -- Columns output
+  ------------------------------------------------------------------------------
+  f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
+    led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
+                    '1'                               when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
+                    (line_ctrl and intensity_ctrl)    when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF   else
+                    not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN;
+  end generate f_led_state;
+
+  f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
+    column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
+  end generate f_column_o;
+
+
+end rtl;
--- a/hdl/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd
+++ b/hdl/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- Bi-color LED controller package
+-- http://www.ohwr.org/projects/svec
+--------------------------------------------------------------------------------
+--
+-- unit name: bicolor_led_ctrl_pkg
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 11-07-2012
+--
+-- version: 1.0
+--
+-- description: Package for Bi-color LED controller.
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+package bicolor_led_ctrl_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Constants declaration
+  ------------------------------------------------------------------------------
+  constant c_LED_RED       : std_logic_vector(1 downto 0) := "10";
+  constant c_LED_GREEN     : std_logic_vector(1 downto 0) := "01";
+  constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
+  constant c_LED_OFF       : std_logic_vector(1 downto 0) := "00";
+
+  ------------------------------------------------------------------------------
+  -- Functions declaration
+  ------------------------------------------------------------------------------
+  function log2_ceil(N : natural) return positive;
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+  component bicolor_led_ctrl
+    generic(
+      g_NB_COLUMN    : natural := 4;
+      g_NB_LINE      : natural := 2;
+      g_CLK_FREQ     : natural := 125000000;  -- in Hz
+      g_REFRESH_RATE : natural := 250         -- in Hz
+      );
+    port
+      (
+        rst_n_i         : in  std_logic;
+        clk_i           : in  std_logic;
+        led_intensity_i : in  std_logic_vector(6 downto 0);
+        led_state_i     : in  std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
+        column_o        : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
+        line_o          : out std_logic_vector(g_NB_LINE - 1 downto 0);
+        line_oen_o      : out std_logic_vector(g_NB_LINE - 1 downto 0)
+        );
+  end component;
+
+end bicolor_led_ctrl_pkg;
+
+
+package body bicolor_led_ctrl_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Function : Returns log of 2 of a natural number
+  ------------------------------------------------------------------------------
+  function log2_ceil(N : natural) return positive is
+  begin
+    if N <= 2 then
+      return 1;
+    elsif N mod 2 = 0 then
+      return 1 + log2_ceil(N/2);
+    else
+      return 1 + log2_ceil((N+1)/2);
+    end if;
+  end;
+
+end bicolor_led_ctrl_pkg;