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Commit 078498ba authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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multiboot completely revamped. Synthesizable is achieved but a lot of bugs.… 

multiboot completely revamped. Synthesizable is achieved but a lot of bugs. Still needs to be simulated.
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hdl/multiboot/rtl/multiboot_core.vhd
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hdl/multiboot/rtl/multiboot_pkg.vhd 0 → 100644
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hdl/multiboot/rtl/multiboot_regs.vhd
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hdl/multiboot/rtl/multiboot_top.vhd
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 14:13:02 02/21/2012
-- Design Name: multiboot module
-- Module Name: multiboot_top - Behavioral
-- Project Name: CONV-TTL-BLO
-- Target Devices: Spartan 6 LX45T
-- Tool versions: ISE 13.3
-- Description: This is the top module for the multiboot core.
-- It is a wishbone to ICAP programmer. The module consists of
-- three files: the top (multiboot_top.vhd), the registers
-- offered via wishbone (multiboot_regs.vhd) and the core
-- logic that uses multiboot_regs.vhd regs to be applied to
-- specific Spartan 6 registers via ICAP.
--
-- Dependencies: WARNING: platform specific. The core uses the following
-- Spartan 6 primitives:
-- - ICAP_SPARTAN6
--
-- Revision Comment
-- 0.01 File Created
-- 0.2 Modified to link readback register from ICAP
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use work.multiboot_pkg.ALL;
entity multiboot_top is
port(
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end multiboot_top;
architecture Behavioral of multiboot_top is
signal CTRL0_s : STD_LOGIC_VECTOR(15 downto 0);
signal CTRL1_s : STD_LOGIC_VECTOR(15 downto 0);
signal STAT_ICAP_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL1_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL2_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL3_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL4_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL1_ICAP_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL2_ICAP_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL3_ICAP_s : STD_LOGIC_VECTOR(15 downto 0);
signal GENERAL4_ICAP_s : STD_LOGIC_VECTOR(15 downto 0);
component multiboot_core
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
CTRL0_i : in STD_LOGIC_VECTOR (15 downto 0);
CTRL1_o : out STD_LOGIC_VECTOR (15 downto 0);
STAT_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component multiboot_regs
port(
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
CTRL0_o : out STD_LOGIC_VECTOR (15 downto 0);
CTRL1_i : in STD_LOGIC_VECTOR (15 downto 0);
STAT_ICAP_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_ICAP_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_ICAP_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_ICAP_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_ICAP_i : in STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_STAT : r_STAT;
signal s_MBA : r_BAR;
signal s_GBA : r_BAR;
signal s_MBA_addr : STD_LOGIC_VECTOR(23 downto 0);
signal s_GBA_addr : STD_LOGIC_VECTOR(23 downto 0);
begin
multiboot_regs_inst : multiboot_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
CTRL0_o => CTRL0_s,
CTRL1_i => CTRL1_s,
STAT_ICAP_i => STAT_ICAP_s,
GENERAL1_o => GENERAL1_s,
GENERAL2_o => GENERAL2_s,
GENERAL3_o => GENERAL3_s,
GENERAL4_o => GENERAL4_s,
GENERAL1_ICAP_i => GENERAL1_ICAP_s,
GENERAL2_ICAP_i => GENERAL2_ICAP_s,
GENERAL3_ICAP_i => GENERAL3_ICAP_s,
GENERAL4_ICAP_i => GENERAL4_ICAP_s
);
port map(wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
CTR0_o => s_CTR0,
CTR1_i => s_CTR1,
STAT_i => s_STAT,
MBA_o => s_MBA,
GBA_o => s_GBA,
MBA_ICAP_i => s_MBA_addr,
GBA_ICAP_i => s_GBA_addr);
multiboot_core_inst: multiboot_core
port map(
clk => wb_clk,
rst => wb_rst_i,
CTRL0_i => CTRL0_s,
CTRL1_o => CTRL1_s,
STAT_ICAP_o => STAT_ICAP_s,
GENERAL1_i => GENERAL1_s,
GENERAL2_i => GENERAL2_s,
GENERAL3_i => GENERAL3_s,
GENERAL4_i => GENERAL4_s,
GENERAL1_ICAP_o => GENERAL1_ICAP_s,
GENERAL2_ICAP_o => GENERAL2_ICAP_s,
GENERAL3_ICAP_o => GENERAL3_ICAP_s,
GENERAL4_ICAP_o => GENERAL4_ICAP_s
);
port map(clk => wb_clk,
rst => wb_rst_i,
CTR0_i => s_CTR0,
CTR1_o => s_CTR1,
STAT_o => s_STAT,
MBA_i => s_MBA,
GBA_i => s_GBA,
MBA_ICAP_o => s_MBA_addr,
GBA_ICAP_o => s_GBA_addr);
end Behavioral;
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