Skip to content

C
Conv TTL Blocking
Commit 0a562a82 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

Merged with code-cleanup branch.

parents 9a13e613 18145f41
Hide whitespace changes
Inline Side-by-side
Showing with 364 additions and 502 deletions
hdl/IMAGES/image1/.gitignore
View file @ 0a562a82
......@@ -11,7 +11,7 @@
#Ignore autotrash from ISE
project/*
project/*/
!project/image1.gise
# !project/image1.gise
!project/image1.xise
!project/image1.tcl
#!project/waveform/
......
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 0a562a82
......@@ -7,8 +7,8 @@
##----------------------------------------
NET "rst_i" LOC = N20;
NET "rst_i" IOSTANDARD = LVTTL;
NET "RST" LOC = N20;
NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL;
......@@ -371,18 +371,18 @@ NET "LEVEL" IOSTANDARD = LVCMOS33;
##--
##-- + ACT: CMOS 3.3V input
##-------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[0]" LOC = V21;
NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[1]" LOC = V22;
NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMM_N[2]" LOC = U22;
NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[0]" LOC = W22;
NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
###-------------------
###-- General purpose
###--
......
hdl/IMAGES/image1/project/image1.gise deleted 100644 → 0
View file @ 9a13e613
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="image1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="image1_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="image1_top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="image1_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="image1_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="image1_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="image1_top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="image1_top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="image1_top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="image1_top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="image1_top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="image1_top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="image1_top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="image1_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="image1_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="image1_top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="image1_top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="image1_top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="image1_top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="image1_top.xst"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="image1_top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="image1_top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="image1_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_par.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="image1_top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="image1_top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361527932" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361527913">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="image1_top.lso"/>
<outfile xil_pn:name="image1_top.ngc"/>
<outfile xil_pn:name="image1_top.ngr"/>
<outfile xil_pn:name="image1_top.prj"/>
<outfile xil_pn:name="image1_top.stx"/>
<outfile xil_pn:name="image1_top.syr"/>
<outfile xil_pn:name="image1_top.xst"/>
<outfile xil_pn:name="image1_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1361520115" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361520115">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361527939" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361527932">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="image1_top.bld"/>
<outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361527975" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361527939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="image1_top.pcf"/>
<outfile xil_pn:name="image1_top_map.map"/>
<outfile xil_pn:name="image1_top_map.mrp"/>
<outfile xil_pn:name="image1_top_map.ncd"/>
<outfile xil_pn:name="image1_top_map.ngm"/>
<outfile xil_pn:name="image1_top_map.xrpt"/>
<outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1361528015" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361527975">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="image1_top.ncd"/>
<outfile xil_pn:name="image1_top.pad"/>
<outfile xil_pn:name="image1_top.par"/>
<outfile xil_pn:name="image1_top.ptwx"/>
<outfile xil_pn:name="image1_top.unroutes"/>
<outfile xil_pn:name="image1_top.xpi"/>
<outfile xil_pn:name="image1_top_pad.csv"/>
<outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361528034" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361528015">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="image1_top.bgn"/>
<outfile xil_pn:name="image1_top.bit"/>
<outfile xil_pn:name="image1_top.drc"/>
<outfile xil_pn:name="image1_top.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1361528034" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361528034">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1361528015" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361528007">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="image1_top.twr"/>
<outfile xil_pn:name="image1_top.twx"/>
</transform>
</transforms>
</generated_project>
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 0a562a82
......@@ -62,24 +62,24 @@ entity image1_core is
-- LEDs
led_array_o : out t_led_array_o;
led_front_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_front_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
-- I/Os for pulses
pulse_i_front_n : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in std_logic_vector(4 downto 1);
pulse_front_n_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
inv_n_i : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
-- Lines for the i2c_slave
-- Lines for the I2C slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
-- FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
......@@ -87,10 +87,10 @@ entity image1_core is
-- Enable signals
fpga_o_en : out std_logic;
fpga_o_blo_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
fpga_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
-- Level and switch inputs
level_i : in std_logic;
......@@ -112,6 +112,45 @@ architecture Behavioral of image1_core is
--============================================================================
-- Component declarations
--============================================================================
component basic_trigger_top
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_en_o : out STD_LOGIC;
fpga_ttl_en_o : out STD_LOGIC;
fpga_inv_en_o : out STD_LOGIC;
fpga_blo_en_o : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_front_i : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_i : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_front_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_rear_o : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)
);
end component;
-- Trigger leds I2C test component
component test_trigleds_wb is
port
......@@ -140,10 +179,10 @@ architecture Behavioral of image1_core is
);
port
(
sda_oen : out std_logic;
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_oen : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
......@@ -154,9 +193,9 @@ architecture Behavioral of image1_core is
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_data_i : in std_logic_vector(31 downto 0);
wb_master_data_o : out std_logic_vector(31 downto 0);
wb_master_addr_o : out std_logic_vector(15 downto 0);
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
......@@ -165,9 +204,9 @@ architecture Behavioral of image1_core is
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_data_i : in std_logic_vector(31 downto 0);
wb_slave_data_o : out std_logic_vector(31 downto 0);
wb_slave_addr_i : in std_logic_vector(3 downto 0);
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
......@@ -195,43 +234,43 @@ architecture Behavioral of image1_core is
-- Signal declarations
--============================================================================
-- Clock and reset signals
signal clk_buf_50 : std_logic;
signal clk_50 : std_logic;
signal clk_buf_200 : std_logic;
signal clk_200 : std_logic;
signal pll_fb_out : std_logic;
signal pll_fb_in : std_logic;
signal rst_n : std_logic;
signal clk_buf_50 : std_logic;
signal clk_50 : std_logic;
signal clk_buf_200 : std_logic;
signal clk_200 : std_logic;
signal pll_fb_out : std_logic;
signal pll_fb_in : std_logic;
signal rst_n : std_logic;
-- Signal to indicate the lock status of the PLL
signal pll_locked : std_logic;
signal pll_locked : std_logic;
-- RTM detection signals
signal rtmm_ok : std_logic;
signal rtmp_ok : std_logic;
signal rtmm_ok : std_logic;
signal rtmp_ok : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_NUM_SLAVES - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_NUM_SLAVES - 1 downto 0);
signal xbar_slave_in : t_wishbone_slave_in_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_NUM_MASTERS - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_NUM_SLAVES - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array (c_NUM_SLAVES - 1 downto 0);
-- Internal I2C signals
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_rd_done : std_logic;
signal i2c_wr_done : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_rd_done : std_logic;
signal i2c_wr_done : std_logic;
signal i2c_up : std_logic;
-- Internal pulse signal
signal pulse_front_in : std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
signal pulse_front_in : std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
-- Internal signals for bicolor LED matrix control
signal leds_array : t_leds_array;
signal leds_array : t_leds_array;
signal led_state_array : t_led_state_array(c_NB_ARRAY_LEDS - 1 downto 0);
-- !!!!!!!!!!!!!!!!!!!
-- I2C test front panel LED signal
signal trigleds : std_logic_vector(5 downto 0);
signal trigleds : std_logic_vector(5 downto 0);
begin
......@@ -242,10 +281,10 @@ begin
rst_n <= not(rst_i);
-- Negate input pulses, due to the Schmitt trigger inverter on the board
pulse_front_in <= not(pulse_i_front_n);
pulse_front_in <= not(pulse_front_n_i);
-- Assign the I2C address based on the geographical address lines (see [1])
i2c_addr <= "10" & FPGA_GA;
i2c_addr <= "10" & fpga_ga_i;
--============================================================================
-- Generation of internal clock signals
......@@ -317,30 +356,30 @@ begin
cmp_basic_trigger: basic_trigger_top
generic map
(
g_NUMBER_OF_CHANNELS => c_NUMBER_OF_CHANNELS,
g_CLK_PERIOD => c_CLKB_PERIOD,
g_OUTPUT_PULSE_LENGTH => c_OUTPUT_PULSE_LENGTH,
g_LED_BLINKING_LENGTH => c_LED_BLINKING_LENGTH
g_NUMBER_OF_CHANNELS => c_NUMBER_OF_CHANNELS,
g_CLK_PERIOD => c_CLKB_PERIOD,
g_OUTPUT_PULSE_LENGTH => c_OUTPUT_PULSE_LENGTH,
g_LED_BLINKING_LENGTH => c_LED_BLINKING_LENGTH
)
port map
(
clk_i => clk_200,
rst_i => rst_i, -- s_rst.SYS_B(c_RST_B_CLKS - 1),
led_ttl_o => leds_array.top.TTL_N,
fpga_o_en => fpga_o_en,
fpga_o_ttl_en => fpga_o_ttl_en,
fpga_o_inv_en => fpga_o_inv_en,
fpga_o_blo_en => fpga_o_blo_en,
fpga_en_o => fpga_en_o,
fpga_ttl_en_o => fpga_ttl_en_o,
fpga_inv_en_o => fpga_inv_en_o,
fpga_blo_en_o => fpga_blo_en_o,
level_i => level_i,
switch_i => switch_i,
manual_rst_n_o => manual_rst_n_o,
pulse_i_front => pulse_front_in,
pulse_o_front => pulse_o_front,
pulse_i_rear => pulse_i_rear,
pulse_o_rear => pulse_o_rear,
led_o_front => open, -- led_front_n,
led_o_rear => led_rear_n,
inv_i => inv_i_n,
pulse_front_i => pulse_front_in,
pulse_front_o => pulse_front_o,
pulse_rear_i => pulse_rear_i,
pulse_rear_o => pulse_rear_o,
led_front_o => open, -- led_front_n_o,
led_rear_o => led_rear_n_o,
inv_i => inv_n_i,
inv_o => inv_o
);
......@@ -357,38 +396,38 @@ begin
cmp_i2c_slave: i2c_slave_top
port map
(
sda_oen => i2c_slave_o.SDA_OE,
sda_i => i2c_slave_i.SDA_I,
sda_o => i2c_slave_o.SDA_O,
scl_oen => i2c_slave_o.SCL_OE,
scl_i => i2c_slave_i.SCL_I,
scl_o => i2c_slave_o.SCL_O,
wb_clk_i => clk_50,
wb_rst_i => rst_i,
wb_master_stb_o => xbar_slave_in(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => xbar_slave_in(c_MASTER_I2C_SLAVE).cyc,
wb_master_sel_o => xbar_slave_in(c_MASTER_I2C_SLAVE).sel,
wb_master_we_o => xbar_slave_in(c_MASTER_I2C_SLAVE).we,
wb_master_data_i => xbar_slave_out(c_MASTER_I2C_SLAVE).dat,
wb_master_data_o => xbar_slave_in(c_MASTER_I2C_SLAVE).dat,
wb_master_addr_o => xbar_slave_in(c_MASTER_I2C_SLAVE).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(c_MASTER_I2C_SLAVE).ack,
wb_master_rty_i => xbar_slave_out(c_MASTER_I2C_SLAVE).rty,
wb_master_err_i => xbar_slave_out(c_MASTER_I2C_SLAVE).err,
wb_slave_stb_i => xbar_master_out(c_SLAVE_I2C_SLAVE).stb,
wb_slave_cyc_i => xbar_master_out(c_SLAVE_I2C_SLAVE).cyc,
wb_slave_sel_i => xbar_master_out(c_SLAVE_I2C_SLAVE).sel,
wb_slave_we_i => xbar_master_out(c_SLAVE_I2C_SLAVE).we,
wb_slave_data_i => xbar_master_out(c_SLAVE_I2C_SLAVE).dat,
wb_slave_data_o => xbar_master_in(c_SLAVE_I2C_SLAVE).dat,
wb_slave_addr_i => xbar_master_out(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
wb_slave_ack_o => xbar_master_in(c_SLAVE_I2C_SLAVE).ack,
wb_slave_rty_o => xbar_master_in(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => xbar_master_in(c_SLAVE_I2C_SLAVE).err,
pf_wb_addr_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => i2c_addr
sda_en_o => i2c_slave_o.SDA_OE,
sda_i => i2c_slave_i.SDA_I,
sda_o => i2c_slave_o.SDA_O,
scl_en_o => i2c_slave_o.SCL_OE,
scl_i => i2c_slave_i.SCL_I,
scl_o => i2c_slave_o.SCL_O,
wb_clk_i => clk_50,
wb_rst_i => rst_i,
wb_master_stb_o => xbar_slave_in(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => xbar_slave_in(c_MASTER_I2C_SLAVE).cyc,
wb_master_sel_o => xbar_slave_in(c_MASTER_I2C_SLAVE).sel,
wb_master_we_o => xbar_slave_in(c_MASTER_I2C_SLAVE).we,
wb_master_dat_i => xbar_slave_out(c_MASTER_I2C_SLAVE).dat,
wb_master_dat_o => xbar_slave_in(c_MASTER_I2C_SLAVE).dat,
wb_master_adr_o => xbar_slave_in(c_MASTER_I2C_SLAVE).adr(15 downto 0),
wb_master_ack_i => xbar_slave_out(c_MASTER_I2C_SLAVE).ack,
wb_master_rty_i => xbar_slave_out(c_MASTER_I2C_SLAVE).rty,
wb_master_err_i => xbar_slave_out(c_MASTER_I2C_SLAVE).err,
wb_slave_stb_i => xbar_master_out(c_SLAVE_I2C_SLAVE).stb,
wb_slave_cyc_i => xbar_master_out(c_SLAVE_I2C_SLAVE).cyc,
wb_slave_sel_i => xbar_master_out(c_SLAVE_I2C_SLAVE).sel,
wb_slave_we_i => xbar_master_out(c_SLAVE_I2C_SLAVE).we,
wb_slave_dat_i => xbar_master_out(c_SLAVE_I2C_SLAVE).dat,
wb_slave_dat_o => xbar_master_in(c_SLAVE_I2C_SLAVE).dat,
wb_slave_adr_i => xbar_master_out(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
wb_slave_ack_o => xbar_master_in(c_SLAVE_I2C_SLAVE).ack,
wb_slave_rty_o => xbar_master_in(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => xbar_master_in(c_SLAVE_I2C_SLAVE).err,
pf_wb_addr_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => i2c_addr
);
xbar_slave_in(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
......@@ -504,7 +543,7 @@ begin
);
-- !!!!!
led_front_n <= not trigleds;
led_front_n_o <= not trigleds;
--============================================================================
-- RTM detection module
......
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 0a562a82
......@@ -119,38 +119,38 @@ package image1_pkg is
c_mask_trigleds_wb,
c_MASK_I2C_SLAVE);
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component;
-- component basic_trigger_top
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
-- g_CLK_PERIOD : TIME := 20 ns;
-- g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
-- g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
-- port (clk_i : in STD_LOGIC;
-- rst_i : in STD_LOGIC;
--
-- led_ttl_o : out STD_LOGIC;
--
-- fpga_o_en : out STD_LOGIC;
-- fpga_o_ttl_en : out STD_LOGIC;
-- fpga_o_inv_en : out STD_LOGIC;
-- fpga_o_blo_en : out STD_LOGIC;
--
-- level_i : in STD_LOGIC;
-- switch_i : in STD_LOGIC; --! General enable
-- manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
-- --! 24V rail after a security given
-- --! delay
-- pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
-- led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
-- inv_i : in STD_LOGIC_VECTOR(4 downto 1);
-- inv_o : out STD_LOGIC_VECTOR(4 downto 1));
-- end component;
-- component i2c_slave_top
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ 0a562a82
......@@ -48,7 +48,7 @@ entity image1_top is
);
port
(
rst_i : in std_logic;
RST : in std_logic;
CLK20_VCXO : in std_logic;
FPGA_CLK_P : in std_logic; --Using the 125MHz clock
FPGA_CLK_N : in std_logic;
......@@ -102,8 +102,8 @@ entity image1_top is
-- RTM identifiers, should match with the expected values
-- TODO: add matching
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
FPGA_RTMM_N : in std_logic_vector(2 downto 0);
FPGA_RTMP_N : in std_logic_vector(2 downto 0)
);
end image1_top;
......@@ -114,54 +114,68 @@ architecture Behavioral of image1_top is
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
); port
);
port
(
rst_i : in std_logic;
clk_20_i : in std_logic;
clk_125_i : in std_logic;
rst_i : in std_logic;
clk_20_i : in std_logic;
clk_125_i : in std_logic;
-- LEDs
led_array_o : out t_led_array_o;
led_array_o : out t_led_array_o;
led_front_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
-- I/Os for pulses
led_front_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
inv_i_n : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
pulse_front_n_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_front_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_rear_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
inv_n_i : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
-- Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o;
-- FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
fpga_o_en : out std_logic;
fpga_o_blo_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
level_i : in std_logic;
switch_i : in std_logic; -- General enable
manual_rst_n_o : out std_logic; -- It allows power sequencing of the
-- 24V rail after a security given delay
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0)
spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o;
-- Enable signals
fpga_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
-- Level and switch inputs
level_i : in std_logic;
switch_i : in std_logic;
-- Manual reset, allows power sequencing of the
-- 24V rail after a security given delay
manual_rst_n_o : out std_logic;
-- RTM identifiers
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0)
);
end component;
end component image1_core;
signal clk_125 : std_logic;
signal clk_125 : std_logic;
signal s_led_array : t_led_array_o := c_led_array_default;
signal s_i2c_slave_i : t_i2c_slave_i;
signal i2c_slave : t_i2c_slave_i;
signal s_i2c_slave_o : t_i2c_slave_o;
signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i;
signal s_switch_i : std_logic_vector(1 downto 1);
signal switch : std_logic_vector(1 downto 1);
signal rtmm, rtmp : std_logic_vector(2 downto 0);
......@@ -180,65 +194,65 @@ begin
O => clk_125
);
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
rtmm <= not fpga_rtmm_n_i;
rtmp <= not fpga_rtmp_n_i;
s_switch_i <= EXTRA_SWITCH;
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
i2c_slave.SCL_I <= SCL_I;
i2c_slave.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
rtmm <= not FPGA_RTMM_N;
rtmp <= not FPGA_RTMP_N;
switch <= EXTRA_SWITCH;
cmp_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
port map
(
rst_i => rst_i,
clk_20_i => CLK20_VCXO,
clk_125_i => clk_125,
led_array_o => s_led_array,
led_front_n => PULSE_FRONT_LED_N,
led_rear_n => PULSE_REAR_LED_N,
pulse_i_front_n => FPGA_INPUT_TTL_N,
pulse_o_front => FPGA_OUT_TTL,
pulse_i_rear => FPGA_BLO_IN,
pulse_o_rear => FPGA_TRIG_BLO,
inv_i_n => INV_IN_N,
inv_o => INV_OUT,
i2c_slave_i => s_i2c_slave_i,
i2c_slave_o => s_i2c_slave_o,
FPGA_GA => FPGA_GA ,
FPGA_GAP => FPGA_GAP,
spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o,
fpga_o_en => FPGA_OE,
fpga_o_blo_en => FPGA_BLO_OE,
fpga_o_ttl_en => FPGA_TRIG_TTL_OE,
fpga_o_inv_en => FPGA_INV_OE,
level_i => LEVEL,
switch_i => s_switch_i(1),
manual_rst_n_o => MR_N,
rtmm_i => rtmm,
rtmp_i => rtmp
rst_i => RST,
clk_20_i => CLK20_VCXO,
clk_125_i => clk_125,
led_array_o => s_led_array,
led_front_n_o => PULSE_FRONT_LED_N,
led_rear_n_o => PULSE_REAR_LED_N,
pulse_front_n_i => FPGA_INPUT_TTL_N,
pulse_front_o => FPGA_OUT_TTL,
pulse_rear_i => FPGA_BLO_IN,
pulse_rear_o => FPGA_TRIG_BLO,
inv_n_i => INV_IN_N,
inv_o => INV_OUT,
i2c_slave_i => i2c_slave,
i2c_slave_o => s_i2c_slave_o,
fpga_ga_i => FPGA_GA ,
fpga_gap_i => FPGA_GAP,
spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o,
fpga_en_o => FPGA_OE,
fpga_blo_en_o => FPGA_BLO_OE,
fpga_ttl_en_o => FPGA_TRIG_TTL_OE,
fpga_inv_en_o => FPGA_INV_OE,
level_i => LEVEL,
switch_i => switch(1),
manual_rst_n_o => MR_N,
rtmm_i => rtmm,
rtmp_i => rtmp
);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 0a562a82
......@@ -43,10 +43,10 @@ entity basic_trigger_top is
led_ttl_o : out std_logic;
-- Enable signals
fpga_o_en : out std_logic;
fpga_o_ttl_en : out std_logic;
fpga_o_inv_en : out std_logic;
fpga_o_blo_en : out std_logic;
fpga_en_o : out std_logic;
fpga_ttl_en_o : out std_logic;
fpga_inv_en_o : out std_logic;
fpga_blo_en_o : out std_logic;
level_i : in std_logic;
switch_i : in std_logic;
......@@ -55,14 +55,14 @@ entity basic_trigger_top is
manual_rst_n_o : out std_logic;
-- Front and rear pulse signals
pulse_i_front : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_front : out std_logic_vector(g_number_of_channels downto 1);
pulse_i_rear : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_rear : out std_logic_vector(g_number_of_channels downto 1);
pulse_front_i : in std_logic_vector(g_number_of_channels downto 1);
pulse_front_o : out std_logic_vector(g_number_of_channels downto 1);
pulse_rear_i : in std_logic_vector(g_number_of_channels downto 1);
pulse_rear_o : out std_logic_vector(g_number_of_channels downto 1);
-- Front and rear LED signals
led_o_front : out std_logic_vector(g_number_of_channels downto 1);
led_o_rear : out std_logic_vector(g_number_of_channels downto 1);
led_front_o : out std_logic_vector(g_number_of_channels downto 1);
led_rear_o : out std_logic_vector(g_number_of_channels downto 1);
-- Inverting inputs and outputs
inv_i : in std_logic_vector(4 downto 1);
......@@ -131,21 +131,21 @@ begin
led_ttl_o <= level;
-- pulse signal assignments
pulse_in_front <= pulse_i_front when (level = '0') else
not pulse_i_front;
pulse_in <= pulse_in_front or pulse_i_rear;
pulse_in_front <= pulse_front_i when (level = '0') else
not pulse_front_i;
pulse_in <= pulse_in_front or pulse_rear_i;
fpga_o_en <= fpga_out_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= fpga_out_ttl_en;
fpga_o_inv_en <= fpga_out_inv_en;
fpga_o_blo_en <= fpga_out_blo_en;
fpga_en_o <= fpga_out_en when (switch_i = '0') else '0';
fpga_ttl_en_o <= fpga_out_ttl_en;
fpga_inv_en_o <= fpga_out_inv_en;
fpga_blo_en_o <= fpga_out_blo_en;
led_o_front <= not(led); -- No need of accurate sync, hence we place
led_o_rear <= not(led); -- some combinatorial here.
led_front_o <= not(led); -- No need of accurate sync, hence we place
led_rear_o <= not(led); -- some combinatorial here.
pulse_o_front <= pulse_out when level = '0' else
pulse_front_o <= pulse_out when level = '0' else
not pulse_out;
pulse_o_rear <= pulse_out;
pulse_rear_o <= pulse_out;
-- As we have one Schmitt inverter in the input,
-- and a buffer in the output, there's no need
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 0a562a82
......@@ -38,9 +38,9 @@ entity i2c_regs is
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
......@@ -50,9 +50,9 @@ entity i2c_regs is
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
......@@ -106,7 +106,7 @@ architecture Behavioral of i2c_regs is
begin
wb_master_we_o <= s_wb_master_we_o;
s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i);
s_wb_slave_addr <= UNSIGNED(wb_slave_adr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i);
......@@ -147,8 +147,8 @@ begin
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0');
wb_master_addr_o <= (others => '0');
wb_master_dat_o <= (others => '0');
wb_master_adr_o <= (others => '0');
s_dtx <= (others => '0');
else
case wb_state is
......@@ -165,16 +165,16 @@ begin
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
wb_master_adr_o <= s_wb_addr_rd;
when S1N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
wb_master_adr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_data_i;
s_DTX <= wb_master_dat_i;
when S2P_WB_WR_RQT =>
null;
......@@ -184,16 +184,16 @@ begin
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
wb_master_dat_o <= f_ch_endian(DRXA_i);
wb_master_adr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
wb_master_dat_o <= f_ch_endian(DRXA_i);
wb_master_adr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
-- null;
......@@ -229,7 +229,7 @@ begin
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
-- when c_CTR0_addr =>
-- s_CTR0 <= f_CTR0(wb_slave_data_i);
-- s_CTR0 <= f_CTR0(wb_slave_dat_i);
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
......@@ -238,15 +238,15 @@ begin
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_CTR0);
when c_LT_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_LT);
wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_LT);
when c_DTX_addr =>
wb_slave_data_o <= s_DTX;
wb_slave_dat_o <= s_DTX;
when c_DRXA_addr =>
wb_slave_data_o <= DRXA_i;
wb_slave_dat_o <= DRXA_i;
when c_DRXB_addr =>
wb_slave_data_o <= DRXB_i;
wb_slave_dat_o <= DRXB_i;
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 0a562a82
......@@ -68,10 +68,10 @@ entity i2c_slave_core is
clk_i : in std_logic;
rst_i : in std_logic;
-- I2C pins
sda_oen : out std_logic;
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_oen : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
......@@ -150,7 +150,7 @@ architecture Behavioral of i2c_slave_core is
-- i2c signals
-------------------------------------------------------------------------------
signal s_sda_o : std_logic;
signal s_sda_oen : std_logic;
signal s_sda_en_o : std_logic;
signal s_bit_done : std_logic;
......@@ -244,7 +244,7 @@ begin
s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv));
scl_o <= '1';
scl_oen <= '0';
scl_en_o <= '0';
sda_o <= s_sda_o;
......@@ -266,22 +266,22 @@ begin
end case;
end process;
sda_oen <= s_sda_oen;
sda_en_o <= s_sda_en_o;
p_sda_oen: process(state)
p_sda_en_o: process(state)
begin
s_sda_oen <= '0';
s_sda_en_o <= '0';
case state is
when S2A_I2C_ADDR_ACK =>
s_sda_oen <= '1';
s_sda_en_o <= '1';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_oen <= '1';
s_sda_en_o <= '1';
when S5RA_READ_SDA_ACK =>
s_sda_oen <= '1';
s_sda_en_o <= '1';
when S5W1A_I2C_ADDR_ACK =>
s_sda_oen <= '1';
s_sda_en_o <= '1';
when S5W2_WRITE_SDA =>
s_sda_oen <= '1';
s_sda_en_o <= '1';
when others =>
null;
end case;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 0a562a82
......@@ -163,10 +163,10 @@ package i2c_slave_pkg is
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
......@@ -189,9 +189,9 @@ package i2c_slave_pkg is
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
......@@ -200,9 +200,9 @@ package i2c_slave_pkg is
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 0a562a82
......@@ -32,10 +32,10 @@ entity i2c_slave_top is
);
port
(
sda_oen : out STD_LOGIC;
sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
......@@ -46,9 +46,9 @@ entity i2c_slave_top is
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
......@@ -57,9 +57,9 @@ entity i2c_slave_top is
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
......@@ -100,10 +100,10 @@ begin
clk_i => wb_clk_i,
rst_i => wb_rst_i,
sda_oen => sda_oen,
sda_en_o => sda_en_o,
sda_i => sda_i,
sda_o => sda_o,
scl_oen => scl_oen,
scl_en_o => scl_en_o,
scl_i => scl_i,
scl_o => scl_o,
......@@ -133,9 +133,9 @@ begin
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_data_i => wb_master_data_i,
wb_master_data_o => wb_master_data_o,
wb_master_addr_o => wb_master_addr_o,
wb_master_dat_i => wb_master_dat_i,
wb_master_dat_o => wb_master_dat_o,
wb_master_adr_o => wb_master_adr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
......@@ -144,9 +144,9 @@ begin
wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i,
wb_slave_data_i => wb_slave_data_i,
wb_slave_data_o => wb_slave_data_o,
wb_slave_addr_i => wb_slave_addr_i,
wb_slave_dat_i => wb_slave_dat_i,
wb_slave_dat_o => wb_slave_dat_o,
wb_slave_adr_i => wb_slave_adr_i,
wb_slave_ack_o => wb_slave_ack_o,
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment