Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
\end{small}
\item\begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board general-purpose switches
\\
Eg: SW1.1-- SR.SWITCHES[0] \\ SW1.2-- SR.SWITCHES[1] \\ SW2.1-- SR.SWITCHES[4] \\ SW2.4-- SR.SWITCHES[7] \\ 1 -- switch is ON \\ 0 -- switch is OFF
1 bit per RTM output channel \\ 1 -- line active \\ 0 -- line inactive
\end{small}
\item\begin{small}
{\bf
HWVERS
} [\emph{read-only}]: Hardware version
\\
PCB version - Hardwired on the board \\ Only meaningful for HW v4.0 and over \\ Earlier versions show 0. The register \\ uses 4 bits for the version number and\\ 2 bits for the execution.\\ e.g. \\ 0x010001 -- hw v4.1 \\ 0x010111 -- hw v5.3 \\ 0x00-- hw v3 and earlier
\end{small}
\item\begin{small}
{\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item\begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item\begin{small}
{\bf
FLIM\_PMISSE
} [\emph{read/write}]: Frequency error
\\
1 -- Input above maximum supported frequency \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item\begin{small}
{\bf
FWDG\_PMISSE
} [\emph{read/write}]: Frequency watchdog error
\\
1 -- Pulse over maximum pulse count for given frequency' \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item\begin{small}
{\bf
MPT
} [\emph{write-only}]: Manual Pulse Trigger
\\
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\item\begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CH1TTLPCR - Channel 1 Pulse Counter Register for TTL pulses}
Version 2.1 and earlier of the CONV-TTL-BOARD supports continuous pulse repetition, restricting output
pulse width to 1.2us and a maximum repetition frequency of 4.15 kHz.\\
For boards v4 and later\footnote{Note that version 3 of the boards is a prototyping version with only 3 prototypes available. Although the hardware can support higher frequencies, the gateware release will not offer this feature on this version. This is due to these boards do not pffer the FPGA with the possibility of PCB version recognition (hardwired on V4 boards and later).}, the user is able to select the desired pulse width via a a dip switch as explained in section \cite{sec:switches}. This ability to select between long $1.2\mu s$ pulses and short $250 ns$ pulses means that the board will be able to deliver higher repetition frequencies, but for a limited amount of time. This mode of operation is known as \textbf{Burst mode}. In this mode, the board allows the user to increase repetition frequencies but will start missing pulses once the pre-defined (Embedded in the FPGA) time has ellapsed. Table\cite{table:freq-table} below summaries the frequency ranges available. Figure \cite gives a graph of the supported frequencies in burst mode Vs the amount of time for which repetition is guaranteed. After this time has elapsed the board will start missing some pulses, by lowering its repetition frequency dynamically in order to protect the output circuitry from irreversible damage.
pulse width to 1.2us and a maximum repetition frequency of 4.16 kHz.\\
For boards v4 and later\footnote{Note that version 3 of the boards is a prototyping version with only 3 prototypes available. Although the hardware can support higher frequencies, the gateware release will not offer this feature on this version. This is because these boards do not have PCB or HW version recognition capability (hardwired on V4 boards and later), see Section \ref{sec:diag-pcbvers} of this document.}, the user is able to select the desired pulse width via a a dip switch as explained in Section \ref{sec:switches}. The switch is highlighted in in Fig.\ref{fig:switches-freq}. This ability to select between long $1.2\mu s$ pulses and short $250 ns$ pulses means that the board will be able to deliver higher repetition frequencies if short pulses are selected.
Moreover, for a given pulse width, the board is able to support higher frequencies for varying times, according to an internal thermal model that is designed to protect the board in the case of very high rate repetition. This mode of operation is known as the \textit{Burst mode}. In this mode, the board allows the user to increase repetition frequencies but will start missing pulses once the pre-defined (Embedded in the FPGA) times have ellapsed. Table~\ref{tbl:freq-table} below summaries the frequency ranges available. Figure~\ref{fig:BC-freq-lim} gives a graph of the supported frequencies in burst mode Vs the amount of time for which repetition is guaranteed. After this time has elapsed the board will start missing some pulses, by lowering its repetition frequency dynamically in order to protect the output circuitry from irreversible damage.
\begin{table}[h]
\caption{Maximum pulse repetition frequency}
...
...
@@ -544,17 +553,27 @@ For boards v4 and later\footnote{Note that version 3 of the boards is a prototyp
The PCB version is necessary to the operation of the burst mode. Indeed the FPGA reads out the hardware version,
and depending on whether the board is v4 and later or v3 earlier, will enable or disable this functionality accordingly.
The PCB version is provided to the FPGA via a resistor network offering, 4 bits for the version number
and 2 bits for potential revisions. The value is available in the SR register (SR -- see Appendix~\ref{app:conv-regs-sr})
in two bytes.
So for instance a v4.1 board will be given as "01000001", with the Least significant byte LSB providing the revision number,
and the most significant byte MSB providing the version number. Note that the revision number is only 2 bits so the two most significant bits in the corresponding byte are just padding.\\
Note also that PCB identification is not available in boards v3 and earlier, and therefore the HWVERS field in the SR register will read as all zeroes.
The PCB version is necessary to the operation of the burst mode, see Section\ref{sec:pulse-rep-freq}.
Indeed the FPGA reads out the hardware version,
and depending on whether the board is v4 and later or v3 earlier, will enable or disable this
functionality accordingly.\\
In v4 boards, the PCB version is provided to the FPGA via a resistor network implementing 4 bits
for the version number
and 2 bits for potential revisions. The value is available in the SR register (SR -- see Appendix
~\ref{app:conv-regs-SR})
in 6 bits.
So for instance a v4.1 board will be given as "010001", with the Least significant 2 bits
providing the revision number,
and the most significant byte providing the version number.\\
Note also that PCB identification is not available in boards v3 and earlier, and therefore the
HWVERS field in the SR register will read as all zeroes.
@@ -1274,7 +1289,7 @@ The memory map contains further details about the contents of each register
\label{sec:diag-remote-reset}
The user can remotely reset the FPGA logic inside the CONV-TTL-BLO by writing to
the board's control register at address \textbf{0x008}(see Appendix~\ref{app:conv-regs-cr})
the board's control register at address \textbf{0x008}(see Appendix~\ref{app:conv-regs-CR})
to first unlock the RST bit and then write it high to initiate the reset. When the
reset is initiated, a 100~ms reset pulse is applied to the logic.
...
...
@@ -1350,7 +1365,7 @@ triggering is password-protected.
\end{table}
In order to manually trigger a pulse, the user should write five bytes to the board's control
register at address \textbf{0x008}(CR -- see Appendix~\ref{app:conv-regs-cr}), as shown in
register at address \textbf{0x008}(CR -- see Appendix~\ref{app:conv-regs-CR}), as shown in
Table~\ref{tbl:man-trig}. The MPT field is dual-purpose, as shown in
Figure~\ref{fig:cr-mpt}. Until the magic sequence is input, it should be written with the
bytes in the magic sequence. After that, it should be written with the channel number.
...
...
@@ -1405,10 +1420,11 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
Fallback to golden bitstream & SR.GWVERS & Error when booting from application bitstream,
fallback to golden bitstream occured
(see Section~\ref{sec:reprog-bitstreams})\\
I$^2$C timeout &SR.I2C\_WDTO & An I$^2$C transfer is not completed
I$^2$C timeout &ERR.I2C\_WDTO & An I$^2$C transfer is not completed
within 24~ms (see Section~\ref{sec:comm-timeout})\\
I$^2$C error & SR.I2C\_ERR & Attempted to access a non-memory-mapped address via I$^2$C \\
Missed pulse & SR.PMISSE & Input pulse rejected (see Figure~\ref{fig:pg-op})\\
I$^2$C error & ERR.I2C\_ERR & Attempted to access a non-memory-mapped address via I$^2$C \\
FLIM missed pulse& ERR.FLIM\_PMISSE & Input pulse rejected because the pulse frequency is higher than the maximum of Table~\ref{tbl:freq-table}(Error set by the PG block in Fig.~\ref{fig:pulse-rep})\\
FWDG missed pulse& ERR.FWDG\_PMISSE & Input pulse rejected because the board cannot sustain the input frequency beyond times in Fig.~\ref{fig:BC-freq-lim}(Error set by the BC block in Fig.~\ref{fig:pulse-rep})\\
\hline
\end{tabular}
}
...
...
@@ -1560,7 +1576,7 @@ if a new application bitstream is correctly loaded to the CONV-TTL-BLO flash chi
a power-cycle will be needed to run this new bitstream.
To detect which bitstream is currently running, read the GWVERS field in the
board's status register (SR -- see Appendix~\ref{app:conv-regs-sr}).
board's status register (SR -- see Appendix~\ref{app:conv-regs-SR}).
