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Conv TTL Blocking
Commits
1d4b172e
Commit
1d4b172e
authored
Mar 19, 2013
by
Theodor-Adrian Stana
Browse files
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I2C slave working, starting I2C slave code cleanup.
parent
c76d3cd3
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18 changed files
with
1409 additions
and
393 deletions
+1409
-393
conv_ttl_blo_v2.gise
hdl/release/syn/conv_ttl_blo_v2.gise
+7
-0
i2c_slave.vhd
hdl/vme64x_i2c/rtl/i2c_slave.vhd
+1
-2
vme64x_i2c.vhd
hdl/vme64x_i2c/rtl/vme64x_i2c.vhd
+208
-45
run.do
hdl/vme64x_i2c/sim/run.do
+4
-3
tb_i2c_slave.vhd
hdl/vme64x_i2c/sim/tb_i2c_slave.vhd
+3
-3
tb_vme64x_i2c.vhd
hdl/vme64x_i2c/sim/tb_vme64x_i2c.vhd
+550
-0
transcript
hdl/vme64x_i2c/sim/transcript
+156
-191
wave.do
hdl/vme64x_i2c/sim/wave.do
+38
-54
wave_i2c_slave.do
hdl/vme64x_i2c/sim/wave_i2c_slave.do
+71
-0
conv_ttl_blo_v2.bit
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.bit
+0
-0
conv_ttl_blo_v2.gise
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.gise
+10
-17
conv_ttl_blo_v2.ppr
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.ppr
+27
-0
conv_ttl_blo_v2.xise
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.xise
+9
-5
Manifest.py
hdl/vme64x_i2c/top/Manifest.py
+1
-0
conv_ttl_blo_v2.ucf
hdl/vme64x_i2c/top/conv_ttl_blo_v2.ucf
+24
-24
conv_ttl_blo_v2.vhd
hdl/vme64x_i2c/top/conv_ttl_blo_v2.vhd
+107
-49
test_regs.vhd
hdl/vme64x_i2c/top/test_regs.vhd
+143
-0
test_regs.wb
hdl/vme64x_i2c/top/test_regs.wb
+50
-0
No files found.
hdl/release/syn/conv_ttl_blo_v2.gise
View file @
1d4b172e
...
...
@@ -110,6 +110,7 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForInputs"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/xst.xmsgs"
/>
...
...
@@ -131,6 +132,7 @@
<transform
xil_pn:end_ts=
"1363164509"
xil_pn:in_ck=
"-3184428132143472969"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"7619738475395271108"
xil_pn:start_ts=
"1363164504"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<outfile
xil_pn:name=
"_ngo"
/>
<outfile
xil_pn:name=
"_xmsgs/ngdbuild.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bld"
/>
...
...
@@ -140,6 +142,7 @@
<transform
xil_pn:end_ts=
"1363164539"
xil_pn:in_ck=
"-3184428132143472968"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1363164509"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
...
...
@@ -156,6 +159,7 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ncd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.pad"
/>
...
...
@@ -171,6 +175,7 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<outfile
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bgn"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bit"
/>
...
...
@@ -182,6 +187,7 @@
<transform
xil_pn:end_ts=
"1363164589"
xil_pn:in_ck=
"-7071212854459549799"
xil_pn:name=
"TRAN_configureTargetDevice"
xil_pn:prop_ck=
"4629081730735892968"
xil_pn:start_ts=
"1363164588"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_impact.cmd"
/>
...
...
@@ -192,6 +198,7 @@
<transform
xil_pn:end_ts=
"1363164570"
xil_pn:in_ck=
"-3184428132143473100"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1363164561"
>
<status
xil_pn:value=
"FailedRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<outfile
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.twr"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.twx"
/>
...
...
hdl/vme64x_i2c/rtl/i2c_slave.vhd
View file @
1d4b172e
...
...
@@ -145,7 +145,6 @@ architecture behav of i2c_slave is
signal
sda_falling
:
std_logic
;
signal
sda_rising
:
std_logic
;
-- FSM
signal
state
:
t_state
;
...
...
@@ -334,7 +333,7 @@ begin
sda_o
<=
ack_n_i
;
if
(
scl_falling
=
'1'
)
then
sda_en_o
<=
'0'
;
if
(
ack_n_i
=
'
1
'
)
then
if
(
ack_n_i
=
'
0
'
)
then
state
<=
ST_RD
;
-- done_o <= '0';
else
...
...
hdl/vme64x_i2c/rtl/vme64x_i2c.vhd
View file @
1d4b172e
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT CHANGED
-- Engineer: Carlos Gil Soriano
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: vme64x_i2c - behav
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
-- author: Theodor Stana (t.stana@cern.ch)
--
--
Dependencies:
--
date of creation: 2013-02-15
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- version: 1.0
--
----------------------------------------------------------------------------------
library
IEEE
;
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
library
work
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
NUMERIC_STD
.
ALL
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
vme64x_i2c
is
port
(
-- Clock, reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- I2C lines
sda_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
sda_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
-- I2C address and status
i2c_addr_i
:
in
std_logic_vector
(
6
downto
0
);
i2c_done_o
:
out
std_logic
;
i2c_addr_i
:
in
std_logic_vector
(
6
downto
0
);
i2c_done_o
:
out
std_logic
;
-- Wishbone master signals
wb
_master_stb_o
:
out
std_logic
;
wb
_master_cyc_o
:
out
std_logic
;
wb
_master_sel_o
:
out
std_logic_vector
(
3
downto
0
);
wb
_master_we_o
:
out
std_logic
;
wb
_master_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb
_master_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb
_master_adr_o
:
out
std_logic_vector
(
31
downto
0
);
wb
_master_ack_i
:
in
std_logic
;
wb
_master_rty_i
:
in
std_logic
;
wb
_master_err_i
:
in
std_logic
wb
m_stb_o
:
out
std_logic
;
wb
m_cyc_o
:
out
std_logic
;
wb
m_sel_o
:
out
std_logic_vector
(
3
downto
0
);
wb
m_we_o
:
out
std_logic
;
wb
m_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb
m_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb
m_adr_o
:
out
std_logic_vector
(
31
downto
0
);
wb
m_ack_i
:
in
std_logic
;
wb
m_rty_i
:
in
std_logic
;
wb
m_err_i
:
in
std_logic
);
end
vme64x_i2c
;
end
entity
vme64x_i2c
;
architecture
behav
of
vme64x_i2c
is
--============================================================================
-- Type declarations
--============================================================================
type
t_state
is
(
ST_IDLE
,
ST_WB_ADR
,
ST_OP
,
ST_SYSMON_RD_WB
,
ST_SYSMON_RD
,
ST_SYSMON_WR
,
ST_SYSMON_WR_WB
);
--============================================================================
-- Component declarations
--============================================================================
...
...
@@ -110,11 +141,27 @@ architecture behav of vme64x_i2c is
-- Signal declarations
--============================================================================
-- Slave component signals
signal
ack_n
:
std_logic
;
signal
op
:
std_logic
;
signal
tx_byte
:
std_logic_vector
(
7
downto
0
);
signal
rx_byte
:
std_logic_vector
(
7
downto
0
);
signal
done
:
std_logic
;
signal
ack_n
:
std_logic
;
signal
op
:
std_logic
;
signal
start_op
:
std_logic
;
signal
tx_byte
:
std_logic_vector
(
7
downto
0
);
signal
rx_byte
:
std_logic_vector
(
7
downto
0
);
signal
done
:
std_logic
;
signal
done_d0
:
std_logic
;
-- Wishbone temporary signals
signal
wb_dat_out
:
std_logic_vector
(
31
downto
0
);
signal
wb_dat_in
:
std_logic_vector
(
31
downto
0
);
signal
wb_adr
:
std_logic_vector
(
15
downto
0
);
signal
wb_cyc
:
std_logic
;
signal
wb_stb
:
std_logic
;
signal
wb_we
:
std_logic
;
signal
wb_ack
:
std_logic
;
-- FSM control signals
signal
state
:
t_state
;
signal
dat_byte_cnt
:
unsigned
(
1
downto
0
);
signal
adr_byte_cnt
:
unsigned
(
0
downto
0
);
begin
...
...
@@ -162,5 +209,121 @@ begin
done_o
=>
done
);
i2c_done_o
<=
done
;
--============================================================================
-- I2C to Wishbone bridge FSM logic
--============================================================================
-- First, assign Wishbone outputs
wbm_dat_o
<=
wb_dat_out
;
wbm_adr_o
<=
x"0000"
&
wb_adr
;
wbm_cyc_o
<=
wb_cyc
;
wbm_stb_o
<=
wb_stb
;
wbm_we_o
<=
wb_we
;
wbm_sel_o
<=
(
others
=>
'1'
);
-- Next, assign some Wishbone inputs to internal signals
wb_ack
<=
wbm_ack_i
;
-- Then, assign the I2C byte to TX to the first byte of the internal WB input
-- data signal; shifting is handled inside the FSM.
tx_byte
<=
wb_dat_in
(
7
downto
0
);
-- Finally, the FSM logic
p_fsm
:
process
(
clk_i
)
is
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
state
<=
ST_IDLE
;
wb_adr
<=
(
others
=>
'0'
);
wb_dat_out
<=
(
others
=>
'0'
);
wb_dat_in
<=
(
others
=>
'0'
);
wb_cyc
<=
'0'
;
wb_stb
<=
'0'
;
wb_we
<=
'0'
;
done_d0
<=
'0'
;
start_op
<=
'0'
;
adr_byte_cnt
<=
(
others
=>
'0'
);
dat_byte_cnt
<=
(
others
=>
'0'
);
else
done_d0
<=
done
;
case
state
is
when
ST_IDLE
=>
if
(
done
=
'1'
)
and
(
done_d0
=
'0'
)
then
state
<=
ST_WB_ADR
;
start_op
<=
op
;
end
if
;
when
ST_WB_ADR
=>
if
(
done
=
'1'
)
and
(
done_d0
=
'0'
)
then
wb_adr
<=
wb_adr
(
7
downto
0
)
&
rx_byte
;
ack_n
<=
'0'
;
adr_byte_cnt
<=
adr_byte_cnt
+
1
;
if
(
adr_byte_cnt
=
1
)
then
state
<=
ST_OP
;
end
if
;
end
if
;
when
ST_OP
=>
if
(
done
=
'1'
)
and
(
done_d0
=
'0'
)
then
wb_dat_out
<=
rx_byte
&
wb_dat_out
(
31
downto
8
);
dat_byte_cnt
<=
dat_byte_cnt
+
1
;
ack_n
<=
'0'
;
if
(
op
/=
start_op
)
then
state
<=
ST_SYSMON_RD_WB
;
dat_byte_cnt
<=
(
others
=>
'0'
);
wb_dat_out
<=
(
others
=>
'0'
);
else
state
<=
ST_SYSMON_WR
;
end
if
;
end
if
;
when
ST_SYSMON_WR
=>
if
(
done
=
'1'
)
and
(
done_d0
=
'0'
)
then
wb_dat_out
<=
rx_byte
&
wb_dat_out
(
31
downto
8
);
dat_byte_cnt
<=
dat_byte_cnt
+
1
;
ack_n
<=
'0'
;
if
(
dat_byte_cnt
=
3
)
then
state
<=
ST_SYSMON_WR_WB
;
end
if
;
end
if
;
when
ST_SYSMON_WR_WB
=>
wb_cyc
<=
'1'
;
wb_stb
<=
'1'
;
wb_we
<=
'1'
;
if
(
wb_ack
=
'1'
)
then
wb_cyc
<=
'0'
;
wb_stb
<=
'0'
;
wb_we
<=
'0'
;
state
<=
ST_IDLE
;
end
if
;
when
ST_SYSMON_RD_WB
=>
wb_cyc
<=
'1'
;
wb_stb
<=
'1'
;
if
(
wb_ack
=
'1'
)
then
wb_dat_in
<=
wbm_dat_i
;
wb_cyc
<=
'0'
;
wb_stb
<=
'0'
;
state
<=
ST_SYSMON_RD
;
end
if
;
when
ST_SYSMON_RD
=>
if
(
done
=
'1'
)
and
(
done_d0
=
'0'
)
then
wb_dat_in
<=
x"00"
&
wb_dat_in
(
31
downto
8
);
dat_byte_cnt
<=
dat_byte_cnt
+
1
;
if
(
dat_byte_cnt
=
3
)
then
state
<=
ST_IDLE
;
end
if
;
end
if
;
when
others
=>
state
<=
ST_IDLE
;
end
case
;
end
if
;
end
if
;
end
process
p_fsm
;
end
behav
;
hdl/vme64x_i2c/sim/run.do
View file @
1d4b172e
...
...
@@ -2,16 +2,17 @@ vlib work
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/i2c_slave.vhd"
vcom -explicit -93 "../rtl/vme64x_i2c.vhd"
vcom -explicit -93 "i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "t
estbench
.vhd"
vcom -explicit -93 "t
b_vme64x_i2c
.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.t
estbench
vsim -t 1ps -voptargs="+acc" -lib work work.t
b_vme64x_i2c
radix -hexadecimal
# add wave *
do wave.do
run
1
ms
run
3
ms
wave zoomfull
hdl/vme64x_i2c/sim/t
estbench
.vhd
→
hdl/vme64x_i2c/sim/t
b_i2c_slave
.vhd
View file @
1d4b172e
...
...
@@ -39,11 +39,11 @@ use ieee.std_logic_1164.all;
use
ieee
.
numeric_std
.
all
;
entity
t
estbench
is
end
entity
t
estbench
;
entity
t
b_i2c_slave
is
end
entity
t
b_i2c_slave
;
architecture
behav
of
t
estbench
is
architecture
behav
of
t
b_i2c_slave
is
--============================================================================
-- Type declarations
...
...
hdl/vme64x_i2c/sim/tb_vme64x_i2c.vhd
0 → 100644
View file @
1d4b172e
This diff is collapsed.
Click to expand it.
hdl/vme64x_i2c/sim/transcript
View file @
1d4b172e
This diff is collapsed.
Click to expand it.
hdl/vme64x_i2c/sim/wave.do
View file @
1d4b172e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/rst
add wave -noupdate /testbench/txb
add wave -noupdate /testbench/rxb
add wave -noupdate /testbench/mst_sta
add wave -noupdate /testbench/mst_sto
add wave -noupdate /testbench/mst_rd
add wave -noupdate /testbench/mst_wr
add wave -noupdate /testbench/mst_ack
add wave -noupdate /testbench/mst_dat_in
add wave -noupdate /testbench/mst_dat_out
add wave -noupdate /testbench/mst_cmd_ack
add wave -noupdate /testbench/ack_fr_slv
add wave -noupdate /testbench/addr
add wave -noupdate /testbench/slv_done
add wave -noupdate /testbench/rcvd
add wave -noupdate /testbench/tmp
add wave -noupdate /testbench/state_mst
add wave -noupdate /testbench/state_slv
add wave -noupdate -divider master
add wave -noupdate /testbench/cmp_master/scl_i
add wave -noupdate /testbench/cmp_master/scl_o
add wave -noupdate /testbench/cmp_master/scl_oen
add wave -noupdate /testbench/cmp_master/sda_i
add wave -noupdate /testbench/cmp_master/sda_o
add wave -noupdate /testbench/cmp_master/sda_oen
add wave -noupdate /testbench/cmp_master/din
add wave -noupdate /testbench/cmp_master/dout
add wave -noupdate /testbench/cmp_master/c_state
add wave -noupdate -divider {bit ctrl}
add wave -noupdate /testbench/cmp_master/bit_ctrl/c_state
add wave -noupdate /testbench/cmp_master/bit_ctrl/cmd_ack
add wave -noupdate /testbench/cmp_master/bit_ctrl/clk_en
add wave -noupdate /testbench/cmp_master/bit_ctrl/al
add wave -noupdate /testbench/cmp_master/bit_ctrl/sda_oen
add wave -noupdate /testbench/cmp_master/bit_ctrl/sda_chk
add wave -noupdate /testbench/cmp_master/bit_ctrl/sSDA
add wave -noupdate /tb_vme64x_i2c/clk
add wave -noupdate /tb_vme64x_i2c/rst_n
add wave -noupdate /tb_vme64x_i2c/i2c_done
add wave -noupdate /tb_vme64x_i2c/mst_ack
add wave -noupdate /tb_vme64x_i2c/mst_dat_in
add wave -noupdate /tb_vme64x_i2c/mst_dat_out
add wave -noupdate /tb_vme64x_i2c/mst_cmd_ack
add wave -noupdate /tb_vme64x_i2c/ack_fr_slv
add wave -noupdate /tb_vme64x_i2c/wb_stb
add wave -noupdate /tb_vme64x_i2c/wb_cyc
add wave -noupdate /tb_vme64x_i2c/wb_sel
add wave -noupdate /tb_vme64x_i2c/wb_we
add wave -noupdate /tb_vme64x_i2c/wb_dat_m2s
add wave -noupdate /tb_vme64x_i2c/wb_dat_s2m
add wave -noupdate /tb_vme64x_i2c/wb_adr
add wave -noupdate /tb_vme64x_i2c/wb_ack
add wave -noupdate /tb_vme64x_i2c/state
add wave -noupdate /tb_vme64x_i2c/reg
add wave -noupdate /tb_vme64x_i2c/rcvd
add wave -noupdate /tb_vme64x_i2c/read4
add wave -noupdate /tb_vme64x_i2c/send
add wave -noupdate /tb_vme64x_i2c/wrote4
add wave -noupdate -divider dut
add wave -noupdate /tb_vme64x_i2c/DUT/state
add wave -noupdate /tb_vme64x_i2c/DUT/op
add wave -noupdate /tb_vme64x_i2c/DUT/start_op
add wave -noupdate /tb_vme64x_i2c/DUT/wb_dat_out
add wave -noupdate /tb_vme64x_i2c/DUT/wb_dat_in
add wave -noupdate /tb_vme64x_i2c/DUT/wb_adr
add wave -noupdate /tb_vme64x_i2c/DUT/dat_byte_cnt
add wave -noupdate /tb_vme64x_i2c/DUT/adr_byte_cnt
add wave -noupdate -divider slave
add wave -noupdate /testbench/DUT/scl_i
add wave -noupdate /testbench/DUT/scl_o
add wave -noupdate /testbench/DUT/scl_en_o
add wave -noupdate /testbench/DUT/sda_i
add wave -noupdate /testbench/DUT/sda_o
add wave -noupdate /testbench/DUT/sda_en_o
add wave -noupdate /testbench/DUT/op_o
add wave -noupdate /testbench/DUT/done_o
add wave -noupdate /testbench/DUT/state
add wave -noupdate -radix hexadecimal /testbench/DUT/txsr
add wave -noupdate -radix hexadecimal -childformat {{/testbench/DUT/rxsr(7) -radix hexadecimal} {/testbench/DUT/rxsr(6) -radix hexadecimal} {/testbench/DUT/rxsr(5) -radix hexadecimal} {/testbench/DUT/rxsr(4) -radix hexadecimal} {/testbench/DUT/rxsr(3) -radix hexadecimal} {/testbench/DUT/rxsr(2) -radix hexadecimal} {/testbench/DUT/rxsr(1) -radix hexadecimal} {/testbench/DUT/rxsr(0) -radix hexadecimal}} -subitemconfig {/testbench/DUT/rxsr(7) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(6) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(5) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(4) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(3) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(2) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(1) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(0) {-height 16 -radix hexadecimal}} /testbench/DUT/rxsr
add wave -noupdate -radix unsigned -childformat {{/testbench/DUT/bit_cnt(2) -radix unsigned} {/testbench/DUT/bit_cnt(1) -radix unsigned} {/testbench/DUT/bit_cnt(0) -radix unsigned}} -subitemconfig {/testbench/DUT/bit_cnt(2) {-height 16 -radix unsigned} /testbench/DUT/bit_cnt(1) {-height 16 -radix unsigned} /testbench/DUT/bit_cnt(0) {-height 16 -radix unsigned}} /testbench/DUT/bit_cnt
add wave -noupdate /testbench/DUT/i2c_addr_i
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/state
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/txsr
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/rxsr
add wave -noupdate /tb_vme64x_i2c/DUT/cmp_i2c_slave/bit_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {
310584000
ps} 0}
configure wave -namecolwidth 2
74
configure wave -valuecolwidth 1
27
WaveRestoreCursors {{Cursor 1} {
697592847
ps} 0}
configure wave -namecolwidth 2
61
configure wave -valuecolwidth 1
00
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
...
...
hdl/vme64x_i2c/sim/wave_i2c_slave.do
0 → 100644
View file @
1d4b172e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/rst
add wave -noupdate /testbench/txb
add wave -noupdate /testbench/rxb
add wave -noupdate /testbench/mst_sta
add wave -noupdate /testbench/mst_sto
add wave -noupdate /testbench/mst_rd
add wave -noupdate /testbench/mst_wr
add wave -noupdate /testbench/mst_ack
add wave -noupdate /testbench/mst_dat_in
add wave -noupdate /testbench/mst_dat_out
add wave -noupdate /testbench/mst_cmd_ack
add wave -noupdate /testbench/ack_fr_slv
add wave -noupdate /testbench/addr
add wave -noupdate /testbench/slv_done
add wave -noupdate /testbench/rcvd
add wave -noupdate /testbench/tmp
add wave -noupdate /testbench/state_mst
add wave -noupdate /testbench/state_slv
add wave -noupdate -divider master
add wave -noupdate /testbench/cmp_master/scl_i
add wave -noupdate /testbench/cmp_master/scl_o
add wave -noupdate /testbench/cmp_master/scl_oen
add wave -noupdate /testbench/cmp_master/sda_i
add wave -noupdate /testbench/cmp_master/sda_o
add wave -noupdate /testbench/cmp_master/sda_oen
add wave -noupdate /testbench/cmp_master/din
add wave -noupdate /testbench/cmp_master/dout
add wave -noupdate /testbench/cmp_master/c_state
add wave -noupdate -divider {bit ctrl}
add wave -noupdate /testbench/cmp_master/bit_ctrl/c_state
add wave -noupdate /testbench/cmp_master/bit_ctrl/cmd_ack
add wave -noupdate /testbench/cmp_master/bit_ctrl/clk_en
add wave -noupdate /testbench/cmp_master/bit_ctrl/al
add wave -noupdate /testbench/cmp_master/bit_ctrl/sda_oen
add wave -noupdate /testbench/cmp_master/bit_ctrl/sda_chk
add wave -noupdate /testbench/cmp_master/bit_ctrl/sSDA
add wave -noupdate -divider slave
add wave -noupdate /testbench/DUT/scl_i
add wave -noupdate /testbench/DUT/scl_o
add wave -noupdate /testbench/DUT/scl_en_o
add wave -noupdate /testbench/DUT/sda_i
add wave -noupdate /testbench/DUT/sda_o
add wave -noupdate /testbench/DUT/sda_en_o
add wave -noupdate /testbench/DUT/op_o
add wave -noupdate /testbench/DUT/done_o
add wave -noupdate /testbench/DUT/state
add wave -noupdate -radix hexadecimal /testbench/DUT/txsr
add wave -noupdate -radix hexadecimal -childformat {{/testbench/DUT/rxsr(7) -radix hexadecimal} {/testbench/DUT/rxsr(6) -radix hexadecimal} {/testbench/DUT/rxsr(5) -radix hexadecimal} {/testbench/DUT/rxsr(4) -radix hexadecimal} {/testbench/DUT/rxsr(3) -radix hexadecimal} {/testbench/DUT/rxsr(2) -radix hexadecimal} {/testbench/DUT/rxsr(1) -radix hexadecimal} {/testbench/DUT/rxsr(0) -radix hexadecimal}} -subitemconfig {/testbench/DUT/rxsr(7) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(6) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(5) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(4) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(3) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(2) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(1) {-height 16 -radix hexadecimal} /testbench/DUT/rxsr(0) {-height 16 -radix hexadecimal}} /testbench/DUT/rxsr
add wave -noupdate -radix unsigned -childformat {{/testbench/DUT/bit_cnt(2) -radix unsigned} {/testbench/DUT/bit_cnt(1) -radix unsigned} {/testbench/DUT/bit_cnt(0) -radix unsigned}} -subitemconfig {/testbench/DUT/bit_cnt(2) {-height 16 -radix unsigned} /testbench/DUT/bit_cnt(1) {-height 16 -radix unsigned} /testbench/DUT/bit_cnt(0) {-height 16 -radix unsigned}} /testbench/DUT/bit_cnt
add wave -noupdate /testbench/DUT/i2c_addr_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {310584000 ps} 0}
configure wave -namecolwidth 274
configure wave -valuecolwidth 127
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {1050 us}
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.bit
View file @
1d4b172e
No preview for this file type
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.gise
View file @
1d4b172e
...
...
@@ -106,10 +106,12 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
367066"
xil_pn:in_ck=
"2444542867738687589"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"-5659100974288834190"
xil_pn:start_ts=
"1363367056
"
>
<transform
xil_pn:end_ts=
"1363
684728"
xil_pn:in_ck=
"-3906018761073273710"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"-5659100974288834190"
xil_pn:start_ts=
"1363684714
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/xst.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.lso"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ngc"
/>
...
...
@@ -122,25 +124,22 @@
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
<outfile
xil_pn:name=
"xst"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
015781"
xil_pn:in_ck=
"9180755367508499589"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"1934330619683713069"
xil_pn:start_ts=
"1363015781
"
>
<transform
xil_pn:end_ts=
"1363
684812"
xil_pn:in_ck=
"9180755367508499589"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"1934330619683713069"
xil_pn:start_ts=
"1363684812
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
022103"
xil_pn:in_ck=
"-3184428132143472969"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"7619738475395271108"
xil_pn:start_ts=
"1363022098
"
>
<transform
xil_pn:end_ts=
"1363
684817"
xil_pn:in_ck=
"-3184428132143472969"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"7619738475395271108"
xil_pn:start_ts=
"1363684812
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForInputs"
/>
<status
xil_pn:value=
"InputChanged"
/>
<outfile
xil_pn:name=
"_ngo"
/>
<outfile
xil_pn:name=
"_xmsgs/ngdbuild.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bld"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ngd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_ngdbuild.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
022134"
xil_pn:in_ck=
"-3184428132143472968"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1363022103
"
>
<transform
xil_pn:end_ts=
"1363
684849"
xil_pn:in_ck=
"-3184428132143472968"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1363684817
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
...
...
@@ -153,11 +152,10 @@
<outfile
xil_pn:name=
"conv_ttl_blo_v2_summary.xml"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_usage.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
022163"
xil_pn:in_ck=
"-7407895592276768303"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1363022134
"
>
<transform
xil_pn:end_ts=
"1363
684881"
xil_pn:in_ck=
"-7407895592276768303"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1363684849
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.ncd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.pad"
/>
...
...
@@ -169,12 +167,9 @@
<outfile
xil_pn:name=
"conv_ttl_blo_v2_pad.txt"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2_par.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
022181"
xil_pn:in_ck=
"-7071212854459536945"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1363022163
"
>
<transform
xil_pn:end_ts=
"1363
684900"
xil_pn:in_ck=
"-7071212854459536945"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1363684881
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bgn"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.bit"
/>
...
...
@@ -183,10 +178,9 @@
<outfile
xil_pn:name=
"webtalk.log"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
022182"
xil_pn:in_ck=
"-7071212854459549799"
xil_pn:name=
"TRAN_configureTargetDevice"
xil_pn:prop_ck=
"4629081730735892968"
xil_pn:start_ts=
"1363022181
"
>
<transform
xil_pn:end_ts=
"1363
684950"
xil_pn:in_ck=
"-7071212854459549799"
xil_pn:name=
"TRAN_configureTargetDevice"
xil_pn:prop_ck=
"4629081730735892968"
xil_pn:start_ts=
"1363684950
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_impact.cmd"
/>
...
...
@@ -194,10 +188,9 @@
<outfile
xil_pn:name=
"_impactbatch.log"
/>
<outfile
xil_pn:name=
"ise_impact.cmd"
/>
</transform>
<transform
xil_pn:end_ts=
"1363
022163"
xil_pn:in_ck=
"-3184428132143473100"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1363022156
"
>
<transform
xil_pn:end_ts=
"1363
684881"
xil_pn:in_ck=
"-3184428132143473100"
xil_pn:name=
"TRAN_postRouteTrce"
xil_pn:prop_ck=
"445577401284416185"
xil_pn:start_ts=
"1363684874
"
>
<status
xil_pn:value=
"FailedRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForPredecessor"
/>
<outfile
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.twr"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_v2.twx"
/>
...
...
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.ppr
0 → 100644
View file @
1d4b172e
<?xml version="1.0"?>
<Project
Version=
"4"
Minor=
"36"
>
<FileSet
Dir=
"sources_1"
File=
"fileset.xml"
/>
<FileSet
Dir=
"constrs_1"
File=
"fileset.xml"
/>
<FileSet
Dir=
"sim_1"
File=
"fileset.xml"
/>
<RunSet
Dir=
"runs"
File=
"runs.xml"
/>
<DefaultLaunch
Dir=
"$PRUNDIR"
/>
<DefaultPromote
Dir=
"$PROMOTEDIR"
/>
<Config>
<Option
Name=
"Id"
Val=
"bd5a523f03344e4cb161d9e4d8cfc3b5"
/>
<Option
Name=
"Part"
Val=
"xc6slx45tfgg484-3"
/>
<Option
Name=
"CompiledLibDir"
Val=
"$PCACHEDIR/compxlib"
/>
<Option
Name=
"TargetLanguage"
Val=
"VHDL"
/>
<Option
Name=
"TargetSimulator"
Val=
"ISim"
/>
<Option
Name=
"Board"
Val=
""
/>
<Option
Name=
"SourceMgmtMode"
Val=
"DisplayOnly"
/>
<Option
Name=
"ActiveSimSet"
Val=
""
/>
<Option
Name=
"CxlOverwriteLibs"
Val=
"1"
/>
<Option
Name=
"CxlFuncsim"
Val=
"1"
/>
<Option
Name=
"CxlTimesim"
Val=
"1"
/>
<Option
Name=
"CxlCore"
Val=
"1"
/>
<Option
Name=
"CxlEdk"
Val=
"0"
/>
<Option
Name=
"CxlExcludeCores"
Val=
"1"
/>
<Option
Name=
"CxlExcludeSubLibs"
Val=
"0"
/>
</Config>
</Project>
hdl/vme64x_i2c/syn/conv_ttl_blo_v2.xise
View file @
1d4b172e
...
...
@@ -350,19 +350,19 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../top/conv_ttl_blo_v2.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
2
"
/>
</file>
<file
xil_pn:name=
"../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
</file>
<file
xil_pn:name=
"../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
1
"
/>
</file>
<file
xil_pn:name=
"../rtl/i2c_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4"
/>
</file>
<file
xil_pn:name=
"../rtl/vme64x_i2c.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
8
"
/>
</file>
<file
xil_pn:name=
"../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -632,14 +632,18 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../reset_gen/rtl/reset_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
10
"
/>
</file>
<file
xil_pn:name=
"../../rtm_detector/rtl/rtm_detector.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
9
"
/>
</file>
<file
xil_pn:name=
"../../glitch_filt/rtl/glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
</file>
<file
xil_pn:name=
"../top/test_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"155"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7"
/>
</file>
</files>
<bindings/>
...
...
hdl/vme64x_i2c/top/Manifest.py
View file @
1d4b172e
files
=
[
"conv_ttl_blo_v2.ucf"
,
"test_regs.vhd"
,
"conv_ttl_blo_v2.vhd"
]
...
...
hdl/vme64x_i2c/top/conv_ttl_blo_v2.ucf
View file @
1d4b172e
...
...
@@ -59,30 +59,30 @@ NET "LED_WR_OWNADDR_I2C" IOSTANDARD = LVTTL;
##-------------------
##-- Front channel LEDs
##-------------------
#
NET "PULSE_FRONT_LED_N[1]" LOC = H5;
#
NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = LVCMOS33;
#
NET "PULSE_FRONT_LED_N[1]" DRIVE = 4;
#
NET "PULSE_FRONT_LED_N[1]" SLEW = QUIETIO;
#
NET "PULSE_FRONT_LED_N[2]" LOC = J6;
#
NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = LVCMOS33;
#
NET "PULSE_FRONT_LED_N[2]" DRIVE = 4;
#
NET "PULSE_FRONT_LED_N[2]" SLEW = QUIETIO;
#
NET "PULSE_FRONT_LED_N[3]" LOC = K6;
#
NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = LVCMOS33;
#
NET "PULSE_FRONT_LED_N[3]" DRIVE = 4;
#
NET "PULSE_FRONT_LED_N[3]" SLEW = QUIETIO;
#
NET "PULSE_FRONT_LED_N[4]" LOC = K5;
#
NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = LVCMOS33;
#
NET "PULSE_FRONT_LED_N[4]" DRIVE = 4;
#
NET "PULSE_FRONT_LED_N[4]" SLEW = QUIETIO;
#
NET "PULSE_FRONT_LED_N[5]" LOC = M7;
#
NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = LVCMOS33;
#
NET "PULSE_FRONT_LED_N[5]" DRIVE = 4;
#
NET "PULSE_FRONT_LED_N[5]" SLEW = QUIETIO;
#
NET "PULSE_FRONT_LED_N[6]" LOC = M6;
#
NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = LVCMOS33;
#
NET "PULSE_FRONT_LED_N[6]" DRIVE = 4;
#
NET "PULSE_FRONT_LED_N[6]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[1]" LOC = H5;
NET "PULSE_FRONT_LED_N[1]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[1]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[1]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[2]" LOC = J6;
NET "PULSE_FRONT_LED_N[2]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[2]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[2]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[3]" LOC = K6;
NET "PULSE_FRONT_LED_N[3]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[3]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[3]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[4]" LOC = K5;
NET "PULSE_FRONT_LED_N[4]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[4]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[4]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[5]" LOC = M7;
NET "PULSE_FRONT_LED_N[5]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[5]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[5]" SLEW = QUIETIO;
NET "PULSE_FRONT_LED_N[6]" LOC = M6;
NET "PULSE_FRONT_LED_N[6]" IOSTANDARD = LVCMOS33;
NET "PULSE_FRONT_LED_N[6]" DRIVE = 4;
NET "PULSE_FRONT_LED_N[6]" SLEW = QUIETIO;
##-------------------
##-- Rear LEDs
...
...
hdl/vme64x_i2c/top/conv_ttl_blo_v2.vhd
View file @
1d4b172e
...
...
@@ -64,7 +64,7 @@ entity conv_ttl_blo_v2 is
LED_WR_OWNADDR_I2C
:
out
std_logic
;
-- I/Os for pulses
--
PULSE_FRONT_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
PULSE_FRONT_LED_N
:
out
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- PULSE_REAR_LED_N : out std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_INPUT_TTL_N : in std_logic_vector(g_nr_ttl_chan downto 1);
-- FPGA_OUT_TTL : out std_logic_vector(g_nr_ttl_chan downto 1);
...
...
@@ -131,6 +131,7 @@ architecture behav of conv_ttl_blo_v2 is
-----------------------------------------
-- base address definitions
constant
c_addr_test_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_i2c_bridge
:
t_wishbone_address
:
=
X"00000040"
;
constant
c_addr_multiboot
:
t_wishbone_address
:
=
X"00000080"
;
constant
c_addr_m25p32
:
t_wishbone_address
:
=
X"00000200"
;
...
...
@@ -138,23 +139,22 @@ architecture behav of conv_ttl_blo_v2 is
-- address mask definitions
-- 64 words per page: 6 + 1 bits
constant
c_mask_test_regs
:
t_wishbone_address
:
=
X"FFFFFFF0"
;
constant
c_mask_i2c_bridge
:
t_wishbone_address
:
=
X"FFFFFFC0"
;
constant
c_mask_multiboot
:
t_wishbone_address
:
=
X"FFFFFFC0"
;
constant
c_mask_m25p32
:
t_wishbone_address
:
=
X"FFFFFE00"
;
-- addresses constant for Wishbone crossbar
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-
1
downto
0
)
:
=
(
--c_addr_m25p32,
--c_addr_multiboot,
(
others
=>
c_addr_i2c_bridge
)
);
:
=
(
(
others
=>
c_addr_test_regs
)
);
-- masks constant for Wishbone crossbar
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-
1
downto
0
)
:
=
(
--c_mask_m25p32,
-- c_mask_multiboot,
(
others
=>
c_mask_i2c_bridge
)
);
:
=
(
(
others
=>
c_mask_test_regs
)
);
--============================================================================
-- Component declarations
...
...
@@ -191,35 +191,61 @@ architecture behav of conv_ttl_blo_v2 is
component
vme64x_i2c
is
port
(
-- Clock, reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- I2C lines
sda_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
-- I2C address and status
i2c_addr_i
:
in
std_logic_vector
(
6
downto
0
);
i2c_done_o
:
out
std_logic
;
-- Wishbone master signals
wb
_master_stb_o
:
out
std_logic
;
wb
_master_cyc_o
:
out
std_logic
;
wb
_master_sel_o
:
out
std_logic_vector
(
3
downto
0
);
wb
_master_we_o
:
out
std_logic
;
wb
_master_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb
_master_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb
_master_adr_o
:
out
std_logic_vector
(
31
downto
0
);
wb
_master_ack_i
:
in
std_logic
;
wb
_master_rty_i
:
in
std_logic
;
wb
_master_err_i
:
in
std_logic
-- Clock, reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- I2C lines
sda_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
-- I2C address and status
i2c_addr_i
:
in
std_logic_vector
(
6
downto
0
);
i2c_done_o
:
out
std_logic
;
-- Wishbone master signals
wb
m_stb_o
:
out
std_logic
;
wb
m_cyc_o
:
out
std_logic
;
wb
m_sel_o
:
out
std_logic_vector
(
3
downto
0
);
wb
m_we_o
:
out
std_logic
;
wb
m_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb
m_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb
m_adr_o
:
out
std_logic_vector
(
31
downto
0
);
wb
m_ack_i
:
in
std_logic
;
wb
m_rty_i
:
in
std_logic
;
wb
m_err_i
:
in
std_logic
);
end
component
vme64x_i2c
;
-- Regs to test I2C operation
component
test_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'reg0'
test_regs_r0_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'bits' in reg: 'reg1'
test_regs_r1_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'bits' in reg: 'reg2'
test_regs_r2_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'bits' in reg: 'reg3'
test_regs_r3_bits_o
:
out
std_logic_vector
(
31
downto
0
)
);
end
component
test_regs
;
--============================================================================
-- Signal declarations
...
...
@@ -266,6 +292,8 @@ architecture behav of conv_ttl_blo_v2 is
signal
i2c_done
:
std_logic
;
signal
i2c_up
:
std_logic
;
signal
i2c_addr
:
std_logic_vector
(
6
downto
0
);
signal
tr0
:
std_logic_vector
(
31
downto
0
);
begin
...
...
@@ -303,7 +331,7 @@ begin
rst
<=
not
rst_n
;
MR_N
<=
rst_n
;
--============================================================================
-- Output enable logic
--============================================================================
...
...
@@ -358,16 +386,16 @@ begin
i2c_done_o
=>
i2c_done
,
-- Wishbone master signals
wb
_master
_stb_o
=>
xbar_slave_in
(
0
)
.
stb
,
wb
_master
_cyc_o
=>
xbar_slave_in
(
0
)
.
cyc
,
wb
_master
_sel_o
=>
xbar_slave_in
(
0
)
.
sel
,
wb
_master
_we_o
=>
xbar_slave_in
(
0
)
.
we
,
wb
_master
_dat_i
=>
xbar_slave_out
(
0
)
.
dat
,
wb
_master
_dat_o
=>
xbar_slave_in
(
0
)
.
dat
,
wb
_master
_adr_o
=>
xbar_slave_in
(
0
)
.
adr
,
wb
_master
_ack_i
=>
xbar_slave_out
(
0
)
.
ack
,
wb
_master
_rty_i
=>
xbar_slave_out
(
0
)
.
rty
,
wb
_master
_err_i
=>
xbar_slave_out
(
0
)
.
err
wb
m
_stb_o
=>
xbar_slave_in
(
0
)
.
stb
,
wb
m
_cyc_o
=>
xbar_slave_in
(
0
)
.
cyc
,
wb
m
_sel_o
=>
xbar_slave_in
(
0
)
.
sel
,
wb
m
_we_o
=>
xbar_slave_in
(
0
)
.
we
,
wb
m
_dat_i
=>
xbar_slave_out
(
0
)
.
dat
,
wb
m
_dat_o
=>
xbar_slave_in
(
0
)
.
dat
,
wb
m
_adr_o
=>
xbar_slave_in
(
0
)
.
adr
,
wb
m
_ack_i
=>
xbar_slave_out
(
0
)
.
ack
,
wb
m
_rty_i
=>
xbar_slave_out
(
0
)
.
rty
,
wb
m
_err_i
=>
xbar_slave_out
(
0
)
.
err
);
-- Process to set the I2C_UP signal for display on the front panel
...
...
@@ -385,11 +413,41 @@ begin
end
if
;
end
process
p_i2c_up
;
--============================================================================
-- Output enable logic
--============================================================================
-- Regs to test I2C operation
cmp_test_regs
:
test_regs
port
map
(
rst_n_i
=>
rst_n
,
clk_sys_i
=>
clk_125
,
wb_adr_i
=>
xbar_master_out
(
0
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
xbar_master_out
(
0
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
0
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
0
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
0
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
0
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
0
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
0
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
0
)
.
stall
,
-- Port for std_logic_vector field: 'bits' in reg: 'reg0'
test_regs_r0_bits_o
=>
tr0
,
-- Port for std_logic_vector field: 'bits' in reg: 'reg1'
test_regs_r1_bits_o
=>
open
,
-- Port for std_logic_vector field: 'bits' in reg: 'reg2'
test_regs_r2_bits_o
=>
open
,
-- Port for std_logic_vector field: 'bits' in reg: 'reg3'
test_regs_r3_bits_o
=>
open
);
PULSE_FRONT_LED_N
<=
not
tr0
(
5
downto
0
);
--============================================================================
-- Instantiation and connection of a Wishbone crossbar module
--============================================================================
xbar_master_in
(
0
)
.
stall
<=
'0'
;
xbar_master_in
(
0
)
.
int
<=
'0'
;
-- xbar_master_in(0).stall <= '0';
xbar_master_in
(
0
)
.
int
<=
'0'
;
xbar_master_in
(
0
)
.
err
<=
'0'
;
cmp_wb_crossbar
:
xwb_crossbar
generic
map
...
...
hdl/vme64x_i2c/top/test_regs.vhd
0 → 100644
View file @
1d4b172e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Test regs for I2C state mach
---------------------------------------------------------------------------------------
-- File : test_regs.vhd
-- Author : auto-generated by wbgen2 from test_regs.wb
-- Created : Mon Mar 18 17:12:07 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE test_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
test_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'reg0'
test_regs_r0_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'bits' in reg: 'reg1'
test_regs_r1_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'bits' in reg: 'reg2'
test_regs_r2_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'bits' in reg: 'reg3'
test_regs_r3_bits_o
:
out
std_logic_vector
(
31
downto
0
)
);
end
test_regs
;
architecture
syn
of
test_regs
is
signal
test_regs_r0_bits_int
:
std_logic_vector
(
31
downto
0
);
signal
test_regs_r1_bits_int
:
std_logic_vector
(
31
downto
0
);
signal
test_regs_r2_bits_int
:
std_logic_vector
(
31
downto
0
);
signal
test_regs_r3_bits_int
:
std_logic_vector
(
31
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
test_regs_r0_bits_int
<=
"00000000000000000000000000000000"
;
test_regs_r1_bits_int
<=
"00000000000000000000000000000000"
;
test_regs_r2_bits_int
<=
"00000000000000000000000000000000"
;
test_regs_r3_bits_int
<=
"00000000000000000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
ack_in_progress
<=
'0'
;
else
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
test_regs_r0_bits_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
test_regs_r0_bits_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
test_regs_r1_bits_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
test_regs_r1_bits_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
test_regs_r2_bits_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
test_regs_r2_bits_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11"
=>
if
(
wb_we_i
=
'1'
)
then
test_regs_r3_bits_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
test_regs_r3_bits_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- bits
test_regs_r0_bits_o
<=
test_regs_r0_bits_int
;
-- bits
test_regs_r1_bits_o
<=
test_regs_r1_bits_int
;
-- bits
test_regs_r2_bits_o
<=
test_regs_r2_bits_int
;
-- bits
test_regs_r3_bits_o
<=
test_regs_r3_bits_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
hdl/vme64x_i2c/top/test_regs.wb
0 → 100644
View file @
1d4b172e
peripheral {
name = "Test regs for I2C state mach";
description = "Wishbone interface for test registers";
hdl_entity = "test_regs";
prefix = "test_regs";
reg {
name = "reg0";
prefix = "r0";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
}
};
reg {
name = "reg1";
prefix = "r1";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
}
};
reg {
name = "reg2";
prefix = "r2";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
}
};
reg {
name = "reg3";
prefix = "r3";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
}
};
};
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