Skip to content

C
Conv TTL Blocking
Commit 1edb77ce authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

top level: pulse width now 1.2us 

- renamed vme64x_i2c to elma_i2c
- continued modifications on ug-conv-ttl-blo
parent 2b8f54e4
Hide whitespace changes
Inline Side-by-side
Showing with 524 additions and 293 deletions
doc/ug/fig/conv-sys-bd.svg
View file @ 1edb77ce
......@@ -14,7 +14,7 @@
id="svg2"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="conv-sys-bd.pdf">
sodipodi:docname="conv-sys-bd.svg">
<defs
id="defs4">
<marker
......@@ -82,8 +82,8 @@
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="1.979899"
inkscape:cx="234.94503"
inkscape:cy="214.78232"
inkscape:cx="277.60397"
inkscape:cy="229.83009"
inkscape:document-units="px"
inkscape:current-layer="g3165"
showgrid="true"
......@@ -119,7 +119,7 @@
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
......@@ -805,7 +805,7 @@
id="tspan11103"
x="432.28348"
y="81.496063"
style="font-size:16px;font-style:italic;font-weight:bold;text-align:center;text-anchor:middle">CONV-TTL-BLO[-RTM]</tspan></text>
style="font-size:16px;font-style:italic;font-weight:bold;text-align:center;text-anchor:middle">CONV-TTL-RTM[-BLO]</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
......
doc/ug/fig/pulse-def.pdf
View file @ 1edb77ce
No preview for this file type
doc/ug/fig/pulse-def.svg
View file @ 1edb77ce
......@@ -9,137 +9,362 @@
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="470.23819"
height="128.71907"
id="svg2"
version="1.1"
width="315.45255"
height="161.17813"
id="svg4178"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="pulse-def.svg">
sodipodi:docname="pulse-def.pdf">
<defs
id="defs4">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path4066"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1"
objecttolerance="10"
gridtolerance="10"
guidetolerance="10"
inkscape:pageopacity="0"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8"
inkscape:cx="291.93717"
inkscape:cy="-18.40853"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
id="namedview22"
showgrid="false"
inkscape:zoom="0.85887272"
inkscape:cx="-236.39801"
inkscape:cy="15.321723"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
inkscape:current-layer="layer1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0" />
<defs
id="defs4180">
<marker
refX="0"
refY="0"
orient="auto"
id="Arrow1Mend"
style="overflow:visible">
<path
d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
transform="matrix(-0.4,0,0,-0.4,-4,0)"
id="path4758"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
inkscape:connector-curvature="0" />
</marker>
<marker
refX="0"
refY="0"
orient="auto"
id="Arrow1Mstart"
style="overflow:visible">
<path
d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
transform="matrix(0.4,0,0,0.4,4,0)"
id="path4755"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
inkscape:connector-curvature="0" />
</marker>
</defs>
<metadata
id="metadata4183">
id="metadata7">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
transform="translate(-92.527756,-219.18502)"
id="layer1">
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-88.082677,-136.1673)">
<path
d="m 141.73228,272.83462 53.14961,0 0,-53.1496 53.14961,0 0,53.1496 124.01574,0 0,-53.1496 35.43307,0"
id="path4714"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 88.582677,237.40155 35.433073,0 17.71653,-88.58267 53.14961,0 17.71654,88.58267 159.44881,0 17.71654,-88.58267 53.14961,0 17.71653,88.58267 70.86614,0"
id="path2987"
inkscape:connector-curvature="0" />
<g
id="g3877">
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path2989"
d="m 125.7874,255.11809 0,-26.57481"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
inkscape:connector-curvature="0"
id="path3761"
d="m 122.24409,228.54328 7.08661,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text3765"
y="230.31494"
x="108.07087"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px"
y="230.31494"
x="108.07087"
id="tspan3767"
sodipodi:role="line">10%</tspan></text>
</g>
<g
id="g3871">
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 139.96063,255.11809 0,-118.70079"
id="path3759"
inkscape:connector-curvature="0" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 136.41732,157.67714 7.08661,0"
id="path3763"
inkscape:connector-curvature="0" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="122.24409"
y="159.44879"
id="text3769"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3771"
x="122.24409"
y="159.44879"
style="font-size:6px">90%</tspan></text>
</g>
<g
id="g3889">
<path
inkscape:connector-curvature="0"
id="path3857"
d="m 387.99213,157.67714 0,-21.25984"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path3861"
d="m 384.44882,157.67714 7.08661,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text3867"
y="159.44879"
x="370.2756"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px"
y="159.44879"
x="370.2756"
id="tspan3869"
sodipodi:role="line">90%</tspan></text>
</g>
<path
d="m 248.0315,226.77163 0,146.29102"
id="path4716"
style="opacity:1;fill:none;stroke:#000000;stroke-width:0.9;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:7.2,7.2;stroke-dashoffset:0"
inkscape:connector-curvature="0" />
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path3897"
d="m 210.82677,255.11809 0,-26.57481"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
d="m 198.4252,290.21932 46.06299,0"
id="path5741"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#Arrow1Mstart);marker-end:url(#Arrow1Mend)"
inkscape:connector-curvature="0" />
inkscape:connector-curvature="0"
id="path3899"
d="m 207.28346,228.54328 7.08661,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="125%"
id="text3901"
y="230.31493"
x="216.14172"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:6px"
y="230.31493"
x="216.14172"
id="tspan3903"
sodipodi:role="line">10%</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4373"
y="248.03146"
x="129.3307"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:8px"
y="248.03146"
x="129.3307"
id="tspan4375"
sodipodi:role="line">t<tspan
id="tspan4377"
style="font-size:8px;baseline-shift:sub">r</tspan></tspan></text>
<text
x="215.16249"
y="300.80869"
id="text6115"
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="200.19685"
y="248.03146"
id="text4379"
sodipodi:linespacing="125%"><tspan
x="215.16249"
y="300.80869"
id="tspan6117"
dy="0 0">1 μs</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.89999998;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:7.2, 7.2;stroke-dashoffset:0"
id="path3001"
d="m 194.88679,226.55332 0,123.33975"
sodipodi:role="line"
id="tspan4381"
x="200.19685"
y="248.03146"
style="font-size:8px">t<tspan
id="tspan4385"
style="font-size:65.00091553%;baseline-shift:sub">f</tspan></tspan></text>
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 196.65354,263.97636 1e-5,-106.29922"
id="path3907"
inkscape:connector-curvature="0" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
id="path3005"
d="m 141.73228,326.71355 53.14961,0 0,53.1496 53.14961,0 0,-53.1496 124.01574,0 0,53.1496 35.43307,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 193.11024,157.67714 7.08661,0"
id="path3909"
inkscape:connector-curvature="0" />
<text
sodipodi:linespacing="125%"
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="178.937"
y="159.44879"
id="text3911"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3913"
x="178.937"
y="159.44879"
style="font-size:6px">90%</tspan></text>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path3915"
d="m 116.92913,246.25982 7.08662,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 148.8189,246.25982 -7.08662,0"
id="path4361"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<g
id="g4363">
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 125.7874,263.97636 0,-35.43308"
id="path4365"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 122.24409,228.54328 7.08661,0"
id="path4367"
inkscape:connector-curvature="0" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="108.07087"
y="230.31494"
id="text4369"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4371"
x="108.07087"
y="230.31494"
style="font-size:6px">10%</tspan></text>
</g>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 187.79527,246.25982 7.08662,0"
id="path4393"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4395"
d="m 219.68504,246.25982 -7.08662,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<text
xml:space="preserve"
id="text3787"
y="246.47113"
x="113.42619"><tspan
id="tspan3789"
y="246.47113"
x="113.42619"
style="font-weight:bold">TTL</tspan></text>
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="161.22047"
y="262.20471"
id="text4407"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4409"
x="161.22047"
y="262.20471"
style="font-size:8px;text-align:center;text-anchor:middle">t<tspan
style="font-size:65.00091553%;text-align:center;text-anchor:middle;baseline-shift:sub"
id="tspan4413">p</tspan></tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 155.90551,260.43305 -28.34645,0"
id="path4415"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4417"
d="m 166.53543,260.43305 27.31746,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<text
sodipodi:linespacing="125%"
id="text4419"
y="143.50392"
x="263.97638"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:8px;text-align:center;text-anchor:middle"
y="143.50392"
x="263.97638"
id="tspan4421"
sodipodi:role="line">T<tspan
style="font-size:65.00091553%;baseline-shift:sub"
id="tspan4425">min</tspan></tspan></text>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4427"
d="m 251.5748,139.96061 -109.84251,0"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 274.6063,139.96061 110.58517,0"
id="path4429"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 487.20472,148.81888 70.86615,0"
id="path4431"
inkscape:connector-curvature="0" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 540.35433,237.40155 17.71654,0"
id="path4433"
inkscape:connector-curvature="0" />
<text
x="91.609787"
y="357.2045"
id="text3791"
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="552.75592"
y="194.88187"
id="text4435"
sodipodi:linespacing="125%"><tspan
style="font-weight:bold"
x="91.609787"
y="357.2045"
id="tspan3793">INV-TTL</tspan></text>
sodipodi:role="line"
id="tspan4437"
x="552.75592"
y="194.88187"
style="font-size:8px;text-align:center;text-anchor:middle">V<tspan
style="font-size:65.00091553%;baseline-shift:sub"
id="tspan4441">p</tspan></tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
d="m 552.75591,186.0236 0,-35.43307"
id="path4443"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
inkscape:connector-curvature="0"
id="path4627"
d="m 552.75591,200.19683 0,35.43307"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#TriangleOutM)"
sodipodi:nodetypes="cc" />
</g>
</svg>
doc/ug/ug-conv-ttl-blo.tex
View file @ 1edb77ce
......@@ -8,6 +8,7 @@
\usepackage{color}
\usepackage[toc,page]{appendix}
\begin{document}
......@@ -110,156 +111,16 @@ TTL output, as well as on the three blocking outputs on the RTM. Similarly, bloc
pulses arriving on a blocking input channel are regenerated in the FPGA and replicated
on both the TTL and blocking outputs of the channel.
%======================================================================================
% SEC: Getting started
%======================================================================================
\pagebreak
\section{Getting Started}
\label{sec:getting-started}
This section provides a description on testing CONV-TTL-BLO boards for basic functionality. The following steps should
be followed in order to test the board.
%The steps listed below were run on a Linux Ubuntu 12.04 unit connected to the wired Ethernet interface on the
%CERN network. The steps to follow should be similar on any Linux or Windows machine; some details
%such as ELMA crate IP or TELNET client escape characters may differ in the reader's case.
\begin{enumerate}
\item Remove the board from its ESD-protecting bag;
\item If you intend to use the board with TTL pulses, remove the foliage from the switches. Otherwise, in case only INV-TTL pulses are to arrive
on the front panel connectors, skip this step;
\begin{itemize}
\item If TTL pulses are expected on the TTL channels, set the TTL switch (see Sec.~\ref{sec:switches}) to its \textbf{ON} position;
\item Set the pulse type switch in the appropriate position: \textbf{ON} - Glitch-sensitive, no pulse jitter; \textbf{OFF} - Glitch-insensitive, pulse
jitter
\end{itemize}
\item Insert the CONV-TTL-BLO board into the VME crate and power on the crate;
\item Check that the \textit{PW} status LED is lit \textbf{\textit{green}} and the \textit{ERR} and \textit{I2C} status LEDs are lit \textbf{\textit{red}}.
The \textit{TTL} status LED should also be lit \textit{\textbf{green}} if you set the TTL switch to the \textbf{ON} position in the previous step.
\item Plug in a CONV-TTL-RTM board with a CONV-TTL-RTM-BLO piggyback into the rear part of the VME crate. The \textit{ERR} LED should now turn off.
\item Input a TTL signal into a front panel input channel, or a blocking signal into the rear panel. When a pulse arrives, the pulse is replicated on the
same channel, both on the TTL output on the front panel, and on the three blocking outputs on the rear panel. The pulse LEDs on the front and rear panels for
the channel are simultaneously lit green for ~96~ms when a pulse arrives.
\item \textbf{\textit{Optional}}: Connect to the VME crate through telnet to identify the board. An example of identifying a CONV-TTL-BLO in the first slot
of the crate \textit{cfvm-864-celma1} from a Linux command line:
\begin{verbatim}
tstana@tstana-unit:~$ telnet cfvm-864-celma1
Trying 137.138.192.90...
Connected to cfvm-864-celma1.cern.ch.
Escape character is '^]'.
login:user
password:USER
%>readreg 1 1
Read Data: 424C4F32
%>
\end{verbatim}
The \textit{I2C} status LED should light \textbf{\textit{green}} after this command is run.
\end{enumerate}
%======================================================================================
% SEC: Pulse signals
%======================================================================================
\pagebreak
\section{Pulse Signal Types}
\label{sec:pulse-def}
In order for CONV-TTL-BLO boards to work as repeaters, logic is implemented in the
on-board FPGA that reacts to a trigger at either rear or front panel and generates a
pulse at the output.
Extensive work was made by Carlos Gil-Soriano to research existing boards at CERN and
define a standard for pulse levels in repeater boards \cite{StandardBlocking}. Based on
this document and on further tests with two of the existing repeater boards at CERN, output
pulse widths and amplitudes were selected for the converter boards.
\begin{table}[h]
\caption{Trigger sources}
\label{tbl:pulse-levels}
\centerline
{
\begin{tabular}{l c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Type}} & \textbf{Pk-pk amplitude} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
TTL & 3.3~V & \\
INV-TTL & 3.3~V & Inverted version of TTL pulse \\
Blocking & 24~V & Same as TTL, but different level and rise and fall times \\
\hline
\end{tabular}
}
\end{table}
Three types of pulses are defined in the context of CONV-TTL-BLO boards. They
differ only in signal amplitude and signal rise and fall times, due to the circuitry
used to generate them; pulse widths are the same for all three types. Table~\ref{tbl:pulse-levels}
presents the different types of pulses and Fig.~\ref{fig:pulse-def} shows a graphic representation of
the pulse signal.
\begin{figure}[h]
\begin{center}
\includegraphics{fig/pulse-def}
\caption{Pulse signal shape}
\label{fig:pulse-def}
\end{center}
\end{figure}
%======================================================================================
% SEC: switches
%======================================================================================
\pagebreak
\section{On-Board Switches}
\label{sec:switches}
There are eight switches provided on-board the CONV-TTL-BLO board. Of these eight, two are
used by the current version of the FPGA firmware, as shown in Table~\ref{tbl:switches}.
\begin{table}[h]
\caption{Switches on CONV-TTL-BLO}
\label{tbl:switches}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Switch}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
SW1.1 & Selects the type of pulse generated at the output \newline
\textbf{ON} -- \textit{Type 1}, glitch-sensitive, without output jitter \newline
\textbf{OFF} -- \textit{Type 2}, glitch-filtered, with output jitter \\
SW2.4 & TTL/INV-TTL input selection switch \newline
\textbf{ON} -- TTL pulses arrive on TTL and INV-TTL inputs \newline
\textbf{OFF} -- INV-TTL pulses arrive on TTL and INV-TTL inputs \newline
\textit{Note:} This switch applies the selection to the whole board, i.e.,
only TTL or INV-TTL pulses may be input on all channels of the board, not
both \\
\hline
\end{tabular}
}
\end{table}
SW1.1 is used to select whether the pulse generated at the output should have jitter
or not. Based on application and the environment in which the boards are used, the
pulse generated can be one of two types. \textit{Type 1} pulses have no output jitter,
but can be sensitive to glitches, i.e., a glitch at the input may trigger the
generation of a pulse. \textit{Type 2} pulses are sensitive to glitches up to 40~ns
long, but there is jitter at the output.
SW2.4 is used to select the type of signal that would arrive on the TTL and INV-TTL inputs.
The switch is valid board-wide, i.e., if it is set for TTL inputs (\textbf{ON}), TTL
signals should be input on both TTL and INV-TTL inputs. Inputting INV-TTL signals on a
channel while the TTL/INV-TTL selection switch is set to TTL invalidates the operation
guaranteed by SW1.1 and introduces a delay on the generated pulse.
%======================================================================================
% SEC: Panels
%======================================================================================
\pagebreak
\section{Front and Rear Panels}
\section{Front and rear panels}
\label{sec:front-rear-panel}
Two panels exist in the context of the pulse repeater boards. The first of these is the
\textit{front panel}, which corresponds to CONV-TTL-BLO boards and offers various status
LEDs, as well as various connectors for TTL and INV-TTL (see Sec.~\ref{sec:pulse-def}) pulses
LEDs, as well as various connectors for TTL and TTL-BAR (see Sec.~\ref{sec:pulse-def}) pulses
and White Rabbit. The second is the \textit{rear panel}, located on the other side of the
VME backplane and corresponding to CONV-TTL-RTM-BLO boards. The rear panel offers blocking
pulse connectors and status LEDs for pulse arrival confirmation.
......@@ -272,7 +133,7 @@ of status LEDs and several ports, divided in four sections from top to bottom:
\item System status LEDs;
\item Small form-factor pluggable (SFP) connector;
\item TTL pulse connectors;
\item INV-TTL pulse connectors.
\item TTL-BAR pulse connectors.
\end{itemize}
\begin{figure}[!htdp]
......@@ -324,7 +185,7 @@ One side of the dual LEMO 00 (type EPY) connector on the CONV-TTL-BLO boards
are used for the TTL trigger inputs. By connecting an external trigger source to
one of these connectors, a blocking pulse is generated at the rear panel and
a TTL-level pulse is generated at the front panel. The triggers can be either
TTL, or INV-TTL level.
TTL, or TTL-BAR level.
All input channels are line-terminated with 50$\Omega$ resistors.
......@@ -342,12 +203,12 @@ TTL output lines are not internally terminated.
\subsubsection{General-purpose}
Four dedicated inverted-TTL connectors can be found in the lower part of the front panel.
The inputs can be either TTL, or INV-TTL, as selected by the TTL selection switch.
The outputs of these connectors are always INV-TTL level (see Sec.~\ref{sec:pulse-def}).
The inputs can be either TTL, or TTL-BAR, as selected by the TTL selection switch.
The outputs of these connectors are always TTL-BAR level (see Sec.~\ref{sec:pulse-def}).
INV-TTL inputs are internally terminated with 50$\Omega$ resistors.
TTL-BAR inputs are internally terminated with 50$\Omega$ resistors.
INV-TTL outputs are not internally terminated and not replicated on the blocking
TTL-BAR outputs are not internally terminated and not replicated on the blocking
outputs.
\subsection{Rear panel}
......@@ -367,11 +228,106 @@ When a pulse is repeated on the output connector of a channel, the pulse status
\end{center}
\end{figure}
%======================================================================================
% SEC: Pulse signals
%======================================================================================
\pagebreak
\section{Pulse signal types}
\label{sec:pulse-def}
In order for CONV-TTL-BLO boards to work as repeaters, logic is implemented in the
on-board FPGA that reacts to a trigger at either the rear or front panel and generates a
pulse at the output. This section presents the pulses generated by the CONV-TTL-BLO
board.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-def}}
\caption{Pulse signal characteristics}
\label{fig:pulse-def}
\end{figure}
The different characteristics of a pulse are defined in Fig.~\ref{fig:pulse-def}.
Three pulse types may exist, depending on signal amplitude, rise and fall times; pulse
widths and frequencies are the same. TTL and TTL-BAR pulses are input and output on the
front panel of the boards. TTL-BAR is essentially an inverted version of TTL signals.
Blocking pulses \cite{StandardBlocking} are input and output on the rear panel
(via a CONV-TTL-RTM). The characteristics of the three types of pulses are shown in
Table~\ref{tbl:pulse-def}.
\begin{table}[h]
\caption{Pulse characteristics by type}
\label{tbl:pulse-def}
\centerline
{
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{TTL} & \textbf{Blocking} & \textbf{Unit} \\
\hline
V$_p$ & Pulse amplitude,
$V_{p,max} - V_{p,min}$ & 3.3 & 24 & V \\
V$_{p,max}$ & Pulse max. amplitude & 3.3 & 24 & V \\
V$_{p,min}$ & Pulse max. amplitude & 0 & 0 & V \\
t$_p$ & Pulse width & 1.2 & 1.2 & $\mu$s \\
T$_{min}$ & Min. period of pulse signal & 3.33 & 3.33 & $\mu$s \\
t$_r$ & Rise time & 6.4 & 140 & ns \\
t$_f$ & Fall time & 3 & 160 & ns \\
\hline
\end{tabular}
}
\end{table}
%======================================================================================
% SEC: switches
%======================================================================================
\pagebreak
\section{On-board switches}
\label{sec:switches}
There are eight switches provided on-board the CONV-TTL-BLO board. Of these eight, two are
used by the current version of the FPGA firmware, as shown in Table~\ref{tbl:switches}.
\begin{table}[h]
\caption{Switches on CONV-TTL-BLO}
\label{tbl:switches}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Switch}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
SW1.1 & Selects the type of pulse generated at the output \newline
\textbf{ON} -- \textit{Type 1}, glitch-sensitive, without output jitter \newline
\textbf{OFF} -- \textit{Type 2}, glitch-filtered, with output jitter \\
SW2.4 & TTL/TTL-BAR input selection switch \newline
\textbf{ON} -- TTL pulses arrive on TTL and TTL-BAR inputs \newline
\textbf{OFF} -- TTL-BAR pulses arrive on TTL and TTL-BAR inputs \newline
\textit{Note:} This switch applies the selection to the whole board, i.e.,
only TTL or TTL-BAR pulses may be input on all channels of the board, not
both \\
\hline
\end{tabular}
}
\end{table}
SW1.1 is used to select whether the pulse generated at the output should have jitter
or not. Based on application and the environment in which the boards are used, the
pulse generated can be one of two types. \textit{Type 1} pulses have no output jitter,
but can be sensitive to glitches, i.e., a glitch at the input may trigger the
generation of a pulse. \textit{Type 2} pulses are sensitive to glitches up to 40~ns
long, but there is jitter at the output.
SW2.4 is used to select the type of signal that would arrive on the TTL and TTL-BAR inputs.
The switch is valid board-wide, i.e., if it is set for TTL inputs (\textbf{ON}), TTL
signals should be input on both TTL and TTL-BAR inputs. Inputting TTL-BAR signals on a
channel while the TTL/TTL-BAR selection switch is set to TTL invalidates the operation
guaranteed by SW1.1 and introduces a delay on the generated pulse.
%======================================================================================
% SEC: Communicating to the CONV-TTL-BLO
%======================================================================================
\pagebreak
\section{Communicating to the CONV-TTL-BLO}
\section{Communicating with the CONV-TTL-BLO}
\label{sec:comm}
It is possible to communicate to the CONV-TTL-BLO remotely via the VME P1 I$^2$C interface.
......@@ -448,15 +404,15 @@ on-board addresses is:
\end{center}
An example of retrieving the CONV-TTL-BLO ID from \textit{reg} 1 of a CONV-TTL-BLO plugged into VME
slot 1 of the crate \textit{cfvm-864-celma1} is given below:
slot 1 of the crate \textit{some-crate} is given below:
\begin{verbatim}
tstana@tstana-unit:~$ telnet cfvm-864-celma1
tstana@tstana-unit:~$ telnet some-crate
Trying 137.138.192.90...
Connected to cfvm-864-celma1.cern.ch.
Connected to some-crate.cern.ch.
Escape character is '^]'.
login:user
password:USER
password:****
%>readreg 1 1
Read Data: 424C4F32
%>
......@@ -471,16 +427,64 @@ below. As expected, when the board is removed, it can no longer acknowledge the
message:
\begin{verbatim}
Connected to cfvm-864-celma1.cern.ch.
Connected to some-crate.cern.ch.
Escape character is '^]'.
login:user
password:USER
password:****
%>readreg 1 1
Not Acknoledged!
%>
\end{verbatim}
%======================================================================================
% Appendix: Getting started
%======================================================================================
\pagebreak
\begin{appendices}
\section{Getting started with the CONV-TTL-BLO}
\label{sec:app-get-started}
This section provides a description on testing CONV-TTL-BLO boards for basic functionality. The following steps should
be followed in order to test the board.
%The steps listed below were run on a Linux Ubuntu 12.04 unit connected to the wired Ethernet interface on the
%CERN network. The steps to follow should be similar on any Linux or Windows machine; some details
%such as ELMA crate IP or TELNET client escape characters may differ in the reader's case.
\begin{enumerate}
\item (\textbf{Optional}) Plug in a CONV-TTL-RTM board with a CONV-TTL-RTM-BLO
piggyback into the rear part of the VME crate.
\item Remove the CONV-TTL-BLO board from its ESD-protecting bag;
\item If TTL or TTL-BAR pulses are to arrive on the front panel inputs, set the
TTL switch to the appropriate position
\begin{itemize}
\item TTL pulses -- set the switch to the \textbf{\textit{ON}} position
\item TTL-BAR pulses -- set the switch to the \textbf{\textit{OFF}} position (default)
\end{itemize}
\item Insert the CONV-TTL-BLO board into the VME crate and power on the crate;
\item Check that the \textit{\textbf{PW}} status LED is lit \textbf{\textit{green}}. If there is
no RTM in the rear side of the crate, the \textit{\textbf{ERR}} LED will light \textbf{\textit{red}}.
The \textit{\textbf{TTL}} status LED should also be lit \textit{\textbf{green}} if you set the TTL
switch to the \textbf{ON} position in the previous step.
\item Input a TTL (or TTL-BAR) signal into a front panel input channel. When a pulse arrives on the input,
it is replicated on the output of the same channel. If an RTM board is present in the rear
part of the VME crate, the pulse will also be replicated on the three blocking outputs of the
same channel on the rear-panel. The channel pulse LED on both the front and rear panels flash
briefly when a pulse arrives.
\item (\textbf{Optional}) Input a blocking signal on a rear panel channel;
The pulse LED of the channel will flash and the pulse will be replicated
on the three blocking outputs of the same channel, as well as the TTL channel output on
the front panel. If the TTL switch is \textbf{OFF}, the pulse is replicated in TTL-BAR.
\end{enumerate}
\end{appendices}
%\begin{table}[h]
%\caption{Pulse signal characteristics}
%\label{tbl:pulse-def}
......@@ -517,33 +521,33 @@ password:USER
%
%\textcolor{red}{\textbf{board picture}}
%
%\subsubsection{TTL and INV-TTL inputs}
%\subsubsection{TTL and TTL-BAR inputs}
%\label{sec:ttl-inp}
%
%TTL and INV-TTL level pulses arrive through the LEMO connectors. The pulses are passed
%TTL and TTL-BAR level pulses arrive through the LEMO connectors. The pulses are passed
%through a Schmitt trigger buffer circuit to smooth out transitions and then passed to the FPGA.
%The buffer circuit is shown in Fig.~\ref{fig:ttl-inp} and is common to the six TTL input channels
%and the four INV-TTL input channels.
%and the four TTL-BAR input channels.
%
%\begin{figure}[h]
%\begin{center}
% \includegraphics[width=.85\textwidth]{fig/ttl-inp.png}
% \caption{TTL and INV-TTL input circuit}
% \caption{TTL and TTL-BAR input circuit}
% \label{fig:ttl-inp}
%\end{center}
%\end{figure}
%
%Since a signal at the input can be both TTL and INV-TTL, a switch (called the \textit{LEVEL} switch)
%Since a signal at the input can be both TTL and TTL-BAR, a switch (called the \textit{LEVEL} switch)
%is provided on the board to select between the two. The switch (shown in Fig.~\ref{fig:level-switch})
%is checked in the FPGA logic and the output pulse per each channel is adjusted according to its status.
%
%As can be seen in Fig.~\ref{fig:level-switch}, when the switch is in the upper position, it indicates
%that the signal on TTL and INV-TTL inputs is TTL level. When the switch is in the lower position,
%this indicates an INV-TTL level at TTL and INV-TTL inputs.
%that the signal on TTL and TTL-BAR inputs is TTL level. When the switch is in the lower position,
%this indicates an TTL-BAR level at TTL and TTL-BAR inputs.
%
%\textcolor{red}{\textbf{LEVEL switch pic}}
%
%A board can only have TTL \textit{or} INV-TTL inputs at one time on \textit{any} channel, not both.
%A board can only have TTL \textit{or} TTL-BAR inputs at one time on \textit{any} channel, not both.
%The LEVEL switch indicates which of the two it is. Since there is only one LEVEL switch on CONV-TTL-BLO
%boards, it is not possible to set the type of signal per each channel.
%
......@@ -622,7 +626,7 @@ password:USER
%on board.
%
%Finally, the \textit{pulse\_generator} modules generate predefined-width pulses to be transmitted on the
%blocking, TTL and INV-TTL channels. The same \textit{pulse\_generator} module with a different pulse width
%blocking, TTL and TTL-BAR channels. The same \textit{pulse\_generator} module with a different pulse width
%is used to light the pulse arrival LEDs on front an rear panels.
%
%\subsection{Reset generation}
......@@ -752,7 +756,7 @@ password:USER
%
%Multiple \textit{pulse\_generator} modules are instantiated in the design and used to generate pulse signals. Six of these
%are configured to output 1~$\mu$s pulses on both TTL and blocking outputs based on a trigger signal which is the \textit{OR}
%of TTL and blocking level input pulses. Four are configured to output 1~$\mu$s pulses based on a trigger from the INV-TTL channels.
%of TTL and blocking level input pulses. Four are configured to output 1~$\mu$s pulses based on a trigger from the TTL-BAR channels.
%Finally, six \textit{pulse\_generator} modules are configured to output 96~ms pulses to light the pulse status LEDs corresponding to the six
%blocking and TTL channels; they are sensitive to the same trigger input as the TTL and blocking pulse generators.
%
......
hdl/vme64x_i2c/rtl/Manifest.py → hdl/elma_i2c/rtl/Manifest.py
View file @ 1edb77ce
files = [
"i2c_slave_pkg.vhd",
"i2c_slave.vhd",
"vme64x_i2c.vhd"
"elma_i2c.vhd"
]
modules = {
......
hdl/vme64x_i2c/rtl/vme64x_i2c.vhd → hdl/elma_i2c/rtl/elma_i2c.vhd
View file @ 1edb77ce
......@@ -58,7 +58,7 @@ use ieee.numeric_std.all;
use work.i2c_slave_pkg.all;
entity vme64x_i2c is
entity elma_i2c is
port
(
-- Clock, reset
......@@ -90,9 +90,9 @@ entity vme64x_i2c is
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end entity vme64x_i2c;
end entity elma_i2c;
architecture behav of vme64x_i2c is
architecture behav of elma_i2c is
--============================================================================
-- Type declarations
......
hdl/release/syn/Makefile
View file @ 1edb77ce
......@@ -42,9 +42,9 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../vme64x_i2c/rtl/i2c_slave_pkg.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \
../../vme64x_i2c/rtl/vme64x_i2c.vhd \
../../elma_i2c/rtl/i2c_slave_pkg.vhd \
../../elma_i2c/rtl/i2c_slave.vhd \
../../elma_i2c/rtl/elma_i2c.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 1edb77ce
......@@ -72,34 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529270" xil_pn:in_ck="1402893700349391657" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1370529254">
<transform xil_pn:end_ts="1370609208" xil_pn:in_ck="-4867058225791759267" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -117,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1370529270" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1370529270">
<transform xil_pn:end_ts="1370609208" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1370609208">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1370529279" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1370529270">
<transform xil_pn:end_ts="1370609217" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1370609208">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -130,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1370529315" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1370529279">
<transform xil_pn:end_ts="1370609256" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1370609217">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -143,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1370529353" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1370529315">
<transform xil_pn:end_ts="1370609294" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1370609256">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -157,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1370529375" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1370529353">
<transform xil_pn:end_ts="1370609316" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1370609294">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1370529353" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1370529342">
<transform xil_pn:end_ts="1370609294" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1370609283">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 1edb77ce
......@@ -350,7 +350,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../rtl/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
......@@ -359,19 +359,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../elma_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<file xil_pn:name="../../elma_i2c/rtl/elma_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
......@@ -644,7 +644,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
</files>
......
hdl/release/top/Manifest.py
View file @ 1edb77ce
......@@ -7,7 +7,7 @@ modules = {
"local" : [
"../../reset_gen",
"../rtl",
"../../vme64x_i2c",
"../../elma_i2c",
"../../ctb_pulse_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
......
hdl/release/top/conv_ttl_blo_v2.ucf
View file @ 1edb77ce
......@@ -62,7 +62,8 @@ NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16;
# TIMESPEC TS_clk_i = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 1edb77ce
......@@ -230,7 +230,7 @@ architecture behav of conv_ttl_blo_v2 is
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vme64x_i2c is
component elma_i2c is
port
(
-- Clock, reset
......@@ -262,7 +262,7 @@ architecture behav of conv_ttl_blo_v2 is
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vme64x_i2c;
end component elma_i2c;
component conv_regs is
port (
......@@ -387,7 +387,7 @@ begin
--============================================================================
i2c_addr <= "10" & fpga_ga_i;
cmp_i2c_bridge : vme64x_i2c
cmp_i2c_bridge : elma_i2c
port map
(
-- Clock, reset
......@@ -563,7 +563,7 @@ begin
cmp_ttl_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 125,
g_pulse_width => 150,
g_glitch_filt_len => 4
)
port map
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment