additions to pres-2.txt

207696ab · Theodor-Adrian Stana · fa27d8d6 · 207696ab
Commit 207696ab authored Nov 15, 2013 by Theodor-Adrian Stana
Hide whitespace changes
Inline Side-by-side

Showing with 1 addition and 1 deletion

pres-2.txt design-review/pres-2.txt +1 -1

No files found.
--- a/design-review/pres-2.txt
+++ b/design-review/pres-2.txt
@@ -40,9 +40,9 @@ conv-ttl-blo/
 1.3. i2c_slave & glitch_filt
 - add synchronizer to glitch_filt
 - SCL line sampling
-- nothing in I2C spec saying 'sample on rising edge'
 -- (tom, eva) sampled on falling edge to avoid incompliant masters
 -- (javier) tapped delay line makes design too complex
+-- will change to rising edge sampling
 - (tom) will change sda_o and sda_en_o assignment
 - (eva) agreed with clearer `falling' and `rising' signal naming
 - (eva) FSM seems clearer if the outputs are set in same process as