Commit 222e55cc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Basic functionality with immunity to no input channel while in INV-TTL mode and…

Basic functionality with immunity to no input channel while in INV-TTL mode and documentation update.
parent 224a9757
ug/
old-ug-conv-ttl-blo.pdf
userGuide.pdf
@misc{StandardBlocking,
author= "C. Gil Soriano",
title= {{Standard Blocking Output Signal Definition for CTDAH board}},
month= sep,
year= 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
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\@writefile{toc}{\contentsline {paragraph}{Acknowledgements}{ii}{section*.1}}
\@writefile{toc}{\contentsline {paragraph}{System Description and Purpose}{ii}{section*.2}}
\@writefile{toc}{\contentsline {section}{\numberline {1}General schema}{1}{section.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}CERN Repetitors needs}{1}{subsection.1.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Front and Rear boards}{1}{subsection.1.2}}
\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces Functional block schema}}{2}{figure.1}}
\@writefile{toc}{\contentsline {section}{\numberline {2}Panels}{3}{section.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.1}Front Panel: CONT-TTL-BLO}{3}{subsection.2.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.2}Rear Panel: CONV-TTL-RTM-BLO}{3}{subsection.2.2}}
\@writefile{toc}{\contentsline {section}{\numberline {3}Power-up and System Monitoring}{4}{section.3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.1}Power Supplies}{4}{subsection.3.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.2}Board Temperature}{4}{subsection.3.2}}
\citation{StandardBlocking}
\@writefile{toc}{\contentsline {section}{\numberline {4}FPGA Control and Pulse Converter Unit}{5}{section.4}}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Board ID}{5}{subsection.4.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.2}HDL control}{5}{subsection.4.2}}
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\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.1}Input}{6}{subsubsection.4.3.1}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.2}Output}{6}{subsubsection.4.3.2}}
\@writefile{toc}{\contentsline {section}{\numberline {5}On board memory and FPGA reprogramming}{7}{section.5}}
\@writefile{toc}{\contentsline {section}{\numberline {6}Testing methodologies}{8}{section.6}}
\bibstyle{unsrt}
\bibdata{Functional}
\bibcite{StandardBlocking}{1}
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\citation{HeinzeReport}
\@writefile{toc}{\contentsline {section}{\numberline {1}Boards and compatibility}{1}{section.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Repetitors and Blocking Generators}{1}{subsection.1.1}}
\citation{HeinzeLAPF}
\citation{ClaudeDoc}
\citation{CTDACSchematics}
\citation{2222AFairchild}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Receivers}{2}{subsection.1.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}Uses of boards}{2}{subsection.1.3}}
\@writefile{toc}{\contentsline {section}{\numberline {2}Standard Blocking Output Signal Definition}{3}{section.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.1}Criteria}{3}{subsection.2.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.2}Target use}{3}{subsection.2.2}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.2.1}Repetitor Boards}{3}{subsubsection.2.2.1}}
\bibstyle{unsrt}
\bibdata{BlockingSpecification.bib}
\bibcite{HeinzeReport}{1}
\bibcite{HeinzeLAPF}{2}
\bibcite{ClaudeDoc}{3}
\bibcite{CTDACSchematics}{4}
\bibcite{2222AFairchild}{5}
@misc{HeinzeReport,
author= "W. Heinze",
title= {{Adapting TTL to Blocking Level with 3U Cards}},
month= nov,
year= 1994,
howpublished = "CERN, PS-CO, Note 94-83",
note = "{\url{https://edms.cern.ch/file/817779/1/TTL_BLO_cards.pdf}}"
}
@misc{HeinzeLAPF,
title= {{LAPF: A TTL to Blocking Converter in Euroformat with Pulse Former}},
howpublished= "CERN, PS-CO",
author= "W. Heinze",
month= mar,
year= 1993,
note = "{\url{https://edms.cern.ch/file/817773/1/LAPF_TTL_BLO_Note.pdf}}"
}
@UNPUBLISHED{ClaudeDoc,
title= {{Distributeur de Timing en Chasis Europe Notice Descriptive}},
note= "CERN, PS-CO-WP, Note 87-028",
author= "C. Dehavay",
month= feb,
year= 1987
}
@misc{CTDACSchematics,
title= {{CTDAC schematics}},
howpublished= "CERN, TS-DEM",
author= "P. Nouchi",
month= may,
year= 2007,
note = "{\url{https://edms.cern.ch/file/842138/1/EDA-01632-V1-0_sch.pdf}}"
}
@misc{2222AFairchild,
title= {{2222A Fairchild Semiconductors Datasheet}},
author= "Fairchild Semiconductors",
month= aug,
year= 2010,
note = "{\url{www.fairchildsemi.com/ds/PN/PN2222A.pdf}}"
}
%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{colortbl}
\begin{document}
\title{\textbf{{\LARGE Standard Blocking Output Signal Definition for CTDAH board}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{February 23, 2012}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
The aim of this document is defining the Standard Blocking Output Signal of the Pulse
Converter Unit. This shape is compatible with previous versions, depending
upon its use.\\
\textbf{History of changes}\\
This document version has been checked by:\\
This document version has been approved by:\\
\begin{center}
\begin{tabular}{|p{3cm}|p{1.5cm}|p{5cm}|}
\hline
\textbf{Date} & \textbf{Pages} & \textbf{Changes}\\
\hline
\hline
September 19, 2011& All & Initial submission\\
\hline
September 21, 2011& All& Scope reduced to Standard Blocking Output Signal
definition\\
\hline
\end{tabular}
\end{center}
\end{abstract}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{2}
\pagestyle{empty}
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\pagenumbering{arabic}
\pagestyle{plain}
\setcounter{page}{1}
\section{Boards and compatibility}
\subsection{Repetitors and Blocking Generators}
Five Pulse Conversion boards outputting the so-called ''Blocking'' pulse
are known to be working at CERN. Three of them were reported and studied by W.
Heinze \cite{HeinzeReport}:
\begin{itemize}
\item \textbf{Level Converter -LA boards-}\\
Due to the VAC transformer ZKB 407/115, the output level is 35 V or 18 V
depending on the applied voltage to the A30 pin in the 96 pin DIN connector
--either 24 V for the 35 V output or 12 V for the 18 V one. The length of the
pulse is 1 $\mu{}s$.
\item \textbf{LAPF-TTL-BLO}\\
This board was used to provide 4 $\mu{}s$ pulses to SAC and LAF boards. For
these boards, a longer pulse width is required due to the input low pass
filter applied in SAC and LAF boards to avoid LINAC noisy environment. It uses
the same transformer as Level Converter and the output level is reported to be the same.
\item \textbf{LASB-TTL-BLO}\\
It uses a VAC 409/27 transformer. It outputs a pulse with a high level of
either 23V or 11V depending upon the voltage supplied to the A30 pin in the 96
pin DIN connector --24 V or 12 V, respectivelly.
\end{itemize}
Apart from these three boards, two more are
actually running in CERN facilities: an 8 Channel Repeater and a 16 channel one.
Both Channel Repeater boards use the same subcircuit in every channel to
output the signal. The main differences between them lie in the power supply
they use and the daisy-chain connector included in the 8 channel version. Thanks
to the daisy-channel two boards can copy the same input by means of a short
interconnecting cable.\\
The output level is 24V for the 8 Channel Repeater and
30V for the 16 channel version. This is due to the use of different power
supplies because of different stocks when they were made. The length of the
pulses ranges from 1.2 $\mu{}s$ to 1.4 $\mu{}s$.
The table below summarizes the information of the repetitors systems:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Board} & \textbf{Input Level} & \multicolumn{2}{|c|}{\textbf{Output
Signal}}\\
\hline
&&Level&Pulse width\\
\hline
& TTL & & \\
8 Channel Repeater & inverted-TTL & 24V & [1.2 $\mu${}$s$,
1.4 $\mu${}$s$]\\ & 10V to 30V & & \\
\hline
\hline
& TTL &&\\
16 Channel Repeater & inverted-TTL & 30V & [1.2 $\mu{}s$, 1.4
$\mu{}s$]\\ & 10V to 30V& & \\
\hline
\hline
LASB -TTL-BLO & TTL & 11V or 23V & 1.5 $\mu{}s$\\
& inverted-TTL & & \\
\hline
\hline
LAPF-TTL-BLO & TTL & 18V or 35V&4 $\mu{}s$\\
& inverted-TTL & &\\
\hline
\hline
Level Adapter & TTL & 18V or 35V & 1$\mu{}s$\\
& inverted-TTL & &\\
\hline
\end{tabular}
\end{center}
None of the boards specify the design value of the rise time. Only the trailing
edge is reported for LAPF when the circuit is unloaded \cite{HeinzeLAPF}: 0.3
$ms$. Measurements on both 8 and 16 Channel Repeater show a worst-case rise time
of 100 $\mu{}s$ and a fall time of 400 $\mu{}s$ when the outputs are loaded with
50 $\Omega$.
\subsection{Receivers}
Three boards are reported to be Blocking pulse receivers in CERN facilities:
\begin{itemize}
\item \textbf{LA-BLO-TTL, LAF-BLO-TTL, CTDAC}\\
By reading the schematics \cite{ClaudeDoc} \cite{CTDACSchematics}, an input
threshold detection around 4.5 V can be inferred from the input net consisting of the 10
$K\Omega$, 1.5 $K\Omega$ and the 2N2222A NPN switching transistor --$V_{BE}$
should be around 0.6 V by \cite{2222AFairchild}.\\It is not documented the
reason why this input value threshold is set.
\end{itemize}
\subsection{Uses of boards}
The boards are used as:
\begin{itemize}
\item \textbf{Repetitors}
The 8 and 16 Channel Repeaters, LASB and Level Adapter are used as repetitors.
\item \textbf{Control signal}
LAPF is intended to interface VME SAC/LAF boards.
\end{itemize}
\pagebreak
\section{Standard Blocking Output Signal Definition}
As it was shown in the previous section, a wide variety of output shapes are
running together. One common type of output shape will be defined to set a
reference for the design of the new CTDAH board.\\
\subsection{Criteria}
The criteria employed to define the output shape is as follows:
\begin{center}
\textit{A board designed for a specific use should be backwards compatible with
existing boards so as to avoid interoperability failure.}
\end{center}
\subsection{Target use}
\begin{center}
\textit{Standard Blocking signals are intended to be used in repetitors.}
\end{center}
\begin{tabular}{p{12cm}}
\rowcolor{yellow}{ \textbf{NOTE}: Due to the fact that just a few boards -5
or less- need a LAPF-TTL-BLO-like shaped pulse, the Standard Blocking signal is
not compatible with wide pulses from LAPF-TTL-BLO boards.}
\end{tabular}
\subsubsection{Repetitor Boards}
To comply with previous designs, the definition for this kind of boards,
\textbf{loaded with 50 $\Omega{}$}, is as follows:
\begin{center}
\begin{tabular}{|c|c|c|}
\hline
\textbf{Parameter} & \textbf{Name} &\textbf{Value} \\
\hline
\hline
$v_{i,H}$ & High level & 24V $\pm$ 1V\\
\hline
\hline
$t_{P_{min}}$&\textit{Minimum pulse width} & 1 $\mu{}s$\\
\hline
$t_{P}$&\textit{Typical pulse width} & 1.2 $\mu{}s$\\
\hline
$t_{P_{max}}$&\textit{Maximum pulse width} & 2 $\mu{}s$\\
\hline
\hline
$t_{r}$&\textit{Rise time} & 150 $ns$ $\pm$ 75 $ns$\\
\hline
\hline
$t_{f}$&\textit{Fall time} & 150 $ns$ $\pm$ 75 $ns$\\
\hline
\end{tabular}
\end{center}
\pagebreak
\bibliographystyle{unsrt}
\bibliography{BlockingSpecification.bib}
\end{document}
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\citation{StandardBlocking}
\@writefile{toc}{\contentsline {paragraph}{System Description and Purpose}{ii}{section*.1}}
\citation{StantonBook}
\citation{MillmanBook}
\citation{LinvillBook}
\citation{LinvillIREPaper}
\citation{McDonaldIEEEPaper}
\citation{NormanIEEPaper}
\citation{LinvillIREPaper}
\citation{LinvillIREPaper}
\@writefile{toc}{\contentsline {section}{\numberline {1}Triggered Monostable Blocking Oscillator}{1}{section.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}References and tips}{1}{subsection.1.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Topologies evaluated}{1}{subsection.1.2}}
\citation{NormanIEEPaper}
\citation{MillmanBook}
\citation{NormanIEEPaper}
\citation{LinvillBook}
\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces Linvill's circuit, taken from \cite {LinvillIREPaper}}}{2}{figure.1}}
\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces Norman's circuit, taken from \cite {NormanIEEPaper}}}{2}{figure.2}}
\@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces Millman's circuit, taken from \cite {MillmanBook}}}{3}{figure.3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}Analysis of the chosen topology}{3}{subsection.1.3}}
\@writefile{lof}{\contentsline {figure}{\numberline {4}{\ignorespaces States and equivalent circuits}}{3}{figure.4}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.3.1}Switching on}{3}{subsubsection.1.3.1}}
\@writefile{lof}{\contentsline {figure}{\numberline {5}{\ignorespaces Eq. circuit B: switching}}{4}{figure.5}}
\citation{NormanIEEPaper}
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\citation{NormanIEEPaper}
\@writefile{lof}{\contentsline {figure}{\numberline {6}{\ignorespaces Eq. circuit A: on-state}}{6}{figure.6}}
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\bibstyle{unsrt}
\bibdata{BlockingGuidelines}
\bibcite{StandardBlocking}{1}
\bibcite{StantonBook}{2}
\bibcite{MillmanBook}{3}
\bibcite{LinvillBook}{4}
\bibcite{LinvillIREPaper}{5}
\bibcite{McDonaldIEEEPaper}{6}
\bibcite{NormanIEEPaper}{7}
@ARTICLE{IEEEStandard,
journal={ANSI/IEEE Std 390-1987},
title={{IEEE} Standard for Pulse Transformers},
year={1987},
keywords={IEEE standards;bipolar pulses;blocking oscillators;coupling devices;electronic circuits;positive feedback;pulse transformers;unipolar pulses;equivalent circuits;pulse transformers;standards;testing;},
doi={10.1109/IEEESTD.1987.79640},
}
@book{StantonBook,
title={Pulse technology},
author={Stanton, W.A.},
isbn={9780471820802},
lccn={64017153},
year={1964},
publisher={Wiley}
}
@book{MillmanBook,
title={Pulse, digital, and switching waveforms: devices and circuits for their generation and processing},
author={Millman, J. and Taub, H.},
isbn={9780070855120},
year={1981},
publisher={McGraw-Hill}
}
@book{LinvillBook,
title={Transistors and active circuits},
author={Linvill, J.G. and Gibbons, J.F.},
lccn={60015759},
series={McGraw-Hill electrical and electronic engineering series},
year={1961},
publisher={McGraw-Hill}
}
@ARTICLE{LinvillIREPaper,
author={Linvill, J.G. and Mattson, R.H.},
journal={Proceedings of the IRE}, title={Junction Transistor Blocking Oscillators},
year={1955},
month={nov. },
volume={43},
number={11},
pages={1632 -1639},
keywords={},
doi={10.1109/JRPROC.1955.277989},
ISSN={0096-8390},}
@ARTICLE{KorzekwaIREPaper,
author={ Korzekwa, S.},
journal={Circuit Theory, IRE Transactions on}, title={Transistor Blocking Oscillator Analysis},
year={1961},
month={dec},
volume={8},
number={4},
pages={ 473 - 479},
keywords={ Solid-state circuits;},
doi={10.1109/TCT.1961.1086851},
ISSN={0096-2007},}
@ARTICLE{NormanIEEPaper,
author={Norman, P. and Smith, E.J.E.},
journal={Proceedings of the IEE - Part B: Electronic and Communication Engineering}, title={The design of transistor blocking oscillators},
year={1959},
month={may },
volume={106},
number={18},
pages={1251 -1259},
keywords={oscillators;oscillators;oscillators;},
doi={10.1049/pi-b-2.1959.0229},
ISSN={0369-8890},}
@ARTICLE{McDonaldIEEEPaper,
author={ McDonald, J.},
journal={Circuit Theory, IEEE Transactions on}, title={Circuit Models to Predict Switching Performance of Nanosecond Blocking Oscillators},
year={1964},
month={dec},
volume={11},
number={4},
pages={ 442 - 448},
keywords={},
doi={10.1109/TCT.1964.1082353},
ISSN={0018-9324},}
@misc{StandardBlocking,
author= "C. Gil Soriano",
title= {{Standard Blocking Output Signal Definition for CTDAH board}},
month= sep,
year= 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
\ No newline at end of file
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\begin{document}
\title{CONV-TTL-BLO HDL specifications}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\begin{abstract}
This document tackles with:
\begin{itemize}
\item HDL development priorities
\item Memory mapping
\end{itemize}
\end{abstract}
\\
\tableofcontents
\pagebreak
\section{HDL schema}
The following schema is used as a reference for the HDL development:\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.3, keepaspectratio]{Figures/HDLspecs.png}
\caption{CONV-TTL-BLO HDL structure}
\end{center}
\end{figure}
\subsection{Control}
It is the part that bridges the I2C frames to the correct wishbone module. The
tasks it is responsible of are:
\begin{itemize}
\item Correctly power-up the rest of the modules.
\item Provide connectivity of all the wishbone registers via
I2C. It manages control access to the registers.
\end{itemize}
\subsection{I2C slave}
An I2C slave is needed to receive the frames from the VME64x SERA and SERB pins
in P1 connector. This module will communicates with \textit{control hdl module}
in the following fashion:
\begin{itemize}
\item It connects as a wishbone \textbf{slave} to control hdl core and
provides interrupt lines for data reception and transmission.
\end{itemize}
The main reason of implementing a wishbone slave is that by dividing data
reception -\textit{i2c slave}- from control access -\textit{control}- the
development is more reliable and clear.\\ This module offers configuration
registers to ease the task of data assembly --for instance, the communication
schema in ELMA crate.
\subsection{Trigger}
The trigger manages the pulse repetition. The parameters handled that affect the
pulse repetition are:
\begin{itemize}
\item \textbf{Debouncing} stages of the input pulse.
\item \textbf{Pulse length} of the output pulse according to Standard
Blocking definition.
\item \textbf{Minimun spacing between pulses} to let the magnetizing current
of the transformer be drained off. It is also refered in other documents as
\textit{Inactivity timeout upon output pulse is outputted}.
\end{itemize}
The pulses must be time-tagged. It can be achieved either by a
lossy time-tagging via i2c, or with a precise one via White Rabbit. Every
time-tag has appended event identifiers (metadata).
\subsubsection{Time-tagging Format}
The format of the time-tags should be defined. At this moment, an implementation
with 96 bits for timestamping with 32 bits of metadata is the default. A record
of the last 256 time-tags per channel is hold in the FPGA.
\subsection{Multiboot manager}
The task of the \textit{Multiboot manager} is to manage a golden bitstream and
another one to update the FPGA from. From within this module a FPGA
reprogramming command is issued.
\subsection{EEPROM manager}
The module responsible to write into the EEPROM, read it back and reprogramming
the memory module. It should be targeted to interface directly with a MICRON
M25P32-VMF6P memory. It will be able to write the MAC address that will be used
by White Rabbit and block memory parts of the EEPROM.
\subsection{White Rabbit core}
Provides precise timestamping.
\pagebreak
\section{HDL development milestones}
The HDL development is scheduled to tackle with several milestones:
\begin{enumerate}
\item \textit{i2c slave} module: verification
\item \textit{Control} module: reset the rest of HDL cores. Bypassing
i2c instrucctions to wishbone interface.
\item \textit{Multiboot manager} module: multiboot between different
precharged bitstreams.
\item \textit{EEPROM manager} module: write a bitstream through the i2c interface.
\item Integration of White Rabbit core: fine timestamping
\end{enumerate}
\section{Wishbone memory map}
So as to access the devices thanks to \textit{CTDAH control} the
following memory map is proposed:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
&& \textbf{FIRST} & \textbf{LAST}\\
\textbf{NUMBER}&\textbf{DEVICE} & \textbf{WISHBONE} & \textbf{WISHBONE}\\
&& \textbf{ADDRESS} & \textbf{ADDRESS}\\
\hline
\hline
0 & Control & 0x0100 & 0x01FF \\
\hline
1 & I2C slave & 0x0200 & 0x02FF \\
\hline
2 & Trigger 1 & 0x0300 & 0x03FF \\
\hline
3 & Trigger 2 & 0x0400 & 0x04FF \\
\hline
4 & Trigger 3 & 0x0500 & 0x05FF \\
\hline
5 & Trigger 4 & 0x0600 & 0x06FF \\
\hline
6 & Trigger 5 & 0x0700 & 0x07FF \\
\hline
7 & Trigger 6 & 0x0800 & 0x08FF \\
\hline
8 & Multiboot manager & 0x0900 & 0x09FF \\
\hline
9 & EEPROM manager & 0x0A00 & 0x0AFF \\
\hline
10 & White Rabbit core & 0x0B00 & 0x0BFF \\
\hline
\hline
11 & EEPROM memory & 0x1000 & 0x1FFF \\
\hline
\end{tabular}
\end{center}
%\section{HDL modules}
%\subsection{i2c slave}
%w\subsection{trigger}
%$\section{Functional specifications}
%CTDAH board holds the logic that controls pulse conversion and forwarding.
%Three input and output signal levels can be handled: TTL, inverted-TTL and
%%Standard Blocking.
%The behaviour of the HDL is as follows:
%\begin{itemize}
% \item Everytime an input pulse is detected, the pulse is converted to the
% output level and time-tagged. Glitches are not forwarded.
% \item The input events are detected and logged.
% \item CTDAH communicates with a monitor board via I$^2$C through VME64x
% connector. The monitor board can set CTDAH control parameters, receive
% notifications from it, report problems affecting the backplane and reprogram
% CTDAH FPGA.
%\end{itemize}
%
%A block diagram for the HDL core is shown below:\\
%
%\begin{figure}[htb]
% \begin{center}
% \includegraphics[scale=1, keepaspectratio]{BlockDiagram.png}
% \caption{CTDAH HDL structure}
% \end{center}
%\end{figure}
%
%
%
%\pagebreak
%\section{Technical specifications}
%
%
%
%\subsection{Memory mapping}
%
%
%\subsection{Time tagger register}
%Each time an input event is detected, it is time-tagged in the internal FPGA
%memory.\\
%A time-tag consist of six words. The first two words form the PULSE\_ID field
%and the later four ones, the UTC time-tag:
%
%\begin{center}
%\begin{tabular}{|c|c|}
%\hline
%0 & PULSE\_ID_U\\
%\hline
%1 & PULSE\_ID_L\\
%\hline
%2 & UTC_{UU}\\
%\hline
%3 & UTC_{UL}\\
%\hline
%4 & UTC_{LU}\\
%\hline
%5 & UTC_{LL}\\
%\hline
%\end{tabular}
%\end{center}
%\subsubsection{PULSE\_ID field}
%The PULSE\_ID$_L$ contains the length of the output pulse, in clock cycles. The
%PULSE\_ID$_U$ field is defined as follows:
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}
%\hline
%15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%& & & & & & \tiny{OM1} & \tiny{OM0} & & & & \tiny{IOK} & \tiny{IFL} &
%\tiny{IFS} & \tiny{IM1} &\tiny{IM0}\\
%\hline
%\end{tabular}
%\end{center}
%\\
%\subsubsection{UTC field}
\end{document}
\relax
\@writefile{toc}{\contentsline {section}{\numberline {1}Title}{1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Subtitle}{1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Another subtitle}{1}}
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@TECHREPORT{UG380,
institution= "Xilinx Inc.",
title= {{Spartan-6 FPGA Configuration User Guide}},
month= jul,
year= 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
\ No newline at end of file
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____ ____
/ /\/ /
/___/ \ / VENDOR : Xilinx Inc.
\ \ \/ VERSION : 14.2 (P.28xd)
\ \ APPLICATION : /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/compxlib
/ / CONTENTS : Compilation Log
/___/ /\ FILENAME : compxlib.log
\ \ / \
\___\/\___\
Release 14.2 - /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/compxlib 14.2 (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
ERROR:Portability:90 - Command line error: Switch "--help" is not allowed.
Usage: compxlib {-arch <arch_name>} [-cfg [<cfg_file>]] [-dir <output_dir>] [-e <dir_parh>] [-exclude_sublib] [-exclude_superseded] [-info <dir_path>] [-intstyle ise|xflow|silent] [-l <language>] {-lib <lib_name>} [-log <log_file>] [-p <dir_path>] {-s
<simulator>} [-source_lib <dir_path>] [-verbose] [-w] [-64bit] {-cfgopt <opt_string>}
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-------------------------------------------------------------------------------
-- LIST OF ISSUES
-------------------------------------------------------------------------------
ISSUE COMMENT
464 A MOSFET got broken. Some captures to detect a broken MOSFET.
523 Problem with the I2C because of unwanted clock stretching and poor
pulling-up of the SCL and SDA lines.
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