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Commit 271a30e4 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Fixed active file indentations & some naming.

parent 494c7f90
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hdl/IMAGES/image1/project/image1.gise
View file @ 271a30e4
......@@ -76,6 +76,7 @@
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359864" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1361359864">
<status xil_pn:value="SuccessfullyRun"/>
......@@ -101,7 +102,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359880" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361359864">
<transform xil_pn:end_ts="1361383048" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361383029">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -123,7 +124,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361359886" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361359880">
<transform xil_pn:end_ts="1361383079" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361383072">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -133,11 +134,9 @@
<outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361359919" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361359886">
<transform xil_pn:end_ts="1361383118" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361383079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="image1_top.pcf"/>
<outfile xil_pn:name="image1_top_map.map"/>
......@@ -148,7 +147,7 @@
<outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1361359953" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361359919">
<transform xil_pn:end_ts="1361383152" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361383118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -163,7 +162,7 @@
<outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361359972" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361359953">
<transform xil_pn:end_ts="1361383171" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361383152">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -174,15 +173,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1361359976" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361359976">
<transform xil_pn:end_ts="1361383284" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361383284">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1361359953" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361359944">
<transform xil_pn:end_ts="1361383152" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361383144">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 271a30e4
This diff is collapsed.
hdl/IMAGES/image1/top/image1_top.vhd
View file @ 271a30e4
......@@ -43,8 +43,13 @@ use work.wishbone_pkg.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity image1_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (RST_N : in STD_LOGIC;
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
);
port
(
RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
FPGA_CLK_N : in STD_LOGIC;
......@@ -94,15 +99,21 @@ entity image1_top is
--! 24V rail after a security given
--! delay
FPGA_RTMM_N : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0));
FPGA_RTMP_N : in STD_LOGIC_VECTOR(2 downto 0)
);
end image1_top;
architecture Behavioral of image1_top is
component image1_core is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (rst_n : in STD_LOGIC;
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6
);
port
(
rst_n : in STD_LOGIC;
clk_20MHz_i : in STD_LOGIC;
clk_125MHz_i : in STD_LOGIC;
--! LEDs
......@@ -136,7 +147,8 @@ architecture Behavioral of image1_top is
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
rtm_i : in t_rtm_i);
rtm_i : in t_rtm_i
);
end component;
signal s_clk_125MHz : STD_LOGIC;
......@@ -151,9 +163,17 @@ architecture Behavioral of image1_top is
begin
inst_125m_IBUFGDS : IBUFGDS
generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => TRUE)
port map (O => s_clk_125MHz, I => FPGA_CLK_P,
IB => FPGA_CLK_N);
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => FPGA_CLK_P,
IB => FPGA_CLK_N,
O => s_clk_125MHz
);
LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
......@@ -185,7 +205,9 @@ begin
inst_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6)
port map(rst_n => RST_N,
port map
(
rst_n => RST_N,
clk_20MHz_i => CLK20_VCXO,
clk_125MHz_i => s_clk_125MHz,
led_array_o => s_led_array,
......@@ -210,6 +232,7 @@ begin
level_i => LEVEL,
switch_i => s_switch_i(1),
manual_rst_n_o => MR_N,
rtm_i => s_rtm_i);
rtm_i => s_rtm_i
);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_core.vhd
View file @ 271a30e4
......@@ -24,10 +24,15 @@ use IEEE.NUMERIC_STD.ALL;
use work.ctdah_pkg.ALL;
entity basic_trigger_core is
generic(g_CLK_PERIOD : TIME;
generic
(
g_CLK_PERIOD : TIME;
g_OUTPUT_PULSE_LENGTH : TIME;
g_LED_BLINKING_LENGTH : TIME);
port (wb_rst_i : in STD_LOGIC;
g_LED_BLINKING_LENGTH : TIME
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
......@@ -36,7 +41,8 @@ entity basic_trigger_core is
crop_o : out STD_LOGIC;
led_o : out STD_LOGIC);
led_o : out STD_LOGIC
);
end basic_trigger_core;
architecture Behavioral of basic_trigger_core is
......@@ -59,8 +65,6 @@ architecture Behavioral of basic_trigger_core is
-- return v;
-- end ledlen;
constant c_PULSE_LENGTH : NATURAL := g_OUTPUT_PULSE_LENGTH/g_CLK_PERIOD;
constant c_LED_LENGTH : NATURAL := g_LED_BLINKING_LENGTH/g_CLK_PERIOD;
......@@ -75,28 +79,46 @@ begin
s_pulse <= pulse_i;
inst_debo: gc_debouncer
generic map( g_LENGTH => 2)
port map(rst => wb_rst_i,
cmp_debouncer: gc_debouncer
generic map
(
g_LENGTH => 2
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_pulse,
output => s_deglitched_pulse,
glitch_mask => "11");
pulse_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_PULSE_LENGTH)
port map (rst => wb_rst_i,
glitch_mask => "11"
);
cmp_pulse_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_PULSE_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => pulse_o,
output_n => pulse_n_o);
led_monostable : gc_simple_monostable
generic map (g_PULSE_LENGTH => c_LED_LENGTH)
port map (rst => wb_rst_i,
output_n => pulse_n_o
);
cmp_led_monostable : gc_simple_monostable
generic map
(
g_PULSE_LENGTH => c_LED_LENGTH
)
port map
(
rst => wb_rst_i,
clk => wb_clk_i,
input => s_deglitched_pulse,
output => led_o,
output_n => open);
output_n => open
);
end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 271a30e4
......@@ -29,11 +29,15 @@ use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
generic
(
g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_ttl_o : out STD_LOGIC;
......@@ -67,8 +71,7 @@ architecture Behavioral of basic_trigger_top is
signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1)
:= (others => '0');
signal s_crop : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1) := (others => '0');
signal s_level : STD_LOGIC;
signal s_fpga_o_en : STD_LOGIC;
......@@ -76,15 +79,19 @@ architecture Behavioral of basic_trigger_top is
signal s_fpga_o_inv_en : STD_LOGIC;
signal s_fpga_o_blo_en : STD_LOGIC;
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1)
of STD_LOGIC_VECTOR(3 downto 0);
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1) of STD_LOGIC_VECTOR(3 downto 0);
signal s_pulse_i_reg : delay_array;
component basic_trigger_core is
generic(g_CLK_PERIOD : TIME := g_CLK_PERIOD;
generic
(
g_CLK_PERIOD : TIME := g_CLK_PERIOD;
g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH;
g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH);
port (wb_rst_i : in STD_LOGIC;
g_LED_BLINKING_LENGTH : TIME := g_LED_BLINKING_LENGTH
);
port
(
wb_rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC;
......@@ -93,7 +100,8 @@ architecture Behavioral of basic_trigger_top is
crop_o : out STD_LOGIC;
led_o : out STD_LOGIC);
led_o : out STD_LOGIC
);
end component;
begin
......@@ -109,7 +117,7 @@ begin
not pulse_i_front;
s_pulse_i <= s_pulse_i_front or pulse_i_rear;
fpga_o_en <= s_fpga_o_en when switch_i = '0' else '0';
fpga_o_en <= s_fpga_o_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= s_fpga_o_ttl_en;
fpga_o_inv_en <= s_fpga_o_inv_en;
fpga_o_blo_en <= s_fpga_o_blo_en;
......@@ -121,12 +129,12 @@ begin
not s_pulse_o;
pulse_o_rear <= s_pulse_o;
inv_o <= inv_i;--! As we have one Schmitt inverter in the input,
--! As we have one Schmitt inverter in the input,
--! and a buffer in the output, there's no need
--! to invert here.
inv_o <= inv_i;
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
gen_trig_cores: for i in 1 to g_NUMBER_OF_CHANNELS generate
trigger: basic_trigger_core
port map
(
......@@ -138,7 +146,7 @@ begin
crop_o => open,
led_o => s_led(i)
);
end generate i_repetitors;
end generate gen_trig_cores;
--! @brief Process to lock the enables so to avoid output glitches
--! on the startup.
......
hdl/ctdah_lib/rtl/gc_counter.vhd
View file @ 271a30e4
......@@ -41,15 +41,17 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
generic
(
g_DATA_WIDTH: NATURAL
);
port (
);
port
(
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
);
end gc_counter;
architecture Behavioral of gc_counter is
......@@ -57,24 +59,17 @@ architecture Behavioral of gc_counter is
begin
main_proc: process(clk_i, rst_i)
p_main: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
begin
if rst_i = '1' then
cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if en_i = '1' then
-- Increment the counter if counting is enabled
cnt_s := cnt_s + 1;
else
end if;
else
end if;
cnt_o <= std_logic_vector(cnt_s);
end process;
end process p_main;
end Behavioral;
hdl/ctdah_lib/rtl/gc_debouncer.vhd
View file @ 271a30e4
......@@ -35,25 +35,25 @@ entity gc_debouncer is
end gc_debouncer;
architecture Behavioral of gc_debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
component gc_ff
port (
component gc_ff
port
(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
end component;
begin
ff1: gc_ff
port map(
port map
(
Q => meta_ff1,
C => clk,
CLR => rst,
......@@ -61,7 +61,8 @@ begin
);
ff2: gc_ff
port map(
port map
(
Q => delay_s(0),
C => clk,
CLR => rst,
......@@ -69,15 +70,16 @@ begin
);
-- Metastability solved here
delay_line: for i in 1 to g_LENGTH-1 generate
gen_delay_line: for i in 1 to g_LENGTH-1 generate
D_Flip_Flop : gc_ff
port map (
port map
(
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
D => delay_s(i-1)
);
end generate gen_delay_line;
process (clk)
begin
......
hdl/ctdah_lib/rtl/gc_ff.vhd
View file @ 271a30e4
......@@ -23,7 +23,8 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_ff is
port(
port
(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
......@@ -43,7 +44,6 @@ begin
else
Q <= D;
end if;
else
end if;
end process;
......
hdl/ctdah_lib/rtl/gc_simple_monostable.vhd
View file @ 271a30e4
......@@ -23,19 +23,23 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_simple_monostable is
generic(g_PULSE_LENGTH : NATURAL := 20);
port (
generic
(
g_PULSE_LENGTH : NATURAL := 20
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
output_n : out STD_LOGIC);
output_n : out STD_LOGIC
);
end gc_simple_monostable;
architecture Behavioral of gc_simple_monostable is
constant c_count_max : UNSIGNED (63 downto 0) :=
to_unsigned(g_PULSE_LENGTH, 64);
constant c_count_max : UNSIGNED (63 downto 0) := to_unsigned(g_PULSE_LENGTH, 64);
signal s_count : UNSIGNED (63 downto 0) := to_unsigned(0, 64);
......@@ -69,14 +73,13 @@ begin
s_count <= to_unsigned(0, 64);
s_running <= '0';
if (s_input = '1')
and (s_input_d0 = '0') then
if (s_input = '1') and (s_input_d0 = '0') then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
s_output_n <= '0';
elsif s_running = '1' then
if s_count < c_count_max then
elsif (s_running = '1') then
if (s_count < c_count_max) then
s_count <= s_count + 1;
s_running <= '1';
s_output <= '1';
......
hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
View file @ 271a30e4
......@@ -29,7 +29,9 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_bit is
port (rst_i : in STD_LOGIC;
port
(
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
......@@ -38,13 +40,14 @@ entity i2c_bit is
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC);
done_o : out STD_LOGIC
);
end i2c_bit;
architecture Behavioral of i2c_bit is
type bit_fsm is (R0_RESET,
type t_state is (
R0_RESET,
S0_IDLE,
S1A_HIGH_TMP,
S1A_HIGH,
......@@ -53,14 +56,15 @@ architecture Behavioral of i2c_bit is
S2A_START_TMP,
S2A_START,
S2B_STOP_DETECT,
Q1_ERROR);
Q1_ERROR
);
--! It specifies the maximum number of stages that will be employed for
--! deglitching. Clocked with wb_clk_i
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with wb_clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
--! Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
-- Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
signal s_sda_deglitched : STD_LOGIC;
signal s_sda_deglitched_d1 : STD_LOGIC;
......@@ -68,54 +72,67 @@ architecture Behavioral of i2c_bit is
signal s_scl_deglitched : STD_LOGIC;
signal s_scl_deglitched_d1 : STD_LOGIC;
signal i2c_bit_fsm : bit_fsm;
signal state : t_state;
signal s_scl_rising : STD_LOGIC;
signal s_scl_falling : STD_LOGIC;
begin
debouncer_scl_i: i2c_debouncer
generic map(g_LENGTH => 6)
port map(rst => rst_i,
cmp_scl_debouncer: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => wb_clk_i,
input => scl_i,
output => s_scl_deglitched,
glitch_mask => c_GLITCH_MASK);
--! Probably safer operation if we add one extra delay to the scl line.
--! However, we increase the glitch time while placing an ACK.
--! We have not implemented a counter to foresee the glitch due to the
--! strange behaviour in Renesas I2C which rescales dinamically (that
--! means in the middle of an I2C transaction) the scl line.
--! Due to the variability of the scl period when an I2C transaction is
--! in progress, it is better not to add a "guesser" of the scl period.
ff1_scl : gc_ff
port map(Q => s_scl_deglitched_d1,
glitch_mask => c_GLITCH_MASK
);
-- Probably safer operation if we add one extra delay to the scl line.
-- However, we increase the glitch time while placing an ACK.
-- We have not implemented a counter to foresee the glitch due to the
-- strange behaviour in Renesas I2C which rescales dinamically (that
-- means in the middle of an I2C transaction) the scl line.
-- Due to the variability of the scl period when an I2C transaction is
cmp_scl_ff: gc_ff
port map
(
Q => s_scl_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_scl_deglitched);
D => s_scl_deglitched
);
debouncer_sda_i: i2c_debouncer
generic map(g_LENGTH => 6)
port map(rst => rst_i,
cmp_sda_debounce: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => wb_clk_i,
input => sda_i,
output => s_sda_deglitched,
glitch_mask => c_GLITCH_MASK);
glitch_mask => c_GLITCH_MASK
);
ff1_sda : gc_ff
port map(Q => s_sda_deglitched_d1,
cmp_sda_ff: gc_ff
port map
(
Q => s_sda_deglitched_d1,
C => wb_clk_i,
CLR => rst_i,
D => s_sda_deglitched);
D => s_sda_deglitched
);
--! This is the process that samples the scl for detecting
--! rise and falling edges
-- This is the process that samples the scl for detecting
-- rise and falling edges
reg_proc: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
......@@ -129,120 +146,129 @@ begin
s_scl_rising <= '0';
s_scl_falling <= '0';
end if;
else
end if;
end process;
--! @brief Combiantion process to update the outputs.
--! @param i2c_bit_fsm Finite state machine for the SDA bit detection.
p_comb_output: process(i2c_bit_fsm)
-- Combinatorial process to update the outputs.
p_comb_output: process(state)
begin
start_o <= '0';
pause_o <= '0';
rcved_o <= '0';
--! done_o is a one-clock signal
done_o <= '0';
case i2c_bit_fsm is
case state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1A_HIGH =>
rcved_o <= '1';
done_o <= '1';
when S1B_LOW =>
rcved_o <= '0';
done_o <= '1';
when S2A_START =>
start_o <= '1';
done_o <= '1';
when S2B_STOP_DETECT =>
pause_o <= '1';
done_o <= '1';
when Q1_ERROR =>
null;
when others =>
null;
end case;
end process;
end process p_comb_output;
--! @brief The fsm of this module, later on the sda sampled line is
--! validated in the falling edge of scl.
--! @bparam wb_clk_i
-- The fsm of this module, later on the sda sampled line is
-- validated in the falling edge of scl.
p_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if rst_i = '1' then
i2c_bit_fsm <= R0_RESET;
--! After a detection of a falling edge we update the
--! detection of a '0', a '1' and a start condition.
elsif s_scl_falling = '1' then
case i2c_bit_fsm is
if (rst_i = '1') then
state <= R0_RESET;
elsif (s_scl_falling = '1') then
-- After a detection of a falling edge we update the
-- detection of a '0', a '1' and a start condition.
case state is
when S1A_HIGH_TMP =>
i2c_bit_fsm <= S1A_HIGH;
state <= S1A_HIGH;
when S1B_LOW_TMP =>
i2c_bit_fsm <= S1B_LOW;
state <= S1B_LOW;
when S2A_START_TMP =>
i2c_bit_fsm <= S2A_START;
state <= S2A_START;
when others =>
i2c_bit_fsm <= S0_IDLE;
state <= S0_IDLE;
end case;
--! When a rising edge is detected we annotate the first value
--! in SDA: either a temporary '0' or '1'
elsif s_scl_rising = '1' then
if s_sda_deglitched_d1 = '1' then
i2c_bit_fsm <= S1A_HIGH_TMP;
elsif (s_scl_rising = '1') then
-- When a rising edge is detected we annotate the first value
-- in SDA: either a temporary '0' or '1'
if (s_sda_deglitched_d1 = '1') then
state <= S1A_HIGH_TMP;
else
i2c_bit_fsm <= S1B_LOW_TMP;
state <= S1B_LOW_TMP;
end if;
else
--! When we are in high level of a scl cycle, we keep on updating
--! the fsm
if s_scl_deglitched = '1' then
case i2c_bit_fsm is
--! Just for random bit swapped coverage.
-- When we are in high level of a scl cycle, we keep on updating
-- the FSM
if (s_scl_deglitched = '1') then
case state is
-- Just for random bit swapped coverage.
when S0_IDLE =>
if s_sda_deglitched = '1' then
i2c_bit_fsm <= S1A_HIGH_TMP;
if (s_sda_deglitched = '1') then
state <= S1A_HIGH_TMP;
else
i2c_bit_fsm <= S1B_LOW_TMP;
state <= S1B_LOW_TMP;
end if;
when S1A_HIGH_TMP =>
if s_sda_deglitched = '0' then
-- The detection of the start condition will be reported
-- in the next SCL rising edge.
i2c_bit_fsm <= S2A_START_TMP;
else
state <= S2A_START_TMP;
end if;
when S1B_LOW_TMP =>
if s_sda_deglitched = '1' then
-- The detection of the pause condition MUST be
-- reported immediately.
i2c_bit_fsm <= S2B_STOP_DETECT;
else
state <= S2B_STOP_DETECT;
end if;
when S2A_START_TMP =>
if s_sda_deglitched = '1' then
if (s_sda_deglitched = '1') then
--! This happens if the deglitching is not enough
i2c_bit_fsm <= Q1_ERROR;
else
state <= Q1_ERROR;
end if;
when others =>
i2c_bit_fsm <= S0_IDLE;
state <= S0_IDLE;
end case;
else
if s_scl_deglitched_d1 = '0' then
i2c_bit_fsm <= S0_IDLE;
else
if (s_scl_deglitched_d1 = '0') then
state <= S0_IDLE;
end if;
end if;
end if;
else
end if;
end process;
end process p_fsm;
end Behavioral;
hdl/i2c_slave_wb_master/rtl/i2c_debounce.vhd
View file @ 271a30e4
......@@ -30,57 +30,69 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_debouncer is
generic (g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH);
port (rst : in STD_LOGIC;
generic
(
g_LENGTH : NATURAL := c_DEBOUNCE_LENGTH
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0));
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal s_input_d0 : STD_LOGIC;
--! The first of this signal is already stable (ff'ed two times at [0])
-- The first of this signal is already stable (ff'ed two times at [0])
signal s_delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
ff1: gc_ff
port map(
cmp_ff1: gc_ff
port map
(
Q => s_input_d0,
C => clk,
CLR => rst,
D => input);
D => input
);
ff2: gc_ff
port map(
cmp_ff2: gc_ff
port map
(
Q => s_delay(0),
C => clk,
CLR => rst,
D => s_input_d0);
D => s_input_d0
);
sync_delay_line: for i in 1 to g_LENGTH - 1 generate
D_Flip_Flop : gc_ff
port map (
gen_sync_delay_line: for i in 1 to g_LENGTH - 1 generate
cmp_ff: gc_ff
port map
(
Q => s_delay(i),
C => clk,
CLR => rst,
D => s_delay(i-1));
end generate sync_delay_line;
D => s_delay(i-1)
);
end generate gen_sync_delay_line;
p_output : process (clk)
p_output: process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
if (rst = '1') then
output <= '1';
else
--! We can deglitch either zeros or ones
-- We can deglitch either zeros or ones
if ( (s_delay and glitch_mask) = glitch_mask
or (not(s_delay)and glitch_mask) = glitch_mask) then
or (not(s_delay) and glitch_mask) = glitch_mask) then
output <= s_delay(0);
else
--! Internall pull-up of the pin
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 271a30e4
This diff is collapsed.
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 271a30e4
......@@ -26,7 +26,10 @@ use work.i2c_slave_pkg.ALL;
use work.ctdah_pkg.ALL;
entity i2c_slave_top is
generic (g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD); -- Specify in ns
generic
(
g_WB_CLK_PERIOD : TIME := c_WB_CLK_PERIOD -- Specify in ns
);
port
(
sda_oen : out STD_LOGIC;
......@@ -70,32 +73,31 @@ end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
signal s_CTR0_slv : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal s_CTR0 : r_CTR0;
signal s_LT_slv : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal ctr0 : STD_LOGIC_VECTOR(r_CTR0'a_length - 1 downto 0);
signal lt : STD_LOGIC_VECTOR(r_LT'a_length - 1 downto 0);
signal s_DRXA : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_DRXB : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxa : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal drxb : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_pf_wb_addr : STD_LOGIC;
signal s_pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal s_rd_done : STD_LOGIC;
signal s_wr_done : STD_LOGIC;
signal pf_wb_addr : STD_LOGIC;
signal pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal rd_done : STD_LOGIC;
signal wr_done : STD_LOGIC;
signal s_clk_i2c : STD_LOGIC;
signal s_rst_i2c : STD_LOGIC;
signal s_reset_extensor : STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1
downto 0) := (others => '1');
signal rst_i2c : STD_LOGIC;
signal reset_extender: STD_LOGIC_VECTOR(2**c_RST_EXTENSOR - 1 downto 0) := (others => '1');
begin
pf_wb_addr_o <= s_pf_wb_addr;
rd_done_o <= s_rd_done;
wr_done_o <= s_wr_done;
--! Added for simulation
s_CTR0 <= f_CTR0(s_CTR0_slv);
pf_wb_addr_o <= pf_wb_addr;
rd_done_o <= rd_done;
wr_done_o <= wr_done;
inst_i2c_slave_core: i2c_slave_core
port map(clk_i => wb_clk_i,
cmp_i2c_slave_core: i2c_slave_core
port map
(
clk_i => wb_clk_i,
rst_i => wb_rst_i,
sda_oen => sda_oen,
......@@ -105,21 +107,24 @@ begin
scl_i => scl_i,
scl_o => scl_o,
CTR0_i => s_CTR0_slv,
LT_o => s_LT_slv,
DRXA_o => s_DRXA,
DRXB_o => s_DRXB,
CTR0_i => ctr0,
LT_o => lt,
DRXA_o => drxa,
DRXB_o => drxb,
pf_wb_addr_o => s_pf_wb_addr,
pf_wb_data_i => s_pf_wb_data,
rd_done_o => s_rd_done,
wr_done_o => s_wr_done);
pf_wb_addr_o => pf_wb_addr,
pf_wb_data_i => pf_wb_data,
rd_done_o => rd_done,
wr_done_o => wr_done
);
inst_i2c_regs: i2c_regs
port map(pf_wb_addr_i => s_pf_wb_addr,
pf_wb_data_o => s_pf_wb_data,
rd_done_i => s_rd_done,
wr_done_i => s_wr_done,
cmp_i2c_regs: i2c_regs
port map
(
pf_wb_addr_i => pf_wb_addr,
pf_wb_data_o => pf_wb_data,
rd_done_i => rd_done,
wr_done_i => wr_done,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk_i,
......@@ -146,25 +151,25 @@ begin
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
CTR0_o => s_CTR0_slv,
LT_i => s_LT_slv,
DRXA_i => s_DRXA,
DRXB_i => s_DRXB,
i2c_addr_i => i2c_addr_i);
CTR0_o => ctr0,
LT_i => lt,
DRXA_i => drxa,
DRXB_i => drxb,
i2c_addr_i => i2c_addr_i
);
s_rst_i2c <= s_reset_extensor(2**c_RST_EXTENSOR - 1);
rst_i2c <= reset_extender(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
s_reset_extensor <= (others => '1');
reset_extender <= (others => '1');
else
s_reset_extensor(0) <= '0';
reset_extender(0) <= '0';
for i in 1 to 2**c_RST_EXTENSOR -1 loop
s_reset_extensor(i) <= s_reset_extensor(i-1);
reset_extender(i) <= reset_extender(i-1);
end loop;
end if;
end if;
......
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