sampling it with the 125 MHz clock to check for edges, wouldn't work?
some synplify warnings, mainly for code cleanup!
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@W:CD638 : conv_ttl_blo.vhd(336) | Signal clk_50 is undriven
@W:CD638 : conv_ttl_blo.vhd(336) | Signal clk_buf_50 is undriven
@W:CD638 : conv_ttl_blo.vhd(337) | Signal clk_200 is undriven
@W:CD638 : conv_ttl_blo.vhd(337) | Signal clk_buf_200 is undriven
@W:CD638 : conv_ttl_blo.vhd(338) | Signal clk_250 is undriven
@W:CD638 : conv_ttl_blo.vhd(338) | Signal clk_buf_250 is undriven
@W:CD638 : conv_ttl_blo.vhd(339) | Signal pll_fb_in is undriven
@W:CD638 : conv_ttl_blo.vhd(339) | Signal pll_fb_out is undriven
@W:CD638 : conv_ttl_blo.vhd(340) | Signal pll_locked is undriven
@W:CD638 : conv_ttl_blo.vhd(343) | Signal rst is undriven
@W:CD638 : conv_ttl_blo.vhd(355) | Signal trig_inv is undriven
@W:CD638 : conv_ttl_blo.vhd(367) | Signal blo_ch_en is undriven
@W:CD638 : conv_ttl_blo.vhd(370) | Signal inv_outputs is undriven
@W:CD638 : conv_ttl_blo.vhd(373) | Signal front_led_en is undriven
@W:CD638 : conv_ttl_blo.vhd(374) | Signal rear_led_en is undriven
@W:CD638 : conv_ttl_blo.vhd(384) | Signal tmp_pulse is undriven
@W:CD638 : conv_ttl_blo.vhd(396) | Signal i2c_up is undriven
@W:CL159 : conv_ttl_blo.vhd(98) | Input fpga_gap_i is unused
@W:CD638 : multiboot_fsm.vhd(154) | Signal fl_bcnt is undriven
@W:CD638 : multiboot_fsm.vhd(156) | Signal fl_sreg is undriven
@W:CD638 : multiboot_fsm.vhd(158) | Signal first is undriven
@W:CD638 : multiboot_regs.vhd(85) | Signal multiboot_cr_flr_int is undriven
@W:CD638 : multiboot_regs.vhd(86) | Signal multiboot_cr_flw_int is undriven
@W:CD638 : multiboot_regs.vhd(89) | Signal multiboot_sr_flrrdy_int is undriven
@W:CD638 : multiboot_regs.vhd(90) | Signal multiboot_sr_flwrdy_int is undriven
@W:CD638 : multiboot_regs.vhd(93) | Signal multiboot_flrdr_int is undriven
@W:CD638 : multiboot_regs.vhd(94) | Signal multiboot_flwdr_int is undriven
@W:CD638 : multiboot_regs.vhd(95) | Signal multiboot_far_data_load_int is undriven
@W:CL240 : xil_multiboot.vhd(55) | wbs_o.int is not assigned a value (floating) -- simulation mismatch possible.
@W:CL240 : xil_multiboot.vhd(55) | wbs_o.rty is not assigned a value (floating) -- simulation mismatch possible.
@W:CL240 : xil_multiboot.vhd(55) | wbs_o.err is not assigned a value (floating) -- simulation mismatch possible.
@W:CD638 : glitch_filt.vhd(72) | Signal degl_dat is undriven
@W:CD638 : vbcp_wb.vhd(129) | Signal done_d0 is undriven
@W:CL159 : vbcp_wb.vhd(97) | Input wbm_rty_i is unused
@W:CL159 : conv_regs.vhd(25) | Input wb_sel_i is unused
@W:CL159 : multiboot_regs.vhd(50) | Input wb_sel_i is unused
/!\ clocks /!\ as I m seeing Matthieu+Tom have also commented
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@W:MT420 : Found inferred clock conv_ttl_blo|fpga_clk_n_i. Please declare a user-defined clock on object "p:fpga_clk_n_i"
@W:MT462 : conv_ttl_blo.vhd(635) | Net gen_ttl_pulse_generators\.2\.cmp_ttl_pulse_gen.trig_i appears to be an unidentified clock source. Assuming default frequency.
