Commit 2c4c8181 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Updated user guide

parent 69ea3cda
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill August 22, 2014
\hfill September 26, 2014
\vspace*{3cm}
......
......@@ -17,7 +17,7 @@ Base address: 0x000
\endhead
\hline
\endfoot
0x0 & 0x54424C4f & BIDR & Board ID Register\\
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
......@@ -94,7 +94,7 @@ is plugged into the channel or not.
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424C4f (ASCII string \textbf{TBLO})
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......@@ -175,7 +175,7 @@ I2C\_ERR
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ Bit 0 -- CH1 \\ Bit 1 -- CH2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......@@ -1521,11 +1521,10 @@ WRTAG
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
......@@ -1561,6 +1560,15 @@ REAR
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTFS
} [\emph{read-only}]: TTL-BAR no signal detect state
\\
High if no cable is plugged in while in TTL-BAR mode \\
Unused in TTL mode \\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
This diff is collapsed.
......@@ -91,10 +91,8 @@
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{ctb-fw-releases,
title = {{CONV-TTL-BLO firmware releases webpage on OHWR}},
month = jan,
year = {2014},
@misc{ctb-gw-releases,
title = {{CONV-TTL-BLO gateware releases webpage on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/wiki/Releases}}
}
......
......@@ -77,7 +77,7 @@
12-08-2014 & 2.21 & Small error corrections (\textit{writereg} instead of \textit{readreg} in Section~\ref{sec:diag-remote-reset},
and typo in Section~\ref{sec:reprog-bitstreams}), and addition of how to read gateware version in
Section~\ref{sec:reprog-bitstreams} \\
22-08-2014 & 3.00 & Added latest per-channel timestamp readout and line status registers. \newline
26-09-2014 & 3.00 & Added latest per-channel timestamp readout and line status registers. \newline
\textbf{Note: this version changes the memory mapping of various modules} \\
\hline
\end{tabular}
......@@ -143,6 +143,7 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\item converter board ID
\item gateware version
\item unique board ID and temperature readout
\item input line state readout
\item state of on-board switches and RTM detection lines
\item input pulse counters
\item input pulse time-tagging
......@@ -226,7 +227,7 @@ of status LEDs and several ports; these are, from top to bottom:
%--------------------------------------------------------------------------------------
\subsubsection{System status LEDs}
There are twelve bicolor status LEDs on the CONV-TTL-BLO front panel. The implemented
status LEDs are presented in Table \ref{tbl:status-leds}. Unimplemented system status
status LEDs are shown in Table \ref{tbl:status-leds}. Unimplemented system status
LEDs are \textit{off}.
\begin{table}[h]
......@@ -244,7 +245,9 @@ LEDs are \textit{off}.
to the FPGA \\
\textit{ERR} & Error LED \newline
-- \textbf{Red} when a system error occured (see Section~\ref{sec:diag-syserr}) \newline
-- \textbf{Off} otherwise \\
-- \textbf{Off} otherwise \newline
In golden gateware v0.1 (see~\cite{ctb-gw-releases}), this LED lights \textit{red} when
no RTM is plugged in \\
\textit{TTL} & TTL status LED \newline
-- \textbf{Green} when TTL logic is selected via the on-board selection switch \newline
-- \textbf{Off} when TTL-BAR logic is selected. \\
......@@ -279,18 +282,16 @@ as well as the blocking outputs of the same channel on the rear panel, if a CONV
board with an attached CONV-TTL-RTM-BLO is present. Similarly, if a blocking pulse arrives
on the rear panel, it is replicated on the TTL output channel.
\begin{figure}[htbp]
Each TTL replication channel has a pulse LED which flashes shortly whenever a pulse is replicated
on the channel. All TTL input channels are terminated with 50$\Omega$ resistors; TTL output channels are
not terminated.
\begin{figure}[h]
\centerline{\includegraphics[scale=.75]{fig/ttl-chan}}
\caption{Pulse repetition on front channel}
\label{fig:ttl-chan}
\end{figure}
Each TTL replication channel has a pulse LED which flashes shortly whenever a pulse is replicated
on the channel.
All TTL input channels are terminated with 50$\Omega$ resistors; TTL output channels are
not terminated.
%--------------------------------------------------------------------------------------
\subsubsection{General-purpose inverters}
Four general-purpose TTL inverter channels can be found in the lower part of the front panel.
......@@ -923,6 +924,14 @@ the implementation of new blocks. The minor version increments on bug fixes.
\subsection{Unique board ID and temperature readout}
\label{sec:diag-id-therm}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Not implemented in golden gateware versions \\
\hline
\end{tabular}
\vspace*{11pt}
CONV-TTL-BLO boards contain a thermometer chip~\cite{ds18b20} which can be used to read the
board temperature. This thermometer chip is also factory-programmed with a unique
ID which can be used to uniquely identify a CONV-TTL-BLO.
......@@ -1006,6 +1015,14 @@ state in the SR will be a logic '0'.
\subsection{Pulse counters}
\label{sec:diag-pulse-cnt}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Not implemented in golden gateware versions \\
\hline
\end{tabular}
\vspace*{11pt}
One channel is allocated on the input of each counter, after the OR gate preceding
the pulse generator. The input counter logic, which is repeated on each channel,
is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a
......@@ -1025,6 +1042,14 @@ read-write register that can be written at any time via I$^2$C with a user-defin
\subsection{Pulse time-tagging}
\label{sec:diag-pulse-timetag}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Not implemented in golden gateware versions \\
\hline
\end{tabular}
\vspace*{11pt}
The architecture of the time-tagging mechanism is shown in Figure~\ref{fig:timetag-arch}.
\begin{figure}[h]
......@@ -1226,6 +1251,14 @@ here for formatting reasons and to keep to the rules of the Linux command-line.
\subsection{Manual pulse triggering}
\label{sec:diag-man-trig}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Not implemented in golden gateware versions \\
\hline
\end{tabular}
\vspace*{11pt}
It is possible to remotely trigger a pulse on a channel of choice. This feature
should only be used when debugging the connection between two CONV-TTL-BLO boards,
or between a CONV-TTL-BLO and another receiver. This is why manual pulse
......@@ -1280,6 +1313,14 @@ error is reported.
\subsection{System errors}
\label{sec:diag-syserr}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Not implemented in golden gateware versions \textit{older than v0.2} \\
\hline
\end{tabular}
\vspace*{11pt}
Various system errors are defined on converter boards. When such an error occurs,
the ERR LED on the front panel lights up in \textit{red}. At this point, the user
should connect to the converter board (Section~\ref{sec:comm}) to see exactly what
......@@ -1301,7 +1342,7 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
I$^2$C timeout & SR.I2C\_WDTO & An I$^2$C transfer is not completed
within 24~ms (see Section~\ref{sec:comm-timeout}) \\
I$^2$C error & SR.I2C\_ERR & Attempted to access a non-memory-mapped address via I$^2$C \\
Missed pulse & SR.PMISS & Input pulse rejected (see Figure~\ref{fig:pg-op}) \\
Missed pulse & SR.PMISSE & Input pulse rejected (see Figure~\ref{fig:pg-op}) \\
\hline
\end{tabular}
}
......@@ -1313,16 +1354,29 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
\subsection{Line state readout}
\label{sec:diag-line-stat}
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{28pt} Not implemented in gateware versions \textit{older than v3.0} \\
\hline
\end{tabular}
\vspace*{11pt}
The line status register (LSR -- see Appendix~\ref{app:conv-regs-lsr}) contains bits
that show the state of the channel line at the board input. Figure~\ref{fig:line-stat}
shows a diagram of this mapping, from the board input, through the on-board circuitry,
to the LSR.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/line-stat}}
\centerline{\includegraphics[width=.95\textwidth]{fig/line-stat}}
\caption{\label{fig:line-stat} Readout of line state at board input}
\end{figure}
Note that while in TTL-BAR repetition mode, the state \textit{no signal detect} block
(see Section~\ref{sec:pulse-rep}) is reflected in the LSR, effectively showing if a
cable is plugged in or not. While in TTL repetition mode, the FRONTFS bits in the LSR
are unused.
%==============================================================================
% SEC: Remote reprog
%==============================================================================
......@@ -1684,7 +1738,7 @@ The inverter channel will add a 30~ns delay to the input TTL signal.
Note that this appendix contains the memory map for the latest gateware
version. For different gateware versions, the memory map may be different. To get
the memory map for a specific gateware version, see the HDL guide for the corresponding
gateware version at~\cite{ctb-hdlguide}.
gateware version at~\cite{ctb-gw-releases}.
Table~\ref{tbl:memmap} shows the complete memory map of the gateware. The
following sections list the memory map of each peripheral.
......
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