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C
Conv TTL Blocking
Commit 305fc989 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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I2C works. Merging with master branch and deleting current

parent 722c523e
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Showing with 372 additions and 153 deletions
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 305fc989
......@@ -984,3 +984,99 @@ NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[31]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[30]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[29]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[28]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[27]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[26]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[25]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[24]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[23]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[22]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[21]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[20]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[19]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[18]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[17]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[16]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[15]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[14]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[13]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[12]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[11]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[10]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[9]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[8]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[31]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[30]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[29]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[28]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[27]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[26]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[25]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[24]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[23]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[22]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[21]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[20]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[19]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[18]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[17]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[16]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[15]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[14]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[13]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[12]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[11]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[10]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[9]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[8]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[1]" KEEP = "TRUE";
hdl/IMAGES/image1/project/image1.gise
View file @ 305fc989
......@@ -64,45 +64,177 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="image1_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_par.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="image1_top_summary.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top_tb.fdo"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="image1_top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356477" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356477" xil_pn:in_ck="-7743529667590320445" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1361356477" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361356477" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356477" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356477" xil_pn:in_ck="-7743529667590320445" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1361356478" xil_pn:in_ck="-7743529667590320445" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-8746751989006931633" xil_pn:start_ts="1361356477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="image1_top_tb.fdo"/>
<outfile xil_pn:name="vsim.wlf"/>
<outfile xil_pn:name="work"/>
</transform>
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295362" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1361295362">
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295887" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-7054792210038822793" xil_pn:start_ts="1361295871">
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361356662" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1361356662">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361358222" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1361358205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -120,11 +252,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1361295378" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361295378">
<transform xil_pn:end_ts="1361356680" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1361356680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1361295893" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361295887">
<transform xil_pn:end_ts="1361358228" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361358222">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -134,11 +266,9 @@
<outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361295927" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361295893">
<transform xil_pn:end_ts="1361358262" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1361358228">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="image1_top.pcf"/>
<outfile xil_pn:name="image1_top_map.map"/>
......@@ -149,7 +279,7 @@
<outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1361295960" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361295927">
<transform xil_pn:end_ts="1361358295" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361358262">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -164,7 +294,7 @@
<outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1361295979" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361295960">
<transform xil_pn:end_ts="1361358314" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361358295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -175,15 +305,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1361295980" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361295979">
<transform xil_pn:end_ts="1361358314" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361358314">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1361295960" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361295953">
<transform xil_pn:end_ts="1361358295" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361358287">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/IMAGES/image1/project/image1.xise
View file @ 305fc989
......@@ -321,7 +321,7 @@
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 305fc989
......@@ -124,6 +124,7 @@ type SLA_fsm is (R0_RESET,
constant c_WATCHDOG_END_VALUE : NATURAL := c_WATCHDOG_DEADLINE/g_WB_CLK_PERIOD;
signal i2c_SLA_fsm : SLA_fsm := R0_RESET;
signal i2c_SLA_fsm_d0 : SLA_fsm := R0_RESET;
signal s_DRXA_slv : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0)
......@@ -150,12 +151,12 @@ signal s_bit_done : STD_LOGIC;
-- Bit counter signals
signal s_bit_cnt_slv : STD_LOGIC_VECTOR(c_COUNTER_WIDTH - 1 downto 0);
signal s_bit_cnt : NATURAL;
signal s_bit_cnt : unsigned(7 downto 0);
signal s_bit_cnt_rst : STD_LOGIC;
-- Byte counter signals
signal s_byte_cnt_slv : STD_LOGIC_VECTOR(c_COUNTER_WIDTH - 1 downto 0);
signal s_byte_cnt : NATURAL;
signal s_byte_cnt : unsigned(7 downto 0);
signal s_byte_cnt_rst : STD_LOGIC;
signal s_byte_cnt_en : STD_LOGIC := '0';
......@@ -175,123 +176,121 @@ signal txsr : std_logic_vector(31 downto 0);
begin
s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
inst_i2c_bit : i2c_bit
port map(rst_i => rst_i,
wb_clk_i => clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => s_start_o,
pause_o => s_pause_o,
rcved_o => s_rcved_o,
done_o => s_bit_done);
bit_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
port map (clk_i => clk_i,
rst_i => s_bit_cnt_rst,
en_i => s_bit_done,
cnt_o => s_bit_cnt_slv);
s_bit_cnt <= to_integer(UNSIGNED(s_bit_cnt_slv));
byte_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
port map (clk_i => clk_i,
rst_i => s_byte_cnt_rst,
en_i => s_byte_cnt_en,
cnt_o => s_byte_cnt_slv);
s_byte_cnt <= to_integer(UNSIGNED(s_byte_cnt_slv));
watchdog_counter_8: gc_counter
generic map (g_data_width => c_WATCHDOG_WIDTH)
port map (clk_i => clk_i,
rst_i => s_watchdog_cnt_rst,
en_i => c_WATCHDOG_ENABLE,
cnt_o => s_watchdog_cnt_slv);
s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv));
scl_o <= '1';
scl_oen <= '0';
sda_o <= s_sda_o;
-- Process to control the TX shift register
-- p_txsr: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- txsr <= (others => '0');
-- elsif (i2c_sla_fsm = S5W1A_I2C_ADDR_ACK) then
-- txsr <= f_ch_endian(pf_wb_data_i);
-- elsif (i2c_sla_fsm = S5W2_WRITE_SDA) then
-- txsr <= txsr(30 downto 0) & '0';
-- end if;
-- end if;
-- end process p_txsr;
p_sda_o: process(i2c_SLA_fsm, txsr)
-- variable v_bit_inv : UNSIGNED(2 downto 0);
-- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0);
variable v_pf_wb_data : STD_LOGIC_VECTOR(0 to 31);
-- variable v_pf_wb_data : std_logic_vector(31 downto 0);
begin
case i2c_SLA_fsm is
when S2A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_o <= '0';
when S5RA_READ_SDA_ACK =>
s_sda_o <= '0';
when S5W1A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S5W2_WRITE_SDA =>
-- v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(2 downto 0)));
-- v_bit_order := to_integer(v_bit_inv);
-- s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
-- v_pf_wb_data(0 to 31) := f_ch_endian(s_pf_wb_data(31 downto 0));
-- -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
-- s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
s_sda_o <= txsr(31);
when others =>
s_sda_o <= '1';
end case;
end process;
sda_oen <= s_sda_oen;
s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
inst_i2c_bit : i2c_bit
port map(rst_i => rst_i,
wb_clk_i => clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => s_start_o,
pause_o => s_pause_o,
rcved_o => s_rcved_o,
done_o => s_bit_done);
bit_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
port map (clk_i => clk_i,
rst_i => s_bit_cnt_rst,
en_i => s_bit_done,
cnt_o => s_bit_cnt_slv);
s_bit_cnt <= unsigned(s_bit_cnt_slv);
byte_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
port map (clk_i => clk_i,
rst_i => s_byte_cnt_rst,
en_i => s_byte_cnt_en,
cnt_o => s_byte_cnt_slv);
s_byte_cnt <= unsigned(s_byte_cnt_slv);
watchdog_counter_8: gc_counter
generic map (g_data_width => c_WATCHDOG_WIDTH)
port map (clk_i => clk_i,
rst_i => s_watchdog_cnt_rst,
en_i => c_WATCHDOG_ENABLE,
cnt_o => s_watchdog_cnt_slv);
s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv));
scl_o <= '1';
scl_oen <= '0';
sda_o <= s_sda_o;
-- Process to control the TX shift register
-- p_txsr: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- txsr <= (others => '0');
-- elsif (i2c_sla_fsm = S5W1A_I2C_ADDR_ACK) then
-- txsr <= f_ch_endian(pf_wb_data_i);
-- elsif (i2c_sla_fsm = S5W2_WRITE_SDA) then
-- txsr <= txsr(30 downto 0) & '0';
-- end if;
-- end if;
-- end process p_txsr;
p_sda_o: process(i2c_SLA_fsm, txsr)
-- variable v_bit_inv : UNSIGNED(s_ctr0.bia downto 0);
-- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0);
variable v_pf_wb_data : STD_LOGIC_VECTOR(0 to 31);
-- variable v_pf_wb_data : std_logic_vector(31 downto 0);
begin
case i2c_SLA_fsm is
when S2A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_o <= '0';
when S5RA_READ_SDA_ACK =>
s_sda_o <= '0';
when S5W1A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S5W2_WRITE_SDA =>
-- v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(s_ctr0.bia downto 0)));
-- v_bit_order := to_integer(v_bit_inv);
-- s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
-- v_pf_wb_data(0 to 31) := f_ch_endian(s_pf_wb_data(31 downto 0));
-- -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
-- s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
s_sda_o <= txsr(31);
when others =>
s_sda_o <= '1';
end case;
end process;
sda_oen <= s_sda_oen;
p_sda_oen: process(i2c_SLA_fsm)
begin
s_sda_oen <= '0';
case i2c_SLA_fsm is
when S2A_I2C_ADDR_ACK =>
s_sda_oen <= '1';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_oen <= '1';
when S5RA_READ_SDA_ACK =>
s_sda_oen <= '1';
when S5W1A_I2C_ADDR_ACK =>
s_sda_oen <= '1';
when S5W2_WRITE_SDA =>
s_sda_oen <= '1';
when others =>
null;
end case;
s_sda_oen <= '0';
case i2c_SLA_fsm is
when S2A_I2C_ADDR_ACK =>
s_sda_oen <= '1';
when S3A_WISHBONE_ADDR_ACK =>
s_sda_oen <= '1';
when S5RA_READ_SDA_ACK =>
s_sda_oen <= '1';
when S5W1A_I2C_ADDR_ACK =>
s_sda_oen <= '1';
when S5W2_WRITE_SDA =>
s_sda_oen <= '1';
when others =>
null;
end case;
end process;
s_DRXA_slv <= s_DRX_slv(r_DRX'a_length - 1 downto 0);
......@@ -397,11 +396,10 @@ begin
--! @param i2c_SLA_fsm_d0 Current value of the i2c fsm
p_bit_counter_comb : process(i2c_SLA_fsm,
i2c_SLA_fsm_d0,
s_byte_cnt,
s_CTR0.BIA)
s_byte_cnt)
begin
s_bit_cnt_rst <= '0';
s_byte_cnt_rst <= '0';
s_bit_cnt_rst <= '0';
s_byte_cnt_rst <= '0';
case i2c_SLA_fsm is
when R0_RESET =>
if i2c_SLA_fsm_d0 /= R0_RESET then
......@@ -425,7 +423,7 @@ begin
or i2c_SLA_fsm_d0 = S5W1A_I2C_ADDR_ACK then
s_bit_cnt_rst <= '1';
end if;
if s_byte_cnt = s_CTR0.BIA then
if s_byte_cnt = s_ctr0.bia then
if i2c_SLA_fsm_d0 = S2A_I2C_ADDR_ACK then
s_byte_cnt_rst <= '1';
end if;
......@@ -456,7 +454,7 @@ begin
s_bit_cnt_rst <= '1';
end if;
when S5R_READ_SDA =>
if s_byte_cnt = s_CTR0.BIA then
if s_byte_cnt = s_ctr0.bia then
if i2c_SLA_fsm_d0 = S3A_WISHBONE_ADDR_ACK then
s_byte_cnt_rst <= '1';
end if;
......@@ -476,14 +474,11 @@ begin
when S7_PAUSE_DETECT =>
null;
when others =>
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
null;
end case;
end process;
p_byte_counter_en: process (i2c_SLA_fsm,
i2c_SLA_fsm_d0,
s_CTR0.BIA)
p_byte_counter_en: process (i2c_SLA_fsm, i2c_SLA_fsm_d0)
begin
s_byte_cnt_en <= '0';
case i2c_SLA_fsm is
......@@ -610,7 +605,7 @@ begin
end if;
when S3A_WISHBONE_ADDR_ACK =>
if s_bit_done = '1' then
if s_byte_cnt < s_CTR0.BIA then
if s_byte_cnt < s_ctr0.bia then
i2c_SLA_fsm <= S3_WISHBONE_ADDR;
else
i2c_SLA_fsm <= S4_DETECT_OPERATION;
......@@ -636,7 +631,7 @@ begin
end if;
when S5RA_READ_SDA_ACK =>
if s_bit_done = '1' then
if s_byte_cnt < s_CTR0.BRD then
if s_byte_cnt < s_ctr0.brd then
i2c_SLA_fsm <= S5R_READ_SDA;
else
i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
......@@ -678,7 +673,7 @@ begin
when S5W2A_WRITE_SDA_ACK =>
if s_bit_done = '1' then
if s_rcved_o = '0' then
if s_byte_cnt < s_CTR0.BWR then
if s_byte_cnt < s_ctr0.bwr then
i2c_SLA_fsm <= S5W2_WRITE_SDA;
else
i2c_SLA_fsm <= R0_RESET;
......
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