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Conv TTL Blocking
Commit 305fc989 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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I2C works. Merging with master branch and deleting current

parent 722c523e
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Showing with 372 additions and 153 deletions
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 305fc989
......@@ -984,3 +984,99 @@ NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_bit_cnt_slv[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_byte_cnt_slv[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[31]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[30]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[29]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[28]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[27]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[26]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[25]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[24]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[23]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[22]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[21]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[20]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[19]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[18]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[17]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[16]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[15]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[14]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[13]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[12]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[11]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[10]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[9]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[8]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/txsr[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[31]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[30]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[29]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[28]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[27]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[26]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[25]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[24]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[23]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[22]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[21]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[20]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[19]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[18]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[17]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[16]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[15]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[14]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[13]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[12]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[11]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[10]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[9]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[8]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[6]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/s_CTR0_slv[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[1]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm_d0[0]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[7]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[5]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[4]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[3]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[2]" KEEP = "TRUE";
#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/CTR0_i[1]" KEEP = "TRUE";
hdl/IMAGES/image1/project/image1.gise
View file @ 305fc989
This diff is collapsed.
hdl/IMAGES/image1/project/image1.xise
View file @ 305fc989
......@@ -321,7 +321,7 @@
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 305fc989
......@@ -124,6 +124,7 @@ type SLA_fsm is (R0_RESET,
constant c_WATCHDOG_END_VALUE : NATURAL := c_WATCHDOG_DEADLINE/g_WB_CLK_PERIOD;
signal i2c_SLA_fsm : SLA_fsm := R0_RESET;
signal i2c_SLA_fsm_d0 : SLA_fsm := R0_RESET;
signal s_DRXA_slv : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0)
......@@ -150,12 +151,12 @@ signal s_bit_done : STD_LOGIC;
-- Bit counter signals
signal s_bit_cnt_slv : STD_LOGIC_VECTOR(c_COUNTER_WIDTH - 1 downto 0);
signal s_bit_cnt : NATURAL;
signal s_bit_cnt : unsigned(7 downto 0);
signal s_bit_cnt_rst : STD_LOGIC;
-- Byte counter signals
signal s_byte_cnt_slv : STD_LOGIC_VECTOR(c_COUNTER_WIDTH - 1 downto 0);
signal s_byte_cnt : NATURAL;
signal s_byte_cnt : unsigned(7 downto 0);
signal s_byte_cnt_rst : STD_LOGIC;
signal s_byte_cnt_en : STD_LOGIC := '0';
......@@ -197,7 +198,7 @@ begin
en_i => s_bit_done,
cnt_o => s_bit_cnt_slv);
s_bit_cnt <= to_integer(UNSIGNED(s_bit_cnt_slv));
s_bit_cnt <= unsigned(s_bit_cnt_slv);
byte_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
......@@ -206,7 +207,7 @@ begin
en_i => s_byte_cnt_en,
cnt_o => s_byte_cnt_slv);
s_byte_cnt <= to_integer(UNSIGNED(s_byte_cnt_slv));
s_byte_cnt <= unsigned(s_byte_cnt_slv);
watchdog_counter_8: gc_counter
generic map (g_data_width => c_WATCHDOG_WIDTH)
......@@ -217,34 +218,32 @@ begin
s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv));
scl_o <= '1';
scl_oen <= '0';
sda_o <= s_sda_o;
-- Process to control the TX shift register
-- p_txsr: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- txsr <= (others => '0');
-- elsif (i2c_sla_fsm = S5W1A_I2C_ADDR_ACK) then
-- txsr <= f_ch_endian(pf_wb_data_i);
-- elsif (i2c_sla_fsm = S5W2_WRITE_SDA) then
-- txsr <= txsr(30 downto 0) & '0';
-- end if;
-- end if;
-- end process p_txsr;
-- p_txsr: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- txsr <= (others => '0');
-- elsif (i2c_sla_fsm = S5W1A_I2C_ADDR_ACK) then
-- txsr <= f_ch_endian(pf_wb_data_i);
-- elsif (i2c_sla_fsm = S5W2_WRITE_SDA) then
-- txsr <= txsr(30 downto 0) & '0';
-- end if;
-- end if;
-- end process p_txsr;
p_sda_o: process(i2c_SLA_fsm, txsr)
-- variable v_bit_inv : UNSIGNED(2 downto 0);
-- variable v_bit_order : NATURAL;
-- variable v_bit_inv : UNSIGNED(s_ctr0.bia downto 0);
-- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0);
variable v_pf_wb_data : STD_LOGIC_VECTOR(0 to 31);
-- variable v_pf_wb_data : std_logic_vector(31 downto 0);
-- variable v_pf_wb_data : std_logic_vector(31 downto 0);
begin
case i2c_SLA_fsm is
......@@ -257,15 +256,15 @@ begin
when S5W1A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S5W2_WRITE_SDA =>
-- v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(2 downto 0)));
-- v_bit_order := to_integer(v_bit_inv);
-- s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
-- v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(s_ctr0.bia downto 0)));
-- v_bit_order := to_integer(v_bit_inv);
-- s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
-- v_pf_wb_data(0 to 31) := f_ch_endian(s_pf_wb_data(31 downto 0));
-- -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
-- s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
-- v_pf_wb_data(0 to 31) := f_ch_endian(s_pf_wb_data(31 downto 0));
-- -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
-- s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
s_sda_o <= txsr(31);
when others =>
......@@ -397,8 +396,7 @@ begin
--! @param i2c_SLA_fsm_d0 Current value of the i2c fsm
p_bit_counter_comb : process(i2c_SLA_fsm,
i2c_SLA_fsm_d0,
s_byte_cnt,
s_CTR0.BIA)
s_byte_cnt)
begin
s_bit_cnt_rst <= '0';
s_byte_cnt_rst <= '0';
......@@ -425,7 +423,7 @@ begin
or i2c_SLA_fsm_d0 = S5W1A_I2C_ADDR_ACK then
s_bit_cnt_rst <= '1';
end if;
if s_byte_cnt = s_CTR0.BIA then
if s_byte_cnt = s_ctr0.bia then
if i2c_SLA_fsm_d0 = S2A_I2C_ADDR_ACK then
s_byte_cnt_rst <= '1';
end if;
......@@ -456,7 +454,7 @@ begin
s_bit_cnt_rst <= '1';
end if;
when S5R_READ_SDA =>
if s_byte_cnt = s_CTR0.BIA then
if s_byte_cnt = s_ctr0.bia then
if i2c_SLA_fsm_d0 = S3A_WISHBONE_ADDR_ACK then
s_byte_cnt_rst <= '1';
end if;
......@@ -476,14 +474,11 @@ begin
when S7_PAUSE_DETECT =>
null;
when others =>
s_bit_cnt_rst <= '1';
s_byte_cnt_rst <= '1';
null;
end case;
end process;
p_byte_counter_en: process (i2c_SLA_fsm,
i2c_SLA_fsm_d0,
s_CTR0.BIA)
p_byte_counter_en: process (i2c_SLA_fsm, i2c_SLA_fsm_d0)
begin
s_byte_cnt_en <= '0';
case i2c_SLA_fsm is
......@@ -610,7 +605,7 @@ begin
end if;
when S3A_WISHBONE_ADDR_ACK =>
if s_bit_done = '1' then
if s_byte_cnt < s_CTR0.BIA then
if s_byte_cnt < s_ctr0.bia then
i2c_SLA_fsm <= S3_WISHBONE_ADDR;
else
i2c_SLA_fsm <= S4_DETECT_OPERATION;
......@@ -636,7 +631,7 @@ begin
end if;
when S5RA_READ_SDA_ACK =>
if s_bit_done = '1' then
if s_byte_cnt < s_CTR0.BRD then
if s_byte_cnt < s_ctr0.brd then
i2c_SLA_fsm <= S5R_READ_SDA;
else
i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
......@@ -678,7 +673,7 @@ begin
when S5W2A_WRITE_SDA_ACK =>
if s_bit_done = '1' then
if s_rcved_o = '0' then
if s_byte_cnt < s_CTR0.BWR then
if s_byte_cnt < s_ctr0.bwr then
i2c_SLA_fsm <= S5W2_WRITE_SDA;
else
i2c_SLA_fsm <= R0_RESET;
......
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