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Conv TTL Blocking
Commit 357142a3 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Various changes due to change in memory map

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doc/ug/multiboot-regs.tex
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\subsection{MultiBoot controller}
\label{app:multiboot-regs}
Base address: 0x040
Base address: 0x100
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
......
doc/ug/ug-conv-ttl-blo.tex
View file @ 357142a3
......@@ -69,7 +69,6 @@
06-03-2014 & 2.00 & Added support for diagnostics \\
08-04-2014 & 2.10 & Changed max. pulse repetition frequency, replaced the timetag FIFO for a
ring buffer \\
15-04-2014 & 2.11 & Updated Section~\ref{sec:reprog-fwstat} \\
11-08-2014 & 2.20 & Various to make the document clearer. Made description in Table~\ref{tbl:syserr}
more concise; moved Figure~\ref{fig:sr-switches} from Section~\ref{sec:switches}
to Section~\ref{sec:diag-sw-rtmdet}; made slight modifications to Figure~\ref{fig:man-trig-fsm}
......@@ -78,7 +77,8 @@
12-08-2014 & 2.21 & Small error corrections (\textit{writereg} instead of \textit{readreg} in Section~\ref{sec:diag-remote-reset},
and typo in Section~\ref{sec:reprog-bitstreams}), and addition of how to read gateware version in
Section~\ref{sec:reprog-bitstreams} \\
22-08-2014 & 3.00 & Changed memory map, adding latest per-channel timestamp readout and line status registers \\
22-08-2014 & 3.00 & Added latest per-channel timestamp readout and line status registers. \newline
\textbf{Note: this version changes the memory mapping of various modules} \\
\hline
\end{tabular}
}
......@@ -1443,7 +1443,7 @@ board's status register (SR -- see Appendix~\ref{app:conv-regs-sr}).
%--------------------------------------------------------------------------------------
% SUBSEC: Don't program bitstreams w/o the ICAP
% SUBSEC: Flash memmap
%--------------------------------------------------------------------------------------
\subsection{Flash memory map}
\label{sec:reprog-flash-memmap}
......@@ -1517,16 +1517,6 @@ MultiBoot-enabled design.
%than the Golden bitstream, always make sure the MultiBoot module is included in any bitstream
%generated after the Golden bitstream.
%--------------------------------------------------------------------------------------
% SUBSEC: Status on reception
%--------------------------------------------------------------------------------------
\subsection{Gateware status on reception}
\label{sec:reprog-fwstat}
CONV-TTL-BLO boards arrive with the Header and Golden bitstreams, along with bitstream
version 2.2 (see the bitstream releases webpage~\cite{ctb-fw-releases} for more details)
programmed into the flash.
%======================================================================================
% SEC: Proj repo
%======================================================================================
......@@ -1691,6 +1681,11 @@ The inverter channel will add a 30~ns delay to the input TTL signal.
\section{Memory map}
\label{app:memmap}
Note that this appendix contains the memory map for the latest gateware
version. For different gateware versions, the memory map may be different. To get
the memory map for a specific gateware version, see the HDL guide for the corresponding
gateware version at~\cite{ctb-hdlguide}.
Table~\ref{tbl:memmap} shows the complete memory map of the gateware. The
following sections list the memory map of each peripheral.
......@@ -1736,7 +1731,7 @@ $reg. index = \frac{addr}{4} + 1$
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x080
\indent Base address: 0x200
\vspace*{11pt}
......
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