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Commit 35e55b98 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Adding testbench for the multiboot. Structure sketched. TODO: Implement verification of fsms.

parent a63e5773
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hdl/multiboot/rtl/multiboot_core.vhd
View file @ 35e55b98
......@@ -158,6 +158,7 @@ begin
s_CTR1.OP_ACK <= c_CTR1_default.OP_ACK;
s_CTR1.FSM_RUN <= c_CTR1_default.FSM_RUN;
s_CTR1.BAD_OP <= c_CTR1_default.BAD_OP;
s_CTR1.x <= c_CTR1_default.x;
--! Watchout! CTR1 is one-clock delayed
case s_ICAP_fsm is
when R0_RESET =>
......@@ -270,8 +271,7 @@ begin
--! @brief Input port update process for the ICAP primitive
--! @param s_multiboot_fsm subfsm of the multiboot
--! @param s_readback_fsm subfsm of the readback
p_ICAP_write_port: process(s_multiboot_fsm,
s_readback_fsm)
p_ICAP_write_port: process(s_ICAP_fsm)
begin
s_icap_i <= NULL_value;
case s_ICAP_fsm is
......@@ -402,7 +402,7 @@ begin
when S10A_NOOP =>
s_readback_fsm <= S11A_FETCH_REG;
when S11A_FETCH_REG =>
if s_rd_ICAP_regA = STD_LOGIC_VECTOR(OP_RD_STAT) then
if s_rd_ICAP_regA = STD_LOGIC_VECTOR(CMD_rd_STAT) then
s_readback_fsm <= S12_WRITE_CMD;
else
s_readback_fsm <= S6B_READ_CMD;
......
hdl/multiboot/rtl/multiboot_pkg.vhd
View file @ 35e55b98
......@@ -5,6 +5,9 @@ use IEEE.NUMERIC_STD.ALL;
package multiboot_pkg is
constant c_MBA_map_addr : STD_LOGIC_VECTOR (23 downto 0) := X"020000";
constant c_GBA_map_addr : STD_LOGIC_VECTOR (23 downto 0) := X"C0FFE5";
----------------------------------------------------------------------------
-- ICAP configuration data codes
----------------------------------------------------------------------------
......@@ -217,6 +220,8 @@ package multiboot_pkg is
function f_STD_LOGIC_VECTOR (r_register : r_BAR) return STD_LOGIC_VECTOR;
component multiboot_regs is
generic(g_MBA_addr : UNSIGNED(23 downto 0);
g_GBA_addr : UNSIGNED(23 downto 0));
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
......
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ 35e55b98
......@@ -28,6 +28,8 @@ use IEEE.NUMERIC_STD.ALL;
use work.multiboot_pkg.ALL;
entity multiboot_regs is
generic(g_MBA_addr : UNSIGNED(23 downto 0);
g_GBA_addr : UNSIGNED(23 downto 0));
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
......@@ -52,18 +54,20 @@ end multiboot_regs;
architecture Behavioral of multiboot_regs is
signal s_CTR0 : r_CTR0 := c_CTR0_default;
signal s_CTR1 : r_CTR1;
signal s_STAT : r_STAT;
signal s_CTR0 : r_CTR0 := c_CTR0_default;
signal s_CTR1 : r_CTR1;
signal s_STAT : r_STAT;
signal s_MBA : r_BAR := c_BAR_default;
signal s_GBA : r_BAR := c_BAR_default;
signal s_MBA_ICAP : STD_LOGIC_VECTOR(23 downto 0);
signal s_GBA_ICAP : STD_LOGIC_VECTOR(23 downto 0);
signal s_MBA : r_BAR := c_BAR_default;
signal s_GBA : r_BAR := c_BAR_default;
signal s_MBA_ICAP : STD_LOGIC_VECTOR(23 downto 0);
signal s_GBA_ICAP : STD_LOGIC_VECTOR(23 downto 0);
signal s_wb_ack : STD_LOGIC := '0';
signal s_wb_rty : STD_LOGIC := '0';
signal s_wb_err : STD_LOGIC := '0';
signal s_wb_data_i : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal s_wb_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal s_wb_ack : STD_LOGIC := '0';
signal s_wb_rty : STD_LOGIC := '0';
signal s_wb_err : STD_LOGIC := '0';
begin
......@@ -76,6 +80,24 @@ begin
s_MBA_ICAP <= MBA_ICAP_i;
s_GBA_ICAP <= GBA_ICAP_i;
process (wb_sel_i,
wb_data_i,
s_wb_data_o)
begin
for i in 0 to 3 loop
if wb_sel_i(i) = '1' then
s_wb_data_i(8*(i+1) - 1 downto 8*i) <=
wb_data_i(8*(i+1) - 1 downto 8*i);
wb_data_o(8*(i+1) - 1 downto 8*i) <=
s_wb_data_o(8*(i+1) - 1 downto 8*i);
else
s_wb_data_i(8*(i+1) - 1 downto 8*i) <= (others => '0');
wb_data_o(8*(i+1) - 1 downto 8*i) <= (others => '0');
end if;
end loop;
end process;
wb_ack_o <= s_wb_ack;
wb_rty_o <= s_wb_rty;
wb_err_o <= s_wb_err;
......@@ -86,11 +108,11 @@ begin
if rising_edge(wb_clk) then
v_wb_addr := UNSIGNED(wb_addr_i);
if wb_rst_i = '1' then
wb_data_o <= (others => '0');
s_CTR0 <= c_CTR0_default;
s_wb_data_o <= (others => '0');
s_wb_ack <= '0';
s_wb_rty <= '0';
s_wb_err <= '0';
wb_data_o <= (others => '0');
else
if (wb_stb_i = '1' and wb_cyc_i = '1')
and s_wb_ack = '0'
......@@ -103,27 +125,27 @@ begin
when '0' =>
case v_wb_addr is
when CTR0_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
s_wb_ack <= '1';
when CTR1_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR1);
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR1);
s_wb_ack <= '1';
when STAT_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_STAT);
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_STAT);
s_wb_ack <= '1';
when c_MBA_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_MBA);
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_MBA);
s_wb_ack <= '1';
when c_GBA_addr =>
wb_data_o <= f_STD_LOGIC_VECTOR(s_GBA);
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_GBA);
s_wb_ack <= '1';
when c_MBA_ICAP_addr =>
wb_data_o (31 downto 24) <= (others => '0');
wb_data_o (23 downto 0) <= s_MBA_ICAP;
s_wb_data_o (31 downto 24) <= (others => '0');
s_wb_data_o (23 downto 0) <= s_MBA_ICAP;
s_wb_ack <= '1';
when c_GBA_ICAP_addr =>
wb_data_o (31 downto 24) <= (others => '0');
wb_data_o (23 downto 0) <= s_GBA_ICAP;
s_wb_data_o (31 downto 24) <= (others => '0');
s_wb_data_o (23 downto 0) <= s_GBA_ICAP;
s_wb_ack <= '1';
when others =>
s_wb_err <= '1';
......@@ -131,13 +153,13 @@ begin
when others =>
case v_wb_addr is
when CTR0_addr =>
s_CTR0 <= f_CTR0(wb_data_i);
s_CTR0 <= f_CTR0(s_wb_data_i);
s_wb_ack <= '1';
when c_MBA_addr =>
s_MBA <= f_BAR(wb_data_i);
s_MBA <= f_BAR(s_wb_data_i);
s_wb_ack <= '1';
when c_GBA_addr =>
s_GBA <= f_BAR(wb_data_i);
s_GBA <= f_BAR(s_wb_data_i);
s_wb_ack <= '1';
when others =>
s_wb_err <= '1';
......
hdl/multiboot/rtl/multiboot_top.vhd
View file @ 35e55b98
......@@ -2,22 +2,25 @@ library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.multiboot_pkg.ALL;
entity multiboot_top is
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr));
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end multiboot_top;
......@@ -34,6 +37,8 @@ signal s_GBA_addr : STD_LOGIC_VECTOR(23 downto 0);
begin
multiboot_regs_inst : multiboot_regs
generic map (g_MBA_addr => g_MBA_addr,
g_GBA_addr => g_GBA_addr)
port map(wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
......
hdl/multiboot/test/multiboot_pkg_tb.vhd 0 → 100644
View file @ 35e55b98
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use work.multiboot_pkg.ALL;
package multiboot_pkg_tb is
constant c_WB_CLK_PERIOD : TIME := 50 ns;
file file_handler : TEXT;
constant c_LOG_PATH : STRING := "../test/log/multiboot_top_tb.log";
constant sep : CHARACTER := ht;
-- Component Declaration
component multiboot_top is
generic(g_MBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_MBA_map_addr);
g_GBA_addr : UNSIGNED (23 downto 0) := UNSIGNED(c_GBA_map_addr));
port(
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC);
end component;
end multiboot_pkg_tb;
package body multiboot_pkg_tb is
end multiboot_pkg_tb;
hdl/multiboot/test/multiboot_top_tb.vhd
View file @ 35e55b98
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