Commit 392ea33d authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Change folder structure

- renamed 'test/' folder to 'software/'
- cleaned up old unnecessary files
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent e3df1443
captures/
sw/
*.bak
conv-ttl-blo-gw @ f68e5997
Subproject commit ba05fd962724d11efdcf685078f37fbd30c4c3ee
Subproject commit f68e5997c501baf06fa0cbdb680589c84ea5d502
# PROMGEN: Xilinx Prom Generator O.76xd
# Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
SOFTWARE_VERSION O.76xd
DATE 11/21/2012 - 12: 5
SOURCE /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.mcs
DEVICE 4096K
DATA_WIDTH 1
FILL_DATA 0xFF
SIGNATURE 0x2946E582
START_ADDRESS 0x00000000 END_ADDRESS 0x0016A673 DIRECTION_UP "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.bit" 6slx45tfgg484
PROMGEN: Xilinx Prom Generator O.76xd
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
promgen -w -p mcs -c FF -o /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream//basic_trigger_top -s 4096 -u 0000 /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.bit -spi
PROM /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.prm map: Wed Nov 21 12:05:59 2012
Calculating PROM checksum with fill value ff
Format Mcs86 (32-bit)
Size 4096K
PROM start 0000:0000
PROM end 003f:ffff
PROM checksum 2946e582
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Nov 21 11:51:58 2012 /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.bit
This diff is collapsed.
Release 13.3 - Bitgen O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/opt/Xilinx/13.3/ISE_DS/ISE/.
"basic_trigger_top" is an NCD, version 3.2, device xc6slx45t, package fgg484,
speed -3
/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.ngc 1353494996
OK
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 13.3 - Bitgen O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/opt/Xilinx/13.3/ISE_DS/ISE/.
"basic_trigger_top" is an NCD, version 3.2, device xc6slx45t, package fgg484,
speed -3
Opened constraints file basic_trigger_top.pcf.
Wed Nov 21 11:51:28 2012
/opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:10 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullUp -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 basic_trigger_top.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 10 |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pullup |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| MaskVectorFile | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from basic_trigger_top.pcf.
Running DRC.
DRC detected 0 errors and 0 warnings.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "basic_trigger_top.bit".
Bitstream generation is complete.
Release 13.3 ngdbuild O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -uc
/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/F
PGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
Reading NGO file
"/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basi
c_trigger_top.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file
"/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/
FPGAbank.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 107076 kilobytes
Writing NGD file "basic_trigger_top.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "basic_trigger_top.bld"...
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/basic_trigger_top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc constraints/FPGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd basic_trigger_top.pcf
par -w -intstyle ise -ol high -mt off basic_trigger_top_map.ncd basic_trigger_top.ncd basic_trigger_top.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_top.twx basic_trigger_top.ncd -o basic_trigger_top.twr basic_trigger_top.pcf
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.syr"
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/FPGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd basic_trigger_top.pcf
par -w -intstyle ise -ol high -mt off basic_trigger_top_map.ncd basic_trigger_top.ncd basic_trigger_top.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_top.twx basic_trigger_top.ncd -o basic_trigger_top.twr basic_trigger_top.pcf
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/FPGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd basic_trigger_top.pcf
par -w -intstyle ise -ol high -mt off basic_trigger_top_map.ncd basic_trigger_top.ncd basic_trigger_top.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_top.twx basic_trigger_top.ncd -o basic_trigger_top.twr basic_trigger_top.pcf
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
Release 13.3 Drc O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 21 11:51:28 2012
drc -z basic_trigger_top.ncd basic_trigger_top.pcf
DRC detected 0 errors and 0 warnings.
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
//! **************************************************************************
// Written by: Map O.76xd on Wed Nov 21 11:50:22 2012
//! **************************************************************************
SCHEMATIC START;
COMP "fpga_o_blo_en" LOCATE = SITE "N3" LEVEL 1;
COMP "fpga_o_inv_en" LOCATE = SITE "P3" LEVEL 1;
COMP "fpga_o_en" LOCATE = SITE "N4" LEVEL 1;
COMP "led_err_o" LOCATE = SITE "F9" LEVEL 1;
COMP "pulse_i_rear<1>" LOCATE = SITE "W18" LEVEL 1;
COMP "pulse_i_rear<2>" LOCATE = SITE "Y18" LEVEL 1;
COMP "pulse_i_rear<3>" LOCATE = SITE "W17" LEVEL 1;
COMP "pulse_i_rear<4>" LOCATE = SITE "Y17" LEVEL 1;
COMP "pulse_i_rear<5>" LOCATE = SITE "Y16" LEVEL 1;
COMP "pulse_i_rear<6>" LOCATE = SITE "Y15" LEVEL 1;
COMP "level" LOCATE = SITE "L22" LEVEL 1;
COMP "led_pps_o" LOCATE = SITE "E6" LEVEL 1;
COMP "fpga_o_ttl_en" LOCATE = SITE "M3" LEVEL 1;
COMP "led_ttl_o" LOCATE = SITE "F8" LEVEL 1;
COMP "led_o_rear<1>" LOCATE = SITE "AB17" LEVEL 1;
COMP "led_o_rear<2>" LOCATE = SITE "AB19" LEVEL 1;
COMP "led_o_rear<3>" LOCATE = SITE "AA16" LEVEL 1;
COMP "led_o_rear<4>" LOCATE = SITE "AA18" LEVEL 1;
COMP "led_o_rear<5>" LOCATE = SITE "AB16" LEVEL 1;
COMP "led_o_rear<6>" LOCATE = SITE "AB18" LEVEL 1;
COMP "led_wr_ok_o" LOCATE = SITE "E5" LEVEL 1;
COMP "led_link_up_o" LOCATE = SITE "F7" LEVEL 1;
COMP "FPGA_CLK_N" LOCATE = SITE "G11" LEVEL 1;
COMP "FPGA_CLK_P" LOCATE = SITE "H12" LEVEL 1;
COMP "pulse_o_rear<1>" LOCATE = SITE "V1" LEVEL 1;
COMP "pulse_o_rear<2>" LOCATE = SITE "U1" LEVEL 1;
COMP "pulse_o_rear<3>" LOCATE = SITE "T2" LEVEL 1;
COMP "pulse_o_rear<4>" LOCATE = SITE "T1" LEVEL 1;
COMP "pulse_o_rear<5>" LOCATE = SITE "R1" LEVEL 1;
COMP "pulse_o_rear<6>" LOCATE = SITE "P2" LEVEL 1;
COMP "led_pw_o" LOCATE = SITE "F10" LEVEL 1;
COMP "pulse_i_front<1>" LOCATE = SITE "T3" LEVEL 1;
COMP "pulse_i_front<2>" LOCATE = SITE "U4" LEVEL 1;
COMP "pulse_i_front<3>" LOCATE = SITE "W3" LEVEL 1;
COMP "pulse_i_front<4>" LOCATE = SITE "W4" LEVEL 1;
COMP "pulse_i_front<5>" LOCATE = SITE "V3" LEVEL 1;
COMP "pulse_i_front<6>" LOCATE = SITE "U3" LEVEL 1;
COMP "inv_i<1>" LOCATE = SITE "Y1" LEVEL 1;
COMP "inv_i<2>" LOCATE = SITE "Y2" LEVEL 1;
COMP "inv_i<3>" LOCATE = SITE "AA1" LEVEL 1;
COMP "inv_i<4>" LOCATE = SITE "AA2" LEVEL 1;
COMP "inv_o<1>" LOCATE = SITE "J1" LEVEL 1;
COMP "inv_o<2>" LOCATE = SITE "K2" LEVEL 1;
COMP "inv_o<3>" LOCATE = SITE "K1" LEVEL 1;
COMP "inv_o<4>" LOCATE = SITE "L1" LEVEL 1;
COMP "led_o_front<1>" LOCATE = SITE "H3" LEVEL 1;
COMP "led_o_front<2>" LOCATE = SITE "J4" LEVEL 1;
COMP "led_o_front<3>" LOCATE = SITE "J3" LEVEL 1;
COMP "led_o_front<4>" LOCATE = SITE "K3" LEVEL 1;
COMP "led_o_front<5>" LOCATE = SITE "L4" LEVEL 1;
COMP "led_o_front<6>" LOCATE = SITE "L3" LEVEL 1;
COMP "manual_rst_n_o" LOCATE = SITE "T22" LEVEL 1;
COMP "switch_i" LOCATE = SITE "F22" LEVEL 1;
COMP "pulse_o_front<1>" LOCATE = SITE "D1" LEVEL 1;
COMP "pulse_o_front<2>" LOCATE = SITE "E1" LEVEL 1;
COMP "pulse_o_front<3>" LOCATE = SITE "F2" LEVEL 1;
COMP "pulse_o_front<4>" LOCATE = SITE "F1" LEVEL 1;
COMP "pulse_o_front<5>" LOCATE = SITE "G1" LEVEL 1;
COMP "pulse_o_front<6>" LOCATE = SITE "H2" LEVEL 1;
SCHEMATIC END;
vhdl work "../../ctdah_lib/rtl/gc_ff.vhd"
vhdl work "../../ctdah_lib/rtl/gc_simple_monostable.vhd"
vhdl work "../../ctdah_lib/rtl/gc_debouncer.vhd"
vhdl work "../../ctdah_lib/rtl/ctdah_pkg.vhd"
vhdl work "../rtl/basic_trigger_core.vhd"
vhdl work "../rtl/basic_trigger_top.vhd"
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 13.3 - par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 21 11:50:43 2012
All signals are completely routed.
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:10
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullUp
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn basic_trigger_top.prj
-ofn basic_trigger_top
-ofmt NGC
-p xc6slx45t-3-fgg484
-top basic_trigger_top
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
INTSTYLE=ise
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Release 13.3 Map O.76xd (lin)
Xilinx Map Application Log File for Design 'basic_trigger_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd
basic_trigger_top.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Nov 21 11:50:06 2012
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:f259d460) REAL time: 9 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:f259d460) REAL time: 10 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f259d460) REAL time: 10 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:7e6de904) REAL time: 12 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:7e6de904) REAL time: 12 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:7e6de904) REAL time: 12 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:7e6de904) REAL time: 12 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:7e6de904) REAL time: 12 secs
Phase 9.8 Global Placement
.................................
.....................
Phase 9.8 Global Placement (Checksum:8eb769c7) REAL time: 13 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:8eb769c7) REAL time: 13 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:2a0a8deb) REAL time: 14 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:2a0a8deb) REAL time: 14 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:fc7e585) REAL time: 14 secs
Total REAL time to Placer completion: 15 secs
Total CPU time to Placer completion: 14 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 249 out of 54,576 1%
Number used as Flip Flops: 249
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 596 out of 27,288 2%
Number used as logic: 572 out of 27,288 2%
Number using O6 output only: 320
Number using O5 output only: 180
Number using O5 and O6: 72
Number used as ROM: 0
Number used as Memory: 8 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 8
Number using O6 output only: 8
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 16
Number with same-slice register load: 4
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 199 out of 6,822 2%
Nummber of MUXCYs used: 384 out of 13,644 2%
Number of LUT Flip Flop pairs used: 618
Number with an unused Flip Flop: 377 out of 618 61%
Number with an unused LUT: 22 out of 618 3%
Number of fully used LUT-FF pairs: 219 out of 618 35%
Number of unique control sets: 17
Number of slice register sites lost
to control set restrictions: 23 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 59 out of 296 19%
Number of LOCed IOBs: 59 out of 59 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.84
Peak Memory Usage: 284 MB
Total REAL time to MAP completion: 16 secs
Total CPU time to MAP completion: 15 secs
Mapping completed.
See MAP report file "basic_trigger_top_map.mrp" for details.
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