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Commit 3ba1d86d authored by gilsoriano's avatar gilsoriano
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Modifications placed into SPI to allow better compatibility and easy of use… 

Modifications placed into SPI to allow better compatibility and easy of use while used together with m25p32 controller. Improvements:
- SPI0 initiliazation modified to avoid undesired SPI transactions.
- SPI1 one-clock instructions can trigger now SPI transactions.
- Added waveforms to spi tb
parent fa473234
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Showing with 136 additions and 89 deletions
hdl/spi_master_multifield/project/spi_master_multifield.xise
View file @ 3ba1d86d
......@@ -51,23 +51,27 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../test/spi_master_core_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../test/spi_analyser_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../test/spi_analyser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../test/spi_analyser_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<file xil_pn:name="../test/spi_master_core_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="42"/>
</file>
</files>
......@@ -411,7 +415,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_master_core_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_master_core_tb|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spi_master_multifield" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
......@@ -419,7 +423,7 @@
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|spi_master_core_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-14T17:32:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9D432F8007A3C311BE2F7AC8ADB2C4AE" xil_pn:valueState="non-default"/>
......
hdl/spi_master_multifield/project/waveform/wave.do
View file @ 3ba1d86d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group SPI /spi_master_core_tb/uut/spi_miso_i
add wave -noupdate -group SPI /spi_master_core_tb/uut/spi_mosi_o
add wave -noupdate -group SPI /spi_master_core_tb/uut/spi_cs_n_o
add wave -noupdate -group SPI /spi_master_core_tb/uut/spi_clk_o
add wave -noupdate -divider spi_master_core
add wave -noupdate /spi_master_core_tb/rst_i
add wave -noupdate /spi_master_core_tb/clk_i
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_miso_i
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_mosi_o
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_cs_n_o
add wave -noupdate -expand -group SPI /spi_master_core_tb/uut/spi_clk_o
add wave -noupdate -radix hexadecimal /spi_master_core_tb/inst_i
add wave -noupdate -radix hexadecimal /spi_master_core_tb/addr_i
add wave -noupdate -radix hexadecimal /spi_master_core_tb/data_i
......@@ -13,6 +14,9 @@ add wave -noupdate /spi_master_core_tb/uut/s_STATUS
add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI0
add wave -noupdate /spi_master_core_tb/uut/s_SPI0_core
add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI1
add wave -noupdate /spi_master_core_tb/uut/s_PUSH_INST_tmp
add wave -noupdate /spi_master_core_tb/uut/s_PUSH_ADDR_tmp
add wave -noupdate /spi_master_core_tb/uut/s_PUSH_DATA_tmp
add wave -noupdate /spi_master_core_tb/uut/s_SPI1_core
add wave -noupdate /spi_master_core_tb/uut/s_SPI1_core_d0
add wave -noupdate /spi_master_core_tb/uut/s_SPI2
......@@ -55,16 +59,17 @@ add wave -noupdate -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_e
add wave -noupdate -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/rst_i
add wave -noupdate -group {READ EDGE counter} /spi_master_core_tb/uut/spi_read_edge_counter/en_i
add wave -noupdate -group {READ EDGE counter} -radix unsigned /spi_master_core_tb/uut/spi_read_edge_counter/cnt_o
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_rst_spi_analyser
add wave -noupdate -expand -group Testbench /spi_master_core_tb/tester/s_spi_count
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/s_inst_check
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_inst_flag
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/s_addr_check
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_addr_flag
add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/s_data_check
add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_data_flag
add wave -noupdate -divider spi_analyser
add wave -noupdate -group Testbench /spi_master_core_tb/s_rst_spi_analyser
add wave -noupdate -group Testbench /spi_master_core_tb/tester/s_spi_count
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/s_inst_check
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_inst_flag
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/s_addr_check
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_addr_flag
add wave -noupdate -group Testbench -radix hexadecimal /spi_master_core_tb/s_data_check
add wave -noupdate -group Testbench /spi_master_core_tb/s_end_data_flag
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1877079 ps} 0}
WaveRestoreCursors {{Cursor 1} {35720851 ps} 0}
configure wave -namecolwidth 260
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -79,4 +84,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {19409250 ps}
WaveRestoreZoom {0 ps} {38813250 ps}
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ 3ba1d86d
......@@ -84,6 +84,10 @@ signal s_SPI2 : r_SPI2;
signal s_SPI2_d0 : r_SPI2;
signal s_SPI3 : r_SPI3;
signal s_PUSH_INST_tmp : STD_LOGIC;
signal s_PUSH_ADDR_tmp : STD_LOGIC;
signal s_PUSH_DATA_tmp : STD_LOGIC;
--! This copy of registers is done to protect for bad use
signal s_SPI0_core : r_SPI0;
signal s_SPI1_core : r_SPI1;
......@@ -341,20 +345,28 @@ begin
s_SPI0_core.CPOL <= s_SPI0.CPOL;
s_SPI0_core.CPHA <= s_SPI0.CPHA;
if (to_integer(s_SPI0.BINST) <= c_SPI0_default.BINST) then
if (to_integer(s_SPI0.BINST) <= to_unsigned(c_INST_LENGTH, 9)) then
s_SPI0_core.BINST <= s_SPI0.BINST;
else
s_SPI0_core.BINST <= to_unsigned(c_INST_LENGTH, 9);
end if;
if (to_integer(s_SPI0.BADDR) <= c_SPI0_default.BADDR) then
if (to_integer(s_SPI0.BADDR) <= to_unsigned(c_ADDR_LENGTH, 9)) then
s_SPI0_core.BADDR <= s_SPI0.BADDR;
else
s_SPI0_core.BADDR <= to_unsigned(c_ADDR_LENGTH, 9);
end if;
if (to_integer(s_SPI0.BDATA) <= c_SPI0_default.BDATA) then
s_SPI0_core.BDATA <= s_SPI0.BDATA;
if (to_integer(s_SPI0.BDATA) <= to_unsigned(c_DATA_LENGTH, 9)) then
s_SPI0_core.BDATA <= s_SPI0.BDATA;
else
s_SPI0_core.BDATA <= to_unsigned(c_DATA_LENGTH, 9);
end if;
if (to_integer(s_SPI0.BREAD) <= c_SPI0_default.BREAD) then
s_SPI0_core.BREAD <= s_SPI0.BREAD;
if (to_integer(s_SPI0.BREAD) <= to_unsigned(c_READ_LENGTH, 3)) then
s_SPI0_core.BREAD <= s_SPI0.BREAD;
else
s_SPI0_core.BREAD <= to_unsigned(c_READ_LENGTH, 9);
end if;
end if;
......@@ -363,13 +375,13 @@ begin
-----------------------------------------------------------
--! HW crop of bad instructions
-----------------------------------------------------------
p_comb_SPI1_ctrl: process(s_SPI1, s_STATUS.clk_fsm)
p_comb_SPI1_ctrl: process(s_SPI0_core, s_SPI1, s_STATUS.clk_fsm)
begin
if s_STATUS.clk_fsm = R0_RESET
or ( s_SPI1.SEND_INST = '1'
and s_SPI0_core.BINST = 0)
or ( s_STATUS.clk_fsm = S0_IDLE
and s_clk_fsm_d0 = R0_RESET) then
and s_SPI0_core.BINST = 0) then
-- or ( s_STATUS.clk_fsm = S0_IDLE
-- and s_clk_fsm_d0 = R0_RESET) then
s_SPI1_core.x <= c_SPI1_default.x;
s_SPI1_core.READ_MISO <= c_SPI1_default.READ_MISO;
s_SPI1_core.SEND_DATA <= c_SPI1_default.SEND_DATA;
......@@ -436,26 +448,29 @@ begin
else
s_SPI1_core.CLK_DIV <= s_SPI1.CLK_DIV;
end if;
--! The push buffers are temporally loaded here to properly
--! attend one-clock SPI1.SEND_OP = '1' when they are directly
--! called to spi_master_core.vhd
s_PUSH_INST_tmp <= s_SPI1.PUSH_INST;
s_PUSH_ADDR_tmp <= s_SPI1.PUSH_ADDR;
s_PUSH_DATA_tmp <= s_SPI1.PUSH_DATA;
s_SPI1_core.x <= s_SPI1.x;
s_SPI1_core.y <= s_SPI1.y;
s_SPI1_core.z <= s_SPI1.z;
end if;
end if;
end process p_comb_SPI1_ctrl;
-----------------------------------------------------------
--! Process to control the load of the FIFOs
-----------------------------------------------------------
p_SPI1_PUSH_ctrl : process(clk_i)
p_SPI1_PUSH_ctrl : process(s_STATUS.clk_fsm, s_clk_fsm_d0)
begin
if rising_edge(clk_i) then
s_SPI1_core.PUSH_INST <= c_SPI1_default.PUSH_INST;
s_SPI1_core.PUSH_ADDR <= c_SPI1_default.PUSH_ADDR;
s_SPI1_core.PUSH_DATA <= c_SPI1_default.PUSH_DATA;
s_SPI1_core.PUSH_INST <= c_SPI1_default.PUSH_INST;
s_SPI1_core.PUSH_ADDR <= c_SPI1_default.PUSH_ADDR;
s_SPI1_core.PUSH_DATA <= c_SPI1_default.PUSH_DATA;
--! As the S1_SETUP will take one clock at least, we push
--! from SPI1 into internal s_SPI1_core, depending upon the
--! setup.
......@@ -465,21 +480,19 @@ begin
if s_STATUS.clk_fsm = S1_SETUP
and s_clk_fsm_d0 /= S1_SETUP then
if s_SPI1.SEND_INST = '1' then
s_SPI1_core.PUSH_INST <= s_SPI1.PUSH_INST;
if s_SPI1_core.SEND_INST = '1' then
s_SPI1_core.PUSH_INST <= s_PUSH_INST_tmp;
end if;
if s_SPI1.SEND_ADDR = '1' then
s_SPI1_core.PUSH_ADDR <= s_SPI1.PUSH_ADDR;
if s_SPI1_core.SEND_ADDR = '1' then
s_SPI1_core.PUSH_ADDR <= s_PUSH_ADDR_tmp;
end if;
if s_SPI1.SEND_DATA = '1' then
s_SPI1_core.PUSH_DATA <= s_SPI1.PUSH_DATA;
if s_SPI1_core.SEND_DATA = '1' then
s_SPI1_core.PUSH_DATA <= s_PUSH_DATA_tmp;
end if;
end if;
else
end if;
end process p_SPI1_PUSH_ctrl;
-----------------------------------------------------------
......
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ 3ba1d86d
......@@ -43,6 +43,8 @@ use IEEE.NUMERIC_STD.ALL;
package spi_master_pkg is
attribute a_length : NATURAL;
----------------------------------------
-- SPI0 register
----------------------------------------
......@@ -67,6 +69,8 @@ package spi_master_pkg is
BINST : UNSIGNED (31 downto 23);
end record;
attribute a_length of r_SPI0 : type is 32;
----------------------------------------
-- SPI1 register
----------------------------------------
......@@ -86,7 +90,7 @@ package spi_master_pkg is
-- 8 SEND_ADDR ADDR bytes will be sent in a write operation
-- 9 SEND_INST INST bytes will be sent in a write operation
-- 10 SEND_OP perform a SEND OPeration
-- 11-10 y Reserved
-- 11 y Reserved
-- 15-12 CLK_DIV CLocK DIVider
-- 31-16 z Reserved
----------------------------------------
......@@ -106,6 +110,8 @@ package spi_master_pkg is
z : STD_LOGIC_VECTOR (31 downto 16);
end record;
attribute a_length of r_SPI1 : type is 32;
----------------------------------------
-- SPI2 register
----------------------------------------
......@@ -134,6 +140,7 @@ package spi_master_pkg is
CLK_DIV : UNSIGNED (15 downto 12);
end record;
attribute a_length of r_SPI2 : type is 16;
----------------------------------------
-- SPI3 register
----------------------------------------
......@@ -148,6 +155,8 @@ package spi_master_pkg is
MOSI_DATA : STD_LOGIC_VECTOR(31 downto 0);
end record;
attribute a_length of r_SPI3 : type is 32;
constant c_INST_LENGTH : NATURAL := 1;
constant c_ADDR_LENGTH : NATURAL := 3;
constant c_DATA_LENGTH : NATURAL := 256;
......@@ -156,14 +165,18 @@ package spi_master_pkg is
constant c_CLK_DIV : UNSIGNED (15 downto 12) := to_unsigned( 2, 4);
constant c_SPI0_default : r_SPI0 := (CPOL => '0',
CPHA => '0',
BREAD => to_unsigned(c_READ_LENGTH,
r_SPI0.BREAD'length),
BDATA => to_unsigned(c_DATA_LENGTH,
r_SPI0.BDATA'length),
BADDR => to_unsigned(c_ADDR_LENGTH,
r_SPI0.BADDR'length),
BINST => to_unsigned(c_INST_LENGTH,
r_SPI0.BINST'length));
BREAD => to_unsigned(0, 3),
BDATA => to_unsigned(0, 9),
BADDR => to_unsigned(0, 9),
BINST => to_unsigned(0, 9));
--! BREAD => to_unsigned(c_READ_LENGTH,
--! 3),
--! BDATA => to_unsigned(c_DATA_LENGTH,
--! 9),
--! BADDR => to_unsigned(c_ADDR_LENGTH,
--! 9),
--! BINST => to_unsigned(c_INST_LENGTH,
--! 9));
constant c_SPI1_default : r_SPI1 := (PUSH_DATA => '0',
PUSH_ADDR => '0',
......
hdl/spi_master_multifield/test/spi_analyser.vhd
View file @ 3ba1d86d
......@@ -52,7 +52,7 @@ entity spi_analyser is
);
end spi_analyser;
architecture behavior of spi_analyser is
architecture Behavioral of spi_analyser is
signal s_spi_count : NATURAL := 0;
......
hdl/spi_master_multifield/test/spi_master_core_tb.vhd
View file @ 3ba1d86d
......@@ -36,28 +36,34 @@ use work.spi_analyser_pkg.ALL;
entity spi_master_core_tb is
end spi_master_core_tb;
architecture behavior of spi_master_core_tb is
component spi_master_core
port(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC
);
architecture Behavioral of spi_master_core_tb is
component spi_master_core
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (8*g_READ_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC);
end component;
......@@ -65,29 +71,35 @@ architecture behavior of spi_master_core_tb is
signal rst_i : STD_LOGIC := '0';
signal clk_i : STD_LOGIC := '0';
signal s_inst : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0) := (others => '0');
signal s_addr : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0) := (others => '0');
signal s_data : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := (others => '0');
signal data_o : STD_LOGIC_VECTOR (8*c_READ_LENGTH - 1 downto 0);
signal inst_i : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0) := (others => '0');
signal addr_i : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0) := (others => '0');
signal data_i : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := (others => '0');
--Inputs
signal s_SPI0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR(31 downto 0);
signal s_SPI0_slv : STD_LOGIC_VECTOR(r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR(31 downto 0);
signal s_SPI1_slv : STD_LOGIC_VECTOR(r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR(15 downto 0);
signal s_SPI2_slv : STD_LOGIC_VECTOR(r_SPI2'a_length - 1 downto 0);
signal s_spi_mosi : STD_LOGIC;
signal s_spi_miso : STD_LOGIC := '0';
signal s_spi_clk : STD_LOGIC;
signal s_spi_cs_n : STD_LOGIC;
signal s_inst_check : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal s_data_check : STD_LOGIC_VECTOR (2047 downto 0) := (others => '0');
signal s_inst_check : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0) :=
(others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0) :=
(others => '0');
signal s_data_check : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) :=
(others => '0');
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
......
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