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Conv TTL Blocking
Commit 3bcc3dfb authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Remapped correctly image1 and expanded the wave.do file for simulation. Now it looks beautiful.

parent abe238c9
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hdl/IMAGES/image1/project/image1.gise
View file @ 3bcc3dfb
......@@ -60,7 +60,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354292643" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1354292642">
<transform xil_pn:end_ts="1354387693" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1354387693">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -112,7 +112,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354292643" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1354292643">
<transform xil_pn:end_ts="1354387693" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1354387693">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -152,7 +152,7 @@
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1354292914" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1354292913">
<transform xil_pn:end_ts="1354387694" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1354387693">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="image1_top_tb.fdo"/>
......
hdl/IMAGES/image1/project/waveform/wave.do
View file @ 3bcc3dfb
This diff is collapsed.
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 3bcc3dfb
......@@ -43,8 +43,21 @@ package image1_pkg is
constant c_SLAVE_MULTIBOOT : NATURAL := 1;
constant c_SLAVE_M25P32 : NATURAL := 2;
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000200";
constant c_ADDR_M25P32 : t_wishbone_address := X"00000080";
--! ==================================
--! MEMORY MAPPINGS
--! ==================================
--! Byte aligned
--! It should be noted that all internal modules are word aligned.
--! Thus, access to byte 1,2 or 3 within an internal word register
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! M25P32 [0800-0FFF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! ==================================
constant c_ADDR_M25P32 : t_wishbone_address := X"00000200";
constant c_ADDR_MULTIBOOT : t_wishbone_address := X"00000080";
constant c_ADDR_I2C_SLAVE : t_wishbone_address := X"00000040";
--! 64 words per page: 6 + 1 bits
......
hdl/IMAGES/image1/rtl/image1_top.vhd
View file @ 3bcc3dfb
......@@ -272,6 +272,8 @@ begin
wr_done_o => open,
i2c_addr_i => s_i2c_addr);
inst_m25p32: m25p32_top
port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_clk => s_clk.SYS_A,
......@@ -292,6 +294,7 @@ begin
prom_cs0_b_n_o => FPGA_PROM_CSO_B_N,
prom_din_i => FPGA_PROM_DIN);
inst_multiboot: multiboot_top
port map(wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_clk => s_clk.SYS_A,
......@@ -306,6 +309,14 @@ begin
wb_rty_o => s_master_i(c_SLAVE_MULTIBOOT).rty,
wb_err_o => s_master_i(c_SLAVE_MULTIBOOT).err);
s_master_i(c_SLAVE_I2C_SLAVE).stall <= '0';
s_master_i(c_SLAVE_I2C_SLAVE).int <= '0';
s_master_i(c_SLAVE_M25P32).stall <= '0';
s_master_i(c_SLAVE_M25P32).int <= '0';
s_master_i(c_SLAVE_MULTIBOOT).stall <= '0';
s_master_i(c_SLAVE_MULTIBOOT).int <= '0';
inst_wb_crossbar: xwb_crossbar
generic map(g_num_masters => c_NUM_MASTERS,
g_num_slaves => c_NUM_SLAVES,
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 3bcc3dfb
......@@ -51,7 +51,7 @@ architecture behavior of image1_top_tb is
signal level : STD_LOGIC := '1';
signal switch_i : STD_LOGIC;
signal manual_rst_n_o : STD_LOGIC;
signal s_RTM_id_i : t_RTM_id;
signal s_RTM_id_i : t_RTM_id := c_RTM_id_default;
--! ========================================================================
--! Signals for the i2c_master_driver (Renesasa alike)
......@@ -237,8 +237,8 @@ begin
wait until falling_edge(s_rst);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
-- --! First we place a write
-- start_I2C;
--! First we place a write
start_I2C;
-- --! Try to write into DTX addr position
-- write_I2C(s_FPGA_GA, X"0002", X"B16B00B5");
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ 3bcc3dfb
......@@ -6,11 +6,11 @@ use IEEE.NUMERIC_STD.ALL;
--! Packages from IP cores
--use work.wishbone_pkg.ALL;
--use work.i2c_slave_pkg.ALL;
--use work.m25p32_pkg.ALL;
--use work.multiboot_pkg.ALL;
use work.image1_pkg.ALL;
use work.rtm_detector_pkg.ALL;
use work.i2c_slave_pkg.ALL;
use work.m25p32_pkg.ALL;
use work.multiboot_pkg.ALL;
package image1_top_tb_pkg is
......@@ -121,12 +121,70 @@ package image1_top_tb_pkg is
constant c_I2C_master_out_default : t_I2C_master_out := (SCL => '1',
SDA => '1');
constant c_RTM_id_default : t_RTM_id
:= (RTMM => STD_LOGIC_VECTOR(c_RTMM_V1),
RTMP =>
STD_LOGIC_VECTOR(c_RTMP_BLOCKING_V1));
constant c_RTM_id_default : t_RTM_id
:= (RTMM => STD_LOGIC_VECTOR(c_RTMM_V1),
RTMP => STD_LOGIC_VECTOR(c_RTMP_BLOCKING_V1));
--! ==================================
--! MEMORY MAPPINGS
--! ==================================
--! Byte aligned
--! It should be noted that all internal modules are word aligned.
--! Thus, access to byte 1,2 or 3 within an internal word register
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! MULTIBOOT [0200-02FF]
--! M25P32 [0080-00BF]
--! I2C_SLAVE [0040-007F]
--! ==================================
--! c_I2C_CTR0_addr [0040]
--! c_I2C_LT_addr [0044]
--! c_I2C_DTX_addr [0048]
--! c_I2C_DRXA_addr [004C]
--! c_I2C_DRXB_addr [0050]
--! c_MULTIBOOT_CTR0_addr [0080]
--! c_MULTIBOOT_CTR1_addr [0084]
--! c_MULTIBOOT_STAT_addr [0088]
--! c_MULTIBOOT_MBA_addr [008C]
--! c_MULTIBOOT_GBA_addr [0090]
--! c_MULTIBOOT_MBA_ICAP_addr [0094]
--! c_MULTIBOOT_GBA_ICAP_addr [0098]
--! c_M25P32_FMI_addr [0800]
--! c_M25P32_SR_m25p32_addr [0804]
--! c_M25P32_DATA_READ_addr [0808]
--! c_M25P32_DATA_WRITE_addr [081C - 8480]
constant c_I2C_CTR0_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"01"& STD_LOGIC_VECTOR(work.i2c_slave_pkg.c_CTR0_addr) & "00";
constant c_I2C_LT_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"01"& STD_LOGIC_VECTOR(work.i2c_slave_pkg.c_LT_addr) & "00";
constant c_I2C_DTX_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"01"& STD_LOGIC_VECTOR(work.i2c_slave_pkg.c_DTX_addr) & "00";
constant c_I2C_DRXA_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"01"& STD_LOGIC_VECTOR(work.i2c_slave_pkg.c_DRXA_addr) & "00";
constant c_I2C_DRXB_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"01"& STD_LOGIC_VECTOR(work.i2c_slave_pkg.c_DRXB_addr) & "00";
constant c_MULTIBOOT_CTR0_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.CTR0_addr) &"00";
constant c_MULTIBOOT_CTR1_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.CTR1_addr) &"00";
constant c_MULTIBOOT_STAT_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.STAT_addr) &"00";
constant c_MULTIBOOT_MBA_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.c_MBA_addr) &"00";
constant c_MULTIBOOT_GBA_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.c_GBA_addr) &"00";
constant c_MULTIBOOT_MBA_ICAP_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.c_MBA_ICAP_addr) &"00";
constant c_MULTIBOOT_GBA_ICAP_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.c_GBA_ICAP_addr) &"00";
constant c_M25P32_FMI_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_FMI_addr &"00";
constant c_M25P32_SR_m25p32_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_SR_m25p32_addr &"00";
constant c_M25P32_DATA_READ_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_DATA_READ_addr &"00";
constant c_M25P32_DATA_WRITE_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_DATA_WRITE_addr &"00";
end image1_top_tb_pkg;
package body image1_top_tb_pkg is
end image1_top_tb_pkg;
hdl/basic_trigger/.gitignore
View file @ 3bcc3dfb
......@@ -12,6 +12,7 @@ doc/Figures/*.eps
project/*
project/*/
project/bitstream/*.*
project/bitstream/basic_trigger_top.*
!project/bitstream/basic_trigger_top.bit
!project/project.gise
!project/project.xise
......
hdl/multiboot/.gitignore
View file @ 3bcc3dfb
......@@ -5,6 +5,7 @@ doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
doc/Xilinx/sp605_*/*
!doc/*.tex
!doc/*.pdf
......
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