Some comments after reading the HW Guide

40b1950d · Javier Serrano · 81f89746 · 40b1950d
Commit 40b1950d authored Nov 06, 2013 by Javier Serrano
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javier.txt design-review/javier.txt +21 -1

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@@ -69,6 +69,27 @@ Page 9. Reader is left wondering why configuration register reads is
 limited to 16 bits. Only later in the document it is proposed as a
 possible design evolution. Is it so hard? Or is it just useless? 

+Some comments after reading the Hardware Guide
+==============================================
+
+I have never seen a /TTL application where pulse producers are
+requested to drive a 50 Ohm input impedance. This means these
+producers should continuously provide a current of V/50, where V is a
+voltage high enough to be interpreted as a TTL high. Not very
+"green". This could be taken into account in some future version of
+the hardware: upon selecting /TTL operation, maybe the termination
+scheme could be a 10k pull-up instead of 50 Ohm to ground, controlled
+with transistors. In this way, the awkward detection of whether an
+input signal is connected could be eliminated from the HDL design.
+
+Please check crosstalk between BLO signals in the P2 connector.
+
+I guess this has been discussed in the past. I wonder if we should not
+have a protection mechanism for the MOSFET in the blocking output
+stage which is independent of what people do with the FPGA. A parallel
+RC network to connect its source to ground (instead of the current
+short) might be an option, with suitable values of R and C.
+
 conv_ttl_blo.vhd
 ================

@@ -79,7 +100,6 @@ signal. In particular, consider the fact that the signal is going to
 the enable inputs of the counter flip-flops. What happens if in a
 given clock cycle some FFs see the signal as '1' and others as '0'?

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 Todo
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