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Conv TTL Blocking
Commit 456634b1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Updated documentation file, set pulse status LED lighting length to 125 ms.

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doc/HDL/usersGuide/Figures/EDA-02446-V1-0_fp.svg deleted 100755 → 0
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doc/HDL/usersGuide/userGuide.aux deleted 100755 → 0
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\relax
\ifx\hyper@anchor\@undefined
\global \let \oldcontentsline\contentsline
\gdef \contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}}
\global \let \oldnewlabel\newlabel
\gdef \newlabel#1#2{\newlabelxx{#1}#2}
\gdef \newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}}
\AtEndDocument{\let \contentsline\oldcontentsline
\let \newlabel\oldnewlabel}
\else
\global \let \hyper@last\relax
\fi
\citation{StandardBlocking}
\@writefile{toc}{\contentsline {section}{\numberline {1}Introduction}{1}{section.1}}
\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces Pulse Repetition system}}{1}{figure.1}}
\newlabel{prs}{{1}{1}{Pulse Repetition system\relax }{figure.1}{}}
\@writefile{lot}{\contentsline {table}{\numberline {1}{\ignorespaces Boards for Blocking repetition}}{2}{table.1}}
\newlabel{boards}{{1}{2}{Boards for Blocking repetition\relax }{table.1}{}}
\@writefile{toc}{\contentsline {section}{\numberline {2}Board Ports}{3}{section.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.1}TTL-triggers}{3}{subsection.2.1}}
\@writefile{lot}{\contentsline {table}{\numberline {2}{\ignorespaces TTL-triggers Front Panel inputs}}{3}{table.2}}
\newlabel{trigFP}{{2}{3}{TTL-triggers Front Panel inputs\relax }{table.2}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.2}TTL-level Blocking pulses replica}{3}{subsection.2.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.3}SFP connector}{3}{subsection.2.3}}
\@writefile{lot}{\contentsline {table}{\numberline {3}{\ignorespaces TTL-level Blocking pulses Front Panel output}}{4}{table.3}}
\newlabel{replicaFP}{{3}{4}{TTL-level Blocking pulses Front Panel output\relax }{table.3}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.4}General pupose}{4}{subsection.2.4}}
\@writefile{lot}{\contentsline {table}{\numberline {4}{\ignorespaces General pupose Front Panel IOs}}{4}{table.4}}
\newlabel{gpFP}{{4}{4}{General pupose Front Panel IOs\relax }{table.4}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.5}Front Panel}{5}{subsection.2.5}}
\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces CONV-TTL-BLO Front Panel}}{5}{figure.2}}
\newlabel{fp}{{2}{5}{CONV-TTL-BLO Front Panel\relax }{figure.2}{}}
\@writefile{toc}{\contentsline {section}{\numberline {3}Board Addressing}{6}{section.3}}
\@writefile{toc}{\contentsline {section}{\numberline {4}Functional Description}{7}{section.4}}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Trigger sources}{7}{subsection.4.1}}
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\@writefile{toc}{\contentsline {section}{\numberline {5}Memory Map}{8}{section.5}}
\@writefile{lot}{\contentsline {table}{\numberline {6}{\ignorespaces CONV-TTL-BLO Memory map I/II}}{8}{table.6}}
\newlabel{mmap1}{{6}{8}{CONV-TTL-BLO Memory map I/II\relax }{table.6}{}}
\@writefile{lot}{\contentsline {table}{\numberline {7}{\ignorespaces CONV-TTL-BLO Memory map II/II}}{9}{table.7}}
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\@writefile{toc}{\contentsline {section}{\numberline {6}Register Description}{10}{section.6}}
\@writefile{toc}{\contentsline {subsection}{\numberline {6.1}Access Registers}{10}{subsection.6.1}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.1.1}CTR0\_ACCESS}{10}{subsubsection.6.1.1}}
\@writefile{lot}{\contentsline {table}{\numberline {8}{\ignorespaces CTR0\_ACCESS Register}}{10}{table.8}}
\newlabel{ctr0access}{{8}{10}{CTR0\_ACCESS Register\relax }{table.8}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.1.2}CTR1\_ACCESS}{10}{subsubsection.6.1.2}}
\@writefile{lot}{\contentsline {table}{\numberline {9}{\ignorespaces CTR1\_ACCESS Register}}{11}{table.9}}
\newlabel{ctr1access}{{9}{11}{CTR1\_ACCESS Register\relax }{table.9}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {6.2}I2C Registers}{12}{subsection.6.2}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.2.1}CTR0\_I2C}{12}{subsubsection.6.2.1}}
\@writefile{lot}{\contentsline {table}{\numberline {10}{\ignorespaces CTR0\_I2C Register}}{12}{table.10}}
\newlabel{ctr0I2C}{{10}{12}{CTR0\_I2C Register\relax }{table.10}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.2.2}CTR1\_I2C}{12}{subsubsection.6.2.2}}
\@writefile{lot}{\contentsline {table}{\numberline {11}{\ignorespaces CTR1\_I2C Register}}{12}{table.11}}
\newlabel{ctr1I2C}{{11}{12}{CTR1\_I2C Register\relax }{table.11}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {6.3}Channel Registers}{13}{subsection.6.3}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.3.1}CTR0\_CH[x]}{13}{subsubsection.6.3.1}}
\@writefile{lot}{\contentsline {table}{\numberline {12}{\ignorespaces CTR0\_CH[x] Register}}{13}{table.12}}
\newlabel{ctr0ch}{{12}{13}{CTR0\_CH[x] Register\relax }{table.12}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.3.2}CTR1\_CH[x]}{13}{subsubsection.6.3.2}}
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\newlabel{ctr1ch}{{13}{13}{CTR1\_CH[x] Register\relax }{table.13}{}}
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\@writefile{lot}{\contentsline {table}{\numberline {15}{\ignorespaces RAM1\_CH[x] Register}}{14}{table.15}}
\newlabel{ram1ch}{{15}{14}{RAM1\_CH[x] Register\relax }{table.15}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {6.3.5}RAM2\_CH[x]}{14}{subsubsection.6.3.5}}
\@writefile{lot}{\contentsline {table}{\numberline {16}{\ignorespaces RAM2\_CH[x] Register}}{14}{table.16}}
\newlabel{ram2ch}{{16}{14}{RAM2\_CH[x] Register\relax }{table.16}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {6.4}Multiboot Registers}{15}{subsection.6.4}}
\@writefile{toc}{\contentsline {subsection}{\numberline {6.5}White Rabbit Registers}{15}{subsection.6.5}}
\bibstyle{unsrt}
\bibdata{userGuide}
\bibcite{StandardBlocking}{1}
\@writefile{toc}{\contentsline {section}{\numberline {7}Installation}{16}{section.7}}
doc/HDL/usersGuide/userGuide.bib deleted 100755 → 0
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@misc{StandardBlocking,
author= "C. Gil Soriano",
title= {{Standard Blocking Output Signal Definition for CTDAH board}},
month= sep,
year= 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@TECHREPORT{UG380,
institution= "Xilinx Inc.",
title= {{Spartan-6 FPGA Configuration User Guide}},
month= jul,
year= 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
\ No newline at end of file
doc/HDL/usersGuide/userGuide.tex deleted 100755 → 0
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doc/ug/Figures/EDA-02446-V1-0_fp.svg 0 → 100755
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doc/ug/Makefile 0 → 100644
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FILE=ug-conv-ttl-blo
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/ug/ug-conv-ttl-blo.bib 0 → 100755
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@misc{StandardBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@misc{rtm-ident,
title = {{RTM detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
doc/ug/ug-conv-ttl-blo.tex 0 → 100755
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hdl/IMAGES/image1/rtl/image1_core.vhd
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......@@ -413,9 +413,9 @@ begin
generic map
(
g_number_of_channels => g_number_of_channels,
g_clk_period => c_CLKB_PERIOD,
g_pulse_length => c_OUTPUT_PULSE_LENGTH,
g_led_blinking_length => c_LED_BLINKING_LENGTH
g_clk_period => 5 ns,
g_pulse_length => 1000 ns,
g_led_blinking_length => (10**6)*125 ns
)
port map
(
......
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