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Commit 45b75c34 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added installation and bicolor_led_ctrl folders

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hdl/bicolor_led_ctrl/README 0 → 100644
View file @ 45b75c34
Taken from:
http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
Revision: 220c7837
hdl/bicolor_led_ctrl/bicolor_led_ctrl.vhd 0 → 100644
View file @ 45b75c34
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN;
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
hdl/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd 0 → 100644
View file @ 45b75c34
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
installation/V1/basic_trigger/bitstream/basic_trigger_top.cfi 0 → 100755
View file @ 45b75c34
# PROMGEN: Xilinx Prom Generator O.76xd
# Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
SOFTWARE_VERSION O.76xd
DATE 11/21/2012 - 12: 5
SOURCE /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.mcs
DEVICE 4096K
DATA_WIDTH 1
FILL_DATA 0xFF
SIGNATURE 0x2946E582
START_ADDRESS 0x00000000 END_ADDRESS 0x0016A673 DIRECTION_UP "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.bit" 6slx45tfgg484
installation/V1/basic_trigger/bitstream/basic_trigger_top.mcs 0 → 100755
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installation/V1/basic_trigger/bitstream/basic_trigger_top.prm 0 → 100755
View file @ 45b75c34
PROMGEN: Xilinx Prom Generator O.76xd
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
promgen -w -p mcs -c FF -o /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream//basic_trigger_top -s 4096 -u 0000 /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.bit -spi
PROM /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.prm map: Wed Nov 21 12:05:59 2012
Calculating PROM checksum with fill value ff
Format Mcs86 (32-bit)
Size 4096K
PROM start 0000:0000
PROM end 003f:ffff
PROM checksum 2946e582
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Nov 21 11:51:58 2012 /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/bitstream/basic_trigger_top.bit
installation/V1/basic_trigger/constraints/FPGAbank.ucf 0 → 100755
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installation/V1/basic_trigger/project/.fuse_hidden00000ecd00000002 0 → 100755
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Release 13.3 - Bitgen O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/opt/Xilinx/13.3/ISE_DS/ISE/.
"basic_trigger_top" is an NCD, version 3.2, device xc6slx45t, package fgg484,
speed -3
installation/V1/basic_trigger/project/_ngo/netlist.lst 0 → 100755
View file @ 45b75c34
/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.ngc 1353494996
OK
installation/V1/basic_trigger/project/_xmsgs/.fuse_hidden00000ecc00000001 0 → 100755
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
installation/V1/basic_trigger/project/_xmsgs/bitgen.xmsgs 0 → 100755
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
installation/V1/basic_trigger/project/_xmsgs/map.xmsgs 0 → 100755
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>
installation/V1/basic_trigger/project/_xmsgs/ngdbuild.xmsgs 0 → 100755
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
installation/V1/basic_trigger/project/_xmsgs/par.xmsgs 0 → 100755
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>
installation/V1/basic_trigger/project/_xmsgs/pn_parser.xmsgs 0 → 100755
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>
installation/V1/basic_trigger/project/_xmsgs/trce.xmsgs 0 → 100755
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
installation/V1/basic_trigger/project/_xmsgs/xst.xmsgs 0 → 100755
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This source diff could not be displayed because it is too large. You can view the blob instead.
installation/V1/basic_trigger/project/basic_trigger.gise 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger.xise 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger_top.bgn 0 → 100755
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Release 13.3 - Bitgen O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/opt/Xilinx/13.3/ISE_DS/ISE/.
"basic_trigger_top" is an NCD, version 3.2, device xc6slx45t, package fgg484,
speed -3
Opened constraints file basic_trigger_top.pcf.
Wed Nov 21 11:51:28 2012
/opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:10 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullUp -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 basic_trigger_top.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 10 |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pullup |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| MaskVectorFile | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from basic_trigger_top.pcf.
Running DRC.
DRC detected 0 errors and 0 warnings.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "basic_trigger_top.bit".
Bitstream generation is complete.
installation/V1/basic_trigger/project/basic_trigger_top.bld 0 → 100755
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Release 13.3 ngdbuild O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -uc
/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/F
PGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
Reading NGO file
"/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basi
c_trigger_top.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file
"/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/
FPGAbank.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 107076 kilobytes
Writing NGD file "basic_trigger_top.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "basic_trigger_top.bld"...
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View file @ 45b75c34
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/basic_trigger_top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc constraints/FPGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd basic_trigger_top.pcf
par -w -intstyle ise -ol high -mt off basic_trigger_top_map.ncd basic_trigger_top.ncd basic_trigger_top.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_top.twx basic_trigger_top.ncd -o basic_trigger_top.twr basic_trigger_top.pcf
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.syr"
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/FPGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd basic_trigger_top.pcf
par -w -intstyle ise -ol high -mt off basic_trigger_top_map.ncd basic_trigger_top.ncd basic_trigger_top.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_top.twx basic_trigger_top.ncd -o basic_trigger_top.twr basic_trigger_top.pcf
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
xst -intstyle ise -ifn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.xst" -ofn "/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/FPGAbank.ucf -p xc6slx45t-fgg484-3 basic_trigger_top.ngc basic_trigger_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd basic_trigger_top.pcf
par -w -intstyle ise -ol high -mt off basic_trigger_top_map.ncd basic_trigger_top.ncd basic_trigger_top.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_top.twx basic_trigger_top.ncd -o basic_trigger_top.twr basic_trigger_top.pcf
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
bitgen -intstyle ise -f basic_trigger_top.ut basic_trigger_top.ncd
installation/V1/basic_trigger/project/basic_trigger_top.drc 0 → 100755
View file @ 45b75c34
Release 13.3 Drc O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 21 11:51:28 2012
drc -z basic_trigger_top.ncd basic_trigger_top.pcf
DRC detected 0 errors and 0 warnings.
installation/V1/basic_trigger/project/basic_trigger_top.ncd 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger_top.ngc 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger_top.ngd 0 → 100755
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//! **************************************************************************
// Written by: Map O.76xd on Wed Nov 21 11:50:22 2012
//! **************************************************************************
SCHEMATIC START;
COMP "fpga_o_blo_en" LOCATE = SITE "N3" LEVEL 1;
COMP "fpga_o_inv_en" LOCATE = SITE "P3" LEVEL 1;
COMP "fpga_o_en" LOCATE = SITE "N4" LEVEL 1;
COMP "led_err_o" LOCATE = SITE "F9" LEVEL 1;
COMP "pulse_i_rear<1>" LOCATE = SITE "W18" LEVEL 1;
COMP "pulse_i_rear<2>" LOCATE = SITE "Y18" LEVEL 1;
COMP "pulse_i_rear<3>" LOCATE = SITE "W17" LEVEL 1;
COMP "pulse_i_rear<4>" LOCATE = SITE "Y17" LEVEL 1;
COMP "pulse_i_rear<5>" LOCATE = SITE "Y16" LEVEL 1;
COMP "pulse_i_rear<6>" LOCATE = SITE "Y15" LEVEL 1;
COMP "level" LOCATE = SITE "L22" LEVEL 1;
COMP "led_pps_o" LOCATE = SITE "E6" LEVEL 1;
COMP "fpga_o_ttl_en" LOCATE = SITE "M3" LEVEL 1;
COMP "led_ttl_o" LOCATE = SITE "F8" LEVEL 1;
COMP "led_o_rear<1>" LOCATE = SITE "AB17" LEVEL 1;
COMP "led_o_rear<2>" LOCATE = SITE "AB19" LEVEL 1;
COMP "led_o_rear<3>" LOCATE = SITE "AA16" LEVEL 1;
COMP "led_o_rear<4>" LOCATE = SITE "AA18" LEVEL 1;
COMP "led_o_rear<5>" LOCATE = SITE "AB16" LEVEL 1;
COMP "led_o_rear<6>" LOCATE = SITE "AB18" LEVEL 1;
COMP "led_wr_ok_o" LOCATE = SITE "E5" LEVEL 1;
COMP "led_link_up_o" LOCATE = SITE "F7" LEVEL 1;
COMP "FPGA_CLK_N" LOCATE = SITE "G11" LEVEL 1;
COMP "FPGA_CLK_P" LOCATE = SITE "H12" LEVEL 1;
COMP "pulse_o_rear<1>" LOCATE = SITE "V1" LEVEL 1;
COMP "pulse_o_rear<2>" LOCATE = SITE "U1" LEVEL 1;
COMP "pulse_o_rear<3>" LOCATE = SITE "T2" LEVEL 1;
COMP "pulse_o_rear<4>" LOCATE = SITE "T1" LEVEL 1;
COMP "pulse_o_rear<5>" LOCATE = SITE "R1" LEVEL 1;
COMP "pulse_o_rear<6>" LOCATE = SITE "P2" LEVEL 1;
COMP "led_pw_o" LOCATE = SITE "F10" LEVEL 1;
COMP "pulse_i_front<1>" LOCATE = SITE "T3" LEVEL 1;
COMP "pulse_i_front<2>" LOCATE = SITE "U4" LEVEL 1;
COMP "pulse_i_front<3>" LOCATE = SITE "W3" LEVEL 1;
COMP "pulse_i_front<4>" LOCATE = SITE "W4" LEVEL 1;
COMP "pulse_i_front<5>" LOCATE = SITE "V3" LEVEL 1;
COMP "pulse_i_front<6>" LOCATE = SITE "U3" LEVEL 1;
COMP "inv_i<1>" LOCATE = SITE "Y1" LEVEL 1;
COMP "inv_i<2>" LOCATE = SITE "Y2" LEVEL 1;
COMP "inv_i<3>" LOCATE = SITE "AA1" LEVEL 1;
COMP "inv_i<4>" LOCATE = SITE "AA2" LEVEL 1;
COMP "inv_o<1>" LOCATE = SITE "J1" LEVEL 1;
COMP "inv_o<2>" LOCATE = SITE "K2" LEVEL 1;
COMP "inv_o<3>" LOCATE = SITE "K1" LEVEL 1;
COMP "inv_o<4>" LOCATE = SITE "L1" LEVEL 1;
COMP "led_o_front<1>" LOCATE = SITE "H3" LEVEL 1;
COMP "led_o_front<2>" LOCATE = SITE "J4" LEVEL 1;
COMP "led_o_front<3>" LOCATE = SITE "J3" LEVEL 1;
COMP "led_o_front<4>" LOCATE = SITE "K3" LEVEL 1;
COMP "led_o_front<5>" LOCATE = SITE "L4" LEVEL 1;
COMP "led_o_front<6>" LOCATE = SITE "L3" LEVEL 1;
COMP "manual_rst_n_o" LOCATE = SITE "T22" LEVEL 1;
COMP "switch_i" LOCATE = SITE "F22" LEVEL 1;
COMP "pulse_o_front<1>" LOCATE = SITE "D1" LEVEL 1;
COMP "pulse_o_front<2>" LOCATE = SITE "E1" LEVEL 1;
COMP "pulse_o_front<3>" LOCATE = SITE "F2" LEVEL 1;
COMP "pulse_o_front<4>" LOCATE = SITE "F1" LEVEL 1;
COMP "pulse_o_front<5>" LOCATE = SITE "G1" LEVEL 1;
COMP "pulse_o_front<6>" LOCATE = SITE "H2" LEVEL 1;
SCHEMATIC END;
installation/V1/basic_trigger/project/basic_trigger_top.prj 0 → 100755
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vhdl work "../../ctdah_lib/rtl/gc_ff.vhd"
vhdl work "../../ctdah_lib/rtl/gc_simple_monostable.vhd"
vhdl work "../../ctdah_lib/rtl/gc_debouncer.vhd"
vhdl work "../../ctdah_lib/rtl/ctdah_pkg.vhd"
vhdl work "../rtl/basic_trigger_core.vhd"
vhdl work "../rtl/basic_trigger_top.vhd"
installation/V1/basic_trigger/project/basic_trigger_top.ptwx 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger_top.twx 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger_top.unroutes 0 → 100755
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Release 13.3 - par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 21 11:50:43 2012
All signals are completely routed.
installation/V1/basic_trigger/project/basic_trigger_top.ut 0 → 100755
View file @ 45b75c34
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:10
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullUp
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
installation/V1/basic_trigger/project/basic_trigger_top.xpi 0 → 100755
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PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF
installation/V1/basic_trigger/project/basic_trigger_top.xst 0 → 100755
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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn basic_trigger_top.prj
-ofn basic_trigger_top
-ofmt NGC
-p xc6slx45t-3-fgg484
-top basic_trigger_top
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
installation/V1/basic_trigger/project/basic_trigger_top_bitgen.xwbt 0 → 100755
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INTSTYLE=ise
INFILE=/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.ncd
OUTFILE=/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project/basic_trigger_top.bit
FAMILY=Spartan6
PART=xc6slx45t-3fgg484
WORKINGDIR=/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/project
LICENSE=WebPack
USER_INFO=205164259_0_0_654
installation/V1/basic_trigger/project/basic_trigger_top_guide.ncd 0 → 100755
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installation/V1/basic_trigger/project/basic_trigger_top_map.map 0 → 100755
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Release 13.3 Map O.76xd (lin)
Xilinx Map Application Log File for Design 'basic_trigger_top'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o basic_trigger_top_map.ncd basic_trigger_top.ngd
basic_trigger_top.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Nov 21 11:50:06 2012
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:f259d460) REAL time: 9 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:f259d460) REAL time: 10 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f259d460) REAL time: 10 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:7e6de904) REAL time: 12 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:7e6de904) REAL time: 12 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:7e6de904) REAL time: 12 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:7e6de904) REAL time: 12 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:7e6de904) REAL time: 12 secs
Phase 9.8 Global Placement
.................................
.....................
Phase 9.8 Global Placement (Checksum:8eb769c7) REAL time: 13 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:8eb769c7) REAL time: 13 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:2a0a8deb) REAL time: 14 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:2a0a8deb) REAL time: 14 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:fc7e585) REAL time: 14 secs
Total REAL time to Placer completion: 15 secs
Total CPU time to Placer completion: 14 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 249 out of 54,576 1%
Number used as Flip Flops: 249
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 596 out of 27,288 2%
Number used as logic: 572 out of 27,288 2%
Number using O6 output only: 320
Number using O5 output only: 180
Number using O5 and O6: 72
Number used as ROM: 0
Number used as Memory: 8 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 8
Number using O6 output only: 8
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 16
Number with same-slice register load: 4
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 199 out of 6,822 2%
Nummber of MUXCYs used: 384 out of 13,644 2%
Number of LUT Flip Flop pairs used: 618
Number with an unused Flip Flop: 377 out of 618 61%
Number with an unused LUT: 22 out of 618 3%
Number of fully used LUT-FF pairs: 219 out of 618 35%
Number of unique control sets: 17
Number of slice register sites lost
to control set restrictions: 23 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 59 out of 296 19%
Number of LOCed IOBs: 59 out of 59 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.84
Peak Memory Usage: 284 MB
Total REAL time to MAP completion: 16 secs
Total CPU time to MAP completion: 15 secs
Mapping completed.
See MAP report file "basic_trigger_top_map.mrp" for details.
installation/V1/basic_trigger/project/basic_trigger_top_ngdbuild.xrpt 0 → 100755
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin" product="ISE" version="13.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Wed Nov 21 11:50:02 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/13.3/ISE_DS/ISE/"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/13.3/ISE_DS/ISE//bin/lin:/usr/lib/lightdm/lightdm:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/opt/modelsim_10/bin:/opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/:/opt/Xilinx/13.3/ISE_DS/PlanAhead/bin/:/media/BACKUP/scripts"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XIL_PAR_DESIGN_CHECK_VERBOSE"/>
<item stringID="value" value="1"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="/home/carlos/.Xilinx/xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/13.3/ISE_DS/ISE//lib/lin"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 11.10"/>
</item>
<item stringID="User_EnvHost" value="carlos-VAIO"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz"/>
<item stringID="speed" value="1199.000 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx45t-fgg484-3"/>
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/constraints/FPGAbank.ucf"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="12"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="236"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="192"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="42"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="216"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="30"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="354"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="39"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="192"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="12"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="236"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="192"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="42"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="216"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="30"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="354"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="39"/>
<item dataType="int" stringID="NGDBUILD_NUM_PLL_ADV" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="192"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>
installation/V1/basic_trigger/project/basic_trigger_top_summary.xml 0 → 100755
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="7">
<CmdHistory>
</CmdHistory>
</DesignSummary>
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<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="basic_trigger" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/basic_trigger_top - Behavioral |media|BACKUP|CERN|contrib|ohwr-git|conv-ttl-blo|hdl|basic_trigger|rtl|basic_trigger_top.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>../constraints/FPGAbank.ucf (/media/BACKUP/CERN/installation/V1/basic_trigger/constraints/FPGAbank.ucf)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002a5000000020000000000000000000000000200000064ffffffff000000810000000300000002000002a50000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>../constraints/FPGAbank.ucf (/media/BACKUP/CERN/installation/V1/basic_trigger/constraints/FPGAbank.ucf)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Generate Target PROM/ACE File</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000028f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000028f0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Target PROM/ACE File</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000075f000000040101000100000000000000000000000064ffffffff000000810000000000000004000001810000000100000000000001170000000100000000000000ab00000001000000000000041c0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>../../ctdah_lib/rtl/ctdah_pkg.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>work</ClosedNode>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000176000000010001000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/trigger_top_tb - behavior |media|BACKUP|CERN|contrib|ohwr-git|conv-ttl-blo|hdl|basic_trigger|test|basic_trigger_top_tb.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>trigger_top_tb - behavior (/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/test/basic_trigger_top_tb.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000236000000020000000000000000000000000200000064ffffffff000000810000000300000002000002360000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>trigger_top_tb - behavior (/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/basic_trigger/test/basic_trigger_top_tb.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002cb000000010000000100000000000000000000000064ffffffff000000810000000000000001000002cb0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000263000000010000000100000000000000000000000064ffffffff000000810000000000000001000002630000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000018e0000011d01000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" />
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000029e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000029e0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
</Project>
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>578</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1598</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1598</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>1485</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>8.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>9.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>11.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>11.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>11.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>11.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>11.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>11.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>11.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>6.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0247</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
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######################################################################
##
## Filename: trigger_top_tb.fdo
## Created on: Wed Oct 24 11:32:39 AM CEST 2012
##
## Auto generated by Project Navigator for Behavioral Simulation
##
## ---------------------DO NOT EDIT THIS FILE-------------------------
## You may want to add additional commands to control the simulation
## in the user specific do file (<module>.udo) which is automatically
## generated in the project directory and will not be removed on
## subsequent simulation flows run from Project Navigator.
## ---------------------DO NOT EDIT THIS FILE-------------------------
##
######################################################################
#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "../ctdah_lib/rtl/gc_ff.vhd"
vcom -explicit -93 "../ctdah_lib/rtl/gc_simple_monostable.vhd"
vcom -explicit -93 "../ctdah_lib/rtl/gc_debouncer.vhd"
vcom -explicit -93 "../ctdah_lib/rtl/ctdah_pkg.vhd"
vcom -explicit -93 "rtl/basic_trigger_core.vhd"
vcom -explicit -93 "rtl/basic_trigger_top.vhd"
vcom -explicit -93 "test/basic_trigger_top_tb.vhd"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ps -lib work work.trigger_top_tb
#
# Source the wave do file
#
do {trigger_top_tb_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {trigger_top_tb.udo}
#
# Run simulation for this time
#
run 1000ns
#
# End
#
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######################################################################
##
## Filename: trigger_top_tb.udo
## Created on: Tue Oct 23 04:18:59 PM CEST 2012
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
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