added second presentation file

50bce627 · Theodor-Adrian Stana · c50b4994 · 50bce627
Commit 50bce627 authored Nov 13, 2013 by Theodor-Adrian Stana
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pres-2.txt design-review/pres-2.txt +43 -0

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--- a/design-review/pres-2.txt
+++ b/design-review/pres-2.txt
+1. Review discussion
+
+1.1. Folder structure
+
+1.2. reset_gen
+- reset bit already available, only needs to be connected
+
+1.3. i2c_slave & glitch_filt
+- add synchronizer to glitch_filt
+- SCL line sampling
+-- nothing in I2C spec saying 'sample on rising edge'
+-- (tom, eva) sampled on falling edge to avoid incompliant masters
+-- (javier) tapped delay line makes design too complex
+- (tom) will change sda_o and sda_en_o assignment
+- (eva) agreed with clearer `falling' and `rising' signal naming
+- (eva) FSM seems clearer if the outputs are set in same process as
+the states
+
+1.4. vbcp_wb
+- watchdog addition (wait for 2.)
+
+1.5. ctb_pulse_gen
+
+1.6. multiboot
+- watchdog (wait for 2.)
+- no other additions?
+
+1.7. bicolor_led_ctrl
+
+
+1.8. top-level
+
+1.9. constraints
+- will add clock constraint to .ucf
+
+2. Block replacement proposal
+
+3. Add modules to own projects/general-cores
+
+3.1. MultiBoot to general-cores?
+3.2. VBCP bridge to own project
+
+4. Discuss about meeting with FE people