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Conv TTL Blocking
Commit 53c9ec7c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Started reimplementation of I2C bridge, i2c_slave unit works in simulation and synthesizes.

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hdl/i2c_to_wb_bridge/doc/Figures/I2C_drawings.svg deleted 100644 → 0
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hdl/i2c_to_wb_bridge/doc/i2cSpecs.tex deleted 100644 → 0
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hdl/i2c_to_wb_bridge/rtl/Manifest.py deleted 100644 → 0
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files = [
"i2c_slave_pkg.vhd",
"i2c_debounce.vhd",
"i2c_bit.vhd",
"bridge_regs.vhd",
"bridge.vhd",
"i2c_to_wb_bridge.vhd"
]
hdl/i2c_to_wb_bridge/rtl/bridge.vhd deleted 100644 → 0
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hdl/i2c_to_wb_bridge/rtl/bridge_regs.vhd deleted 100644 → 0
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hdl/i2c_to_wb_bridge/rtl/i2c_bit.vhd deleted 100644 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - behav
-- Project Name: Level Conversion Circuits
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit. It offers some
-- interrupting lines to the upper level (i2c_slave_core.vhd)
-- which is responsible for managing byte level transactions
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.1 - Module works with no reported issues.
-- 1.0 - Code revamped. Now is clearer and easier to read.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_bit is
port
(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC;
done_o : out STD_LOGIC
);
end i2c_bit;
architecture behav of i2c_bit is
component i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end component i2c_debouncer;
type t_state is (
R0_RESET,
S0_IDLE,
S1A_HIGH_TMP,
S1A_HIGH,
S1B_LOW_TMP,
S1B_LOW,
S2A_START_TMP,
S2A_START,
S2B_STOP_DETECT,
Q1_ERROR
);
-- It specifies the maximum number of stages that will be employed for
-- deglitching. Clocked with clk_i
constant c_MAX_GLITCH_DELAY : NATURAL := 6;
-- Three delay stages out of six
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111";
signal sda_deglitched : STD_LOGIC;
signal sda_deglitched_d1 : STD_LOGIC;
signal scl_deglitched : STD_LOGIC;
signal scl_deglitched_d1 : STD_LOGIC;
signal state : t_state;
signal scl_rising : STD_LOGIC;
signal scl_falling : STD_LOGIC;
begin
cmp_scl_debouncer: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => scl_i,
output => scl_deglitched,
glitch_mask => c_GLITCH_MASK
);
cmp_sda_debounce: i2c_debouncer
generic map
(
g_LENGTH => 6
)
port map
(
rst => rst_i,
clk => clk_i,
input => sda_i,
output => sda_deglitched,
glitch_mask => c_GLITCH_MASK
);
process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
sda_deglitched_d1 <= '0';
scl_deglitched_d1 <= '0';
else
sda_deglitched_d1 <= sda_deglitched;
scl_deglitched_d1 <= scl_deglitched;
end if;
end if;
end process;
-- This is the process that samples the scl for detecting
-- rise and falling edges
reg_proc: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
scl_falling <= '0';
scl_rising <= '0';
elsif (scl_deglitched = '0') and (scl_deglitched_d1 = '1') then
scl_falling <= '1';
elsif (scl_deglitched = '1') and (scl_deglitched_d1 = '0') then
scl_rising <= '1';
else
scl_falling <= '0';
scl_rising <= '0';
end if;
end if;
end process;
-- Combinatorial process to update the outputs.
p_comb_output: process(state)
begin
start_o <= '0';
pause_o <= '0';
rcved_o <= '0';
done_o <= '0';
case state is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1A_HIGH =>
rcved_o <= '1';
done_o <= '1';
when S1B_LOW =>
rcved_o <= '0';
done_o <= '1';
when S2A_START =>
start_o <= '1';
done_o <= '1';
when S2B_STOP_DETECT =>
pause_o <= '1';
done_o <= '1';
when Q1_ERROR =>
null;
when others =>
null;
end case;
end process p_comb_output;
-- The fsm of this module, later on the sda sampled line is
-- validated in the falling edge of scl.
p_fsm: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
state <= R0_RESET;
elsif scl_falling = '1' then
-- After a detection of a falling edge we update the
-- detection of a '0', a '1' and a start condition.
case state is
when S1A_HIGH_TMP =>
state <= S1A_HIGH;
when S1B_LOW_TMP =>
state <= S1B_LOW;
when S2A_START_TMP =>
state <= S2A_START;
when others =>
state <= S0_IDLE;
end case;
elsif (scl_rising = '1') then
-- When a rising edge is detected we annotate the first value
-- in SDA: either a temporary '0' or '1'
if (sda_deglitched_d1 = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
end if;
else
-- When we are in high level of a scl cycle, we keep on updating
-- the FSM
if (scl_deglitched = '1') then
case state is
-- Just for random bit swapped coverage.
when S0_IDLE =>
if (sda_deglitched = '1') then
state <= S1A_HIGH_TMP;
else
state <= S1B_LOW_TMP;
end if;
when S1A_HIGH_TMP =>
if sda_deglitched = '0' then
-- The detection of the start condition will be reported
-- in the next SCL rising edge.
state <= S2A_START_TMP;
end if;
when S1B_LOW_TMP =>
if sda_deglitched = '1' then
-- The detection of the pause condition MUST be
-- reported immediately.
state <= S2B_STOP_DETECT;
end if;
when S2A_START_TMP =>
if (sda_deglitched = '1') then
--! This happens if the deglitching is not enough
state <= Q1_ERROR;
end if;
when others =>
state <= S0_IDLE;
end case;
else
if (scl_deglitched_d1 = '0') then
state <= S0_IDLE;
end if;
end if;
end if;
end if;
end process p_fsm;
end behav;
hdl/i2c_to_wb_bridge/rtl/i2c_debounce.vhd deleted 100644 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:11:43 10/25/2011
-- Design Name:
-- Module Name: i2c_debounce - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a I2C debouncer. The main difference is that it is
-- intended to filter out low glitches. That means the oppositive
-- from the previous version --debouncer.vhd.
-- This behaviour makes more sense compared on how I2C definition
-- resolves arbitration --conceptually the same as this module.
--
-- A '1' in the glitch_mask means that the bit should be studied.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_debouncer is
generic
(
g_LENGTH : NATURAL := 6
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
signal input_d0 : STD_LOGIC;
-- The first of this signal is already stable (ff'ed two times at [0])
signal delay : STD_LOGIC_VECTOR(g_LENGTH - 1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
input_d0 <= '0';
delay <= (others => '0');
else
input_d0 <= input;
delay(0) <= input_d0;
delay(g_length-1 downto 1) <= delay(g_length-2 downto 0);
end if;
end if;
end process;
p_output: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
output <= '1';
else
-- We can deglitch either zeros or ones
if ( (delay and glitch_mask) = glitch_mask
or (not(delay) and glitch_mask) = glitch_mask) then
output <= delay(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
end if;
end if;
end process p_output;
end Behavioral;
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hdl/i2c_to_wb_bridge/rtl/i2c_to_wb_bridge.vhd deleted 100644 → 0
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--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT CHANGED
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_to_wb_bridge - behav
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.all;
entity i2c_to_wb_bridge is
port
(
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
wb_master_stb_o : out std_logic;
wb_master_cyc_o : out std_logic;
wb_master_sel_o : out std_logic_vector(3 downto 0);
wb_master_we_o : out std_logic;
wb_master_dat_i : in std_logic_vector(31 downto 0);
wb_master_dat_o : out std_logic_vector(31 downto 0);
wb_master_adr_o : out std_logic_vector(15 downto 0);
wb_master_ack_i : in std_logic;
wb_master_rty_i : in std_logic;
wb_master_err_i : in std_logic;
wb_slave_stb_i : in std_logic;
wb_slave_cyc_i : in std_logic;
wb_slave_sel_i : in std_logic_vector(3 downto 0);
wb_slave_we_i : in std_logic;
wb_slave_dat_i : in std_logic_vector(31 downto 0);
wb_slave_dat_o : out std_logic_vector(31 downto 0);
wb_slave_adr_i : in std_logic_vector(3 downto 0);
wb_slave_ack_o : out std_logic;
wb_slave_rty_o : out std_logic;
wb_slave_err_o : out std_logic;
pf_wb_addr_o : out std_logic;
rd_done_o : out std_logic;
wr_done_o : out std_logic;
i2c_addr_i : in std_logic_vector(6 downto 0)
);
end i2c_to_wb_bridge;
architecture behav of i2c_to_wb_bridge is
component bridge is
generic
(
g_WB_CLK_PERIOD : time := 50 ns
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
-- I2C pins
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- Registers
CTR0_i : in std_logic_vector (r_CTR0'a_length - 1 downto 0);
LT_o : out std_logic_vector (r_LT'a_length - 1 downto 0);
DRXA_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
DRXB_o : out std_logic_vector (r_DRX'a_length - 1 downto 0);
-- Alarms for controlling the i2c states
pf_wb_addr_o : out std_logic;
pf_wb_data_i : in std_logic_vector(31 downto 0);
rd_done_o : out std_logic;
wr_done_o : out std_logic
);
end component bridge;
component bridge_regs is
port
(
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
-- These are the registers offers to others modules of the FPGA
wb_slave_we_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
-- These are the registers that are offered to the i2c slave core
ctr0_o : out STD_LOGIC_VECTOR (31 downto 0);
lt_i : in STD_LOGIC_VECTOR (31 downto 0);
drxa_i : in STD_LOGIC_VECTOR (31 downto 0);
drxb_i : in STD_LOGIC_VECTOR (31 downto 0);
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
rd_done_i : in STD_LOGIC;
wr_done_i : in STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0)
);
end component bridge_regs;
signal ctr0 : std_logic_vector(r_CTR0'a_length - 1 downto 0);
signal lt : std_logic_vector(r_LT'a_length - 1 downto 0);
signal drxa : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal drxb : std_logic_vector(r_DRX'a_length - 1 downto 0);
signal pf_wb_addr : std_logic;
signal pf_wb_data : std_logic_vector(31 downto 0);
signal rd_done : std_logic;
signal wr_done : std_logic;
begin
pf_wb_addr_o <= pf_wb_addr;
rd_done_o <= rd_done;
wr_done_o <= wr_done;
cmp_bridge: bridge
generic map
(
g_wb_clk_period => 8 ns
)
port map
(
clk_i => clk_i,
rst_i => rst_i,
sda_en_o => sda_en_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_en_o,
scl_i => scl_i,
scl_o => scl_o,
CTR0_i => ctr0,
LT_o => lt,
DRXA_o => drxa,
DRXB_o => drxb,
pf_wb_addr_o => pf_wb_addr,
pf_wb_data_i => pf_wb_data,
rd_done_o => rd_done,
wr_done_o => wr_done
);
cmp_bridge_regs: bridge_regs
port map
(
pf_wb_addr_i => pf_wb_addr,
pf_wb_data_o => pf_wb_data,
rd_done_i => rd_done,
wr_done_i => wr_done,
wb_rst_i => rst_i,
wb_clk_i => clk_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o,
wb_master_dat_i => wb_master_dat_i,
wb_master_dat_o => wb_master_dat_o,
wb_master_adr_o => wb_master_adr_o,
wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i,
wb_slave_we_i => wb_slave_we_i,
wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i,
wb_slave_dat_i => wb_slave_dat_i,
wb_slave_dat_o => wb_slave_dat_o,
wb_slave_adr_i => wb_slave_adr_i,
wb_slave_ack_o => wb_slave_ack_o,
wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o,
ctr0_o => ctr0,
lt_i => lt,
drxa_i => drxa,
drxb_i => drxb,
i2c_addr_i => i2c_addr_i
);
end behav;
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../top"
]
}
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project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/i2c_to_wb_bridge/test/i2c_bit_tb.vhd deleted 100644 → 0
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--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
-- Design Name: i2c slave to wb_master testbench
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
library work;
USE ieee.std_logic_1164.ALL;
USE work.i2c_slave_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
wb_clk_i : IN std_logic;
sda_i : IN std_logic;
scl_i : IN std_logic;
done_o : OUT std_logic;
start_o : OUT std_logic;
pause_o : OUT std_logic;
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
signal sda_i : std_logic := '0';
signal scl_i : std_logic := '0';
--Outputs
signal start_o : std_logic;
signal pause_o : std_logic;
signal rcved_o : std_logic;
signal done_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (rst_i => rst_i,
wb_clk_i => wb_clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o,
pause_o => pause_o,
rcved_o => rcved_o,
done_o => done_o);
-- Clock process definitions
wb_clk_i_process :process
begin
wb_clk_i <= '1';
wait for wb_clk_i_period/2;
wb_clk_i <= '0';
wait for wb_clk_i_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_i_period*2;
rst_i <= '1';
wait for wb_clk_i_period*2;
rst_i <= '0';
wait for wb_clk_i_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 0 to 6 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
begin
init_cond;
rst;
start;
addr_send("0101100");
pause;
wait;
end process;
END;
hdl/i2c_to_wb_bridge/test/i2c_master_driver.vhd deleted 100644 → 0
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hdl/i2c_to_wb_bridge/test/i2c_slave_top_tb.vhd deleted 100644 → 0
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hdl/i2c_to_wb_bridge/test/i2c_tb_pkg.vhd deleted 100644 → 0
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library IEEE;
library work;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
package i2c_tb_pkg is
--! Clock period definitions
constant c_WB_CLK_PERIOD : time := 50 ns; -- @ 20 MHz
constant c_SCL_I_PERIOD : time := 10000 ns; -- @ 400 KHz
--! Will be used as the LSB of the I2C
constant c_VME_SLOT : UNSIGNED(4 downto 0) := "11110";
--! Length of some buses
constant c_WR_DATA_LENGTH : NATURAL := 32;
constant c_RD_DATA_LENGTH : NATURAL := 32;
constant c_WB_ADDR_LENGTH : NATURAL := 16;
component i2c_slave_top is
port (sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC;
wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
rd_done_o : out STD_LOGIC;
wr_done_o : out STD_LOGIC;
i2c_addr_i : in STD_LOGIC_VECTOR(6 downto 0));
end component;
component i2c_master_driver is
generic(g_WR_DATA_LENGTH : NATURAL := c_WR_DATA_LENGTH;
g_RD_DATA_LENGTH : NATURAL := c_RD_DATA_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WB_ADDR_LENGTH;
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
scl_master_o : out STD_LOGIC;
i2c_addr_op_i : in STD_LOGIC_VECTOR(7 downto 0);
wishbone_addr_i : in STD_LOGIC_VECTOR(g_WB_ADDR_LENGTH - 1 downto 0);
wr_data_i : in STD_LOGIC_VECTOR(g_WR_DATA_LENGTH - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(g_RD_DATA_LENGTH - 1 downto 0);
start_i : in STD_LOGIC;
start_done_o : out STD_LOGIC;
pause_i : in STD_LOGIC;
pause_done_o : out STD_LOGIC;
write_i : in STD_LOGIC;
write_done_o : out STD_LOGIC;
read_i : in STD_LOGIC;
read_done_o : out STD_LOGIC);
end component;
type I2C_master_driver_ctrl is
record
START : STD_LOGIC;
PAUSE : STD_LOGIC;
WRITE : STD_LOGIC;
READ : STD_LOGIC;
end record;
constant c_I2C_master_driver_ctrl_default : I2C_master_driver_ctrl
:=(START => '0',
PAUSE => '0',
WRITE => '0',
READ => '0');
end i2c_tb_pkg;
package body i2c_tb_pkg is
end i2c_tb_pkg;
hdl/i2c_to_wb_bridge/test/log/i2c_master_driver.txt deleted 100644 → 0
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1 OK WRITE [ADDRESS|0]
1 OK WRITE WISHBONE HIGH
1 OK WRITE WISHBONE LOW
1 OK WRITE READ DATA 0
1 OK WRITE READ DATA 1
1 OK WRITE READ DATA 2
1 OK WRITE READ DATA 3
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
hdl/i2c_to_wb_bridge/top/Manifest.py deleted 100644 → 0
View file @ 9a04b242
files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../rtl",
]
}
hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.ucf deleted 100644 → 0
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hdl/i2c_to_wb_bridge/top/conv_ttl_blo_v2.vhd deleted 100644 → 0
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hdl/pulse_generator/rtl/Manifest.py
View file @ 53c9ec7c
files = [
"pulse_generator.vhd"
]
files = "pulse_generator.vhd"
modules = {
"local" : [
"../../glitch_filt",
"../../../../ip_cores/general-cores"
]
}
hdl/pulse_generator/rtl/pulse_generator.vhd
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hdl/pulse_generator/sim/run.do
View file @ 53c9ec7c
vlib work
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../old_rep_test/rtl/pulse_gen.vhd"
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/pulse_generator.vhd"
vcom -explicit -93 "testbench.vhd"
......
hdl/pulse_generator/sim/testbench.vhd
View file @ 53c9ec7c
......@@ -63,12 +63,13 @@ architecture behav of testbench is
generic
(
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 6
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_type_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
);
......@@ -93,6 +94,7 @@ architecture behav of testbench is
signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
signal ptype : std_logic;
--==============================================================================
-- architecture begin
......@@ -104,14 +106,15 @@ begin
generic map
(
g_pulse_width => 125,
g_glitch_filt_len => 6
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
trig_i => actual_trig,
pulse_o => pulse
clk_i => clk,
rst_n_i => rst_n,
pulse_type_i => ptype,
trig_i => actual_trig,
pulse_o => pulse
);
-- CLOCK GENERATION
......@@ -150,16 +153,22 @@ begin
rst_n_i => rst_n,
pulse_o => trig
);
actual_trig <= '1'; --trig;
actual_trig <= trig;
actual_pulse <= pulse;
lvl_n <= not lvl;
cmp_pulse_gen2: pulse_gen
generic map
(
g_pwidth => 1033,
g_freq => 2066
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_o => ptype
);
lvl <= '1';
--trig <= '1';
end architecture behav;
--==============================================================================
-- architecture end
......
hdl/pulse_generator/sim/transcript
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hdl/pulse_generator/sim/wave.do
View file @ 53c9ec7c
......@@ -4,15 +4,21 @@ add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/ptype
add wave -noupdate /testbench/pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/glitch_filt
add wave -noupdate /testbench/DUT/pulse
add wave -noupdate /testbench/DUT/pulse_reject
add wave -noupdate /testbench/DUT/width_cnt
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/pulse_type1
add wave -noupdate /testbench/DUT/pulse_type1_d0
add wave -noupdate /testbench/DUT/pulse_type1_d1
add wave -noupdate /testbench/DUT/pulse_type1_d2
add wave -noupdate /testbench/DUT/pulse_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {12112676 ps} 0}
WaveRestoreCursors {{Cursor 2} {16080000 ps} 0}
configure wave -namecolwidth 233
configure wave -valuecolwidth 91
configure wave -valuecolwidth 132
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
......@@ -25,4 +31,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {105 us}
WaveRestoreZoom {0 ps} {102112676 ps}
hdl/release/syn/Makefile
View file @ 53c9ec7c
......@@ -42,7 +42,100 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo_v2.xise
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 53c9ec7c
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hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 53c9ec7c
This diff is collapsed.
hdl/release/top/conv_ttl_blo_v2.ucf
View file @ 53c9ec7c
This diff is collapsed.
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 53c9ec7c
This diff is collapsed.
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