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Conv TTL Blocking
Commit 6016b221 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Merged with I2C debug/fix branch.

parents a2f05fe6 e484a065
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captures/
*.bak
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
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hdl/IMAGES/image1/project/image1.gise deleted 100644 → 0
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hdl/IMAGES/image1/project/image1.xise
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hdl/IMAGES/image1/rtl/image1_core.vhd
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......@@ -7,6 +7,7 @@
-- unit name: image1_core.vhd
--
-- author: Carlos Gil Soriano (gilsoriano@gmail.com)
-- Theodor-Adrian Stana (t.stana@cern.ch)
--
-- date: 01-12-2012
--
......@@ -143,6 +144,12 @@ architecture Behavioral of image1_core is
signal s_leds_array_image1 : t_leds_array;
signal s_led_state_array : t_led_state_array(
c_NB_ARRAY_LEDS - 1 downto 0);
signal i2c_rd_done : std_logic;
signal i2c_wr_done : std_logic;
signal i2c_up : std_logic;
--
--
......@@ -152,7 +159,9 @@ architecture Behavioral of image1_core is
--
signal trigleds : std_logic_vector(5 downto 0);
signal leds_from_trig : std_logic_vector(5 downto 0);
signal sda_dummy : std_logic;
signal sda_dummy_n : std_logic;
-- signal s_check_cfg : BOOLEAN;
begin
......@@ -176,12 +185,12 @@ begin
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => c_CLKFBOUT_MULT,
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => c_CLKOUTA_DIVIDE, CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => c_CLKOUTB_DIVIDE, CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT0_DIVIDE => 20, CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => c_CLKIN_PERIOD,
REF_JITTER => 0.010)
port map (
......@@ -265,9 +274,9 @@ begin
-- !!!!!
led_front_n <= leds_from_trig or (not trigleds);
-- led_front_n <= "111000";
led_front_n <= not trigleds;
......@@ -278,8 +287,6 @@ begin
g_LED_BLINKING_LENGTH => c_LED_BLINKING_LENGTH)
port map(clk_i => s_clk.SYS_B,
rst_i => s_rst.SYS_B(c_RST_B_CLKS - 1),
led_pw_o => s_leds_array_image1.top.PWR,
led_err_o => open,
led_ttl_o => s_leds_array_image1.top.TTL_N,
fpga_o_en => fpga_o_en,
fpga_o_ttl_en => fpga_o_ttl_en,
......@@ -301,10 +308,7 @@ begin
led_o_rear => led_rear_n,
led_link_up_o => s_leds_array_image1.middle.WR_LINK,
led_pps_o => s_leds_array_image1.middle.WR_GMT,
led_wr_ok_o => s_leds_array_image1.middle.WR_OK,
led_o_rear => open, --led_rear_n,
inv_i => inv_i_n,
inv_o => inv_o);
......@@ -326,16 +330,22 @@ begin
s_slave_i(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
s_slave_i(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
i2c_slave_o.sda_o <= sda_dummy;
sda_dummy_n <= not sda_dummy;
led_rear_n <= (others => sda_dummy_n);
inst_i2c_slave: i2c_slave_top
port map(sda_oen => i2c_slave_o.SDA_OE,
sda_i => i2c_slave_i.SDA_I,
sda_o => i2c_slave_o.SDA_O,
sda_o => sda_dummy, -- i2c_slave_o.SDA_O,
scl_oen => i2c_slave_o.SCL_OE,
scl_i => i2c_slave_i.SCL_I,
scl_o => i2c_slave_o.SCL_O,
wb_clk => s_clk.SYS_A,
wb_clk_i => s_clk.SYS_A,
wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_master_stb_o => s_slave_i(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => s_slave_i(c_MASTER_I2C_SLAVE).cyc,
......@@ -358,11 +368,29 @@ begin
wb_slave_rty_o => s_master_i(c_SLAVE_I2C_SLAVE).rty,
wb_slave_err_o => s_master_i(c_SLAVE_I2C_SLAVE).err,
pf_wb_addr_o => open,
rd_done_o => open,
wr_done_o => open,
rd_done_o => i2c_rd_done,
wr_done_o => i2c_wr_done,
i2c_addr_i => s_i2c_addr
);
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up: process (s_clk.sys_a) is
begin
if rising_edge(s_clk.sys_a) then
if (s_rst_n = '0') then
i2c_up <= '0';
elsif (i2c_rd_done = '1') or (i2c_wr_done = '1') then
i2c_up <= '1';
end if;
end if;
end process p_i2c_up;
--
--
-- inst_m25p32: m25p32_top
......@@ -401,6 +429,11 @@ begin
-- wb_err_o => s_master_i(c_SLAVE_MULTIBOOT).err);
--
--
s_master_i(c_SLAVE_I2C_SLAVE).stall <= '0';
s_master_i(c_SLAVE_I2C_SLAVE).int <= '0';
s_master_i(c_slave_trigleds_wb).int <= '0';
......@@ -443,6 +476,13 @@ begin
trigleds_reg_bits_o => trigleds
);
s_leds_array_image1.top.pwr <= '1';
s_leds_array_image1.middle.wr_ok <= '0';
s_leds_array_image1.middle.wr_link <= '0';
s_leds_array_image1.middle.wr_addr <= '0';
--! Here are organized in the same disposition as in the front panel.
--! Take a look to image1_led_pkg.vhd for the correct order for
--! bicolor_led_ctrl
......@@ -456,20 +496,20 @@ begin
when s_leds_array_image1.top.TTL_N = '1'
else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_I2C) <= f_LED_STATE(c_LED_COLOR_I2C)
when s_leds_array_image1.top.I2C = '1'
else f_LED_STATE(c_LED_OFF);
when i2c_up = '1'
else f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_OK) <= f_LED_STATE(c_LED_COLOR_WR_OK)
when s_leds_array_image1.middle.WR_OK = '1'
else f_LED_STATE(c_LED_OFF);
else f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_LINK) <= f_LED_STATE(c_LED_COLOR_WR_LINK)
when s_leds_array_image1.middle.WR_LINK = '1'
else f_LED_STATE(c_LED_OFF);
else f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_GMT) <= f_LED_STATE(c_LED_COLOR_WR_GMT)
when s_leds_array_image1.middle.WR_GMT = '1'
else f_LED_STATE(c_LED_OFF);
else f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_ADDR) <= f_LED_STATE(c_LED_COLOR_WR_ADDR)
when s_leds_array_image1.middle.WR_ADDR = '1'
else f_LED_STATE(c_LED_OFF);
else f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_MULTICAST3) <= f_LED_STATE(c_LED_COLOR_MULTICAST3)
when s_leds_array_image1.bottom.MULTICAST(3) = '1'
else f_LED_STATE(c_LED_OFF);
......@@ -484,7 +524,8 @@ begin
else f_LED_STATE(c_LED_OFF);
s_rst_n <= not(s_rst.SYS_A(c_RST_A_CLKS - 1));
inst_bicolor_led_ctrl: bicolor_led_ctrl
generic map(g_NB_COLUMN => c_NB_COLUMN,
g_NB_LINE => c_NB_LINE,
......
hdl/IMAGES/image1/rtl/image1_led_pkg.vhd
View file @ 6016b221
......@@ -68,18 +68,18 @@ package image1_led_pkg is
constant c_LED_NB_MULTICAST2 : NATURAL := 10;
constant c_LED_NB_MULTICAST3 : NATURAL := 11;
constant c_LED_COLOR_PWR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_ERR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_RED);
constant c_LED_COLOR_TTL_N : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_I2C : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_OK : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_LINK : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_GMT : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_WR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST3 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST2 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST1 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_MULTICAST0 : STD_LOGIC_VECTOR(1 downto 0) := not(c_LED_GREEN);
constant c_LED_COLOR_PWR : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN; --not(c_LED_GREEN);
constant c_LED_COLOR_ERR : STD_LOGIC_VECTOR(1 downto 0) := c_LED_RED;
constant c_LED_COLOR_TTL_N : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_I2C : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_OK : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_LINK : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_GMT : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_WR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST3 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST2 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST1 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
constant c_LED_COLOR_MULTICAST0 : STD_LOGIC_VECTOR(1 downto 0) := c_LED_GREEN;
type t_leds_array_top is
......
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 6016b221
......@@ -127,8 +127,6 @@ package image1_pkg is
port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
......@@ -150,12 +148,6 @@ package image1_pkg is
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component;
......@@ -170,7 +162,7 @@ package image1_pkg is
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
......@@ -205,7 +197,7 @@ package image1_pkg is
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
......@@ -237,7 +229,7 @@ package image1_pkg is
--! Set it up accordingly.
g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
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hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
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......@@ -20,7 +20,7 @@ package image1_top_tb_pkg is
:= work.image1_pkg.c_NUMBER_OF_CHANNELS;
component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
......@@ -37,12 +37,12 @@ package image1_top_tb_pkg is
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(6 downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(6 downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(6 downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(6 downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
......
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @ 6016b221
......@@ -9,3 +9,7 @@
2 OK WRITE READ DATA 1
2 OK WRITE READ DATA 2
2 OK WRITE READ DATA 3
3 OK READ [ADDRESS|0]
3 OK READ WISHBONE HIGH
3 OK READ WISHBONE LOW
3 OK READ [ADDRESS|0]
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 6016b221
......@@ -36,8 +36,6 @@ entity basic_trigger_top is
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
......@@ -54,11 +52,7 @@ entity basic_trigger_top is
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
--! WR LEDs not to let them ON
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)
);
......@@ -85,8 +79,7 @@ architecture Behavioral of basic_trigger_top is
type delay_array is array (g_NUMBER_OF_CHANNELS downto 1)
of STD_LOGIC_VECTOR(3 downto 0);
signal s_pulse_i_reg : delay_array;
signal s_locked : STD_LOGIC;
component basic_trigger_core is
generic(g_CLK_PERIOD : TIME := g_CLK_PERIOD;
g_OUTPUT_PULSE_LENGTH : TIME := g_OUTPUT_PULSE_LENGTH;
......@@ -109,14 +102,7 @@ begin
--! 1 means TTL_N Switch DOWN
s_level <= level_i;
led_pw_o <= '0';
led_err_o <= '1';
led_ttl_o <= not(s_level);
led_link_up_o <= not(s_locked);
led_pps_o <= '1';
led_wr_ok_o <= '1';
led_ttl_o <= s_level;
-- pulse signal assignments
s_pulse_i_front <= pulse_i_front when (s_level = '0') else
......
hdl/bicolor_led_ctrl/bicolor_led_ctrl.vhd
View file @ 6016b221
......@@ -227,10 +227,10 @@ begin
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN;
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else
(line_ctrl and intensity_ctrl);-- when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 6016b221
......@@ -29,7 +29,7 @@ use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
entity i2c_regs is
port (wb_clk : in STD_LOGIC;
port (wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
......@@ -99,15 +99,19 @@ signal s_wb_master_we_o : STD_LOGIC;
signal s_wb_master_ack_retries : STD_LOGIC_VECTOR(c_RETRY_LENGTH - 1 downto 0)
:= (others => '0');
signal s_wb_addr_rd : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal s_wb_addr_rd : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
attribute keep : string;
signal wbm_dat_out : std_logic_vector(31 downto 0);
attribute keep of wbm_dat_out : signal is "true";
begin
wb_master_we_o <= s_wb_master_we_o;
s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i);
wb_master_we_o <= s_wb_master_we_o;
s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i);
wb_master_data_o <= wbm_dat_out;
wb_slave_ack_o <= s_wb_slave_ack;
wb_slave_rty_o <= s_wb_slave_rty;
......@@ -117,10 +121,10 @@ begin
pf_wb_data_o <= s_DTX;
--! @brief Process that controls the retries of the wishbone interface
--! @param wb_clk Main clock
p_wb_master_retries: process (wb_clk)
--! @param wb_clk_i Main clock
p_wb_master_retries: process (wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if i2c_master_WB_BASIC_fsm = S3_WB_ACK then
s_wb_master_ack_retries(0) <= '1';
for i in 1 to c_RETRY_LENGTH - 1 loop
......@@ -139,63 +143,86 @@ begin
--! read/written when repetitions of the
--! wishbone master interface happen.
--! @param i2c_master_WB_BASIC_fsm fsm of the wishone master interface
wbmaster_comb_proc: process(i2c_master_WB_BASIC_fsm)
wbmaster_comb_proc : process(wb_clk_i)
-- function f_le2be(val : std_logic_vector(31 downto 0))
-- return std_logic_vector(31 downto 0) is
-- variable retval;
-- begin
-- retval( 7 downto 0) <= val(31 downto 24);
-- retval(15 downto 8) <= val(23 downto 16);
-- retval(23 downto 16) <= val(15 downto 8);
-- retval(31 downto 24) <= val(7 downto 0);
--
-- return retval;
-- end function;
begin
s_wb_master_we_o <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0');
wb_master_addr_o <= (others => '0');
case i2c_master_WB_BASIC_fsm is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd(15 downto 0) <= DRXA_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
when S1N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_data_i;
when S2P_WB_WR_RQT =>
null;
when S2_WB_WR_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= DRXA_i;
wb_master_addr_o(15 downto 0) <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= DRXA_i;
wb_master_addr_o(15 downto 0) <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
null;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
s_wb_master_we_o <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wbm_dat_out <= (others => '0');
wb_master_addr_o <= (others => '0');
s_dtx <= (others => '0');
else
case i2c_master_WB_BASIC_fsm is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd <= DRXA_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
when S1N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_data_i;
when S2P_WB_WR_RQT =>
null;
when S2_WB_WR_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wbm_dat_out <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wbm_dat_out <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
-- null;
wb_master_cyc_o <= '0';
wb_master_stb_o <= '0';
s_wb_master_we_o <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
--! @brief Process to rule slave wishbone outputs
--! @param wb_clk Main clock
p_wb_slave: process (wb_clk)
--! @param wb_clk_i Main clock
p_wb_slave: process (wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if i2c_master_WB_BASIC_fsm = R0_RESET then
s_CTR0 <= c_CTR0_default;
s_CTR0.I2C_ADDR <= UNSIGNED(i2c_addr_i);
......@@ -233,7 +260,7 @@ begin
wb_slave_data_o <= DRXA_i;
when c_DRXB_addr =>
wb_slave_data_o <= DRXB_i;
when others =>
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
......@@ -246,10 +273,10 @@ begin
--! @brief This is the process that controls the wishbone master interface
--! which bridges the i2c interface with the wishbone interface.
--! @param wb_clk Main clock
p_master_fsm: process(wb_clk)
--! @param wb_clk_i Main clock
p_master_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
--! Here is the part in which we propagate the reset, let one-clock
--! for it.
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 6016b221
......@@ -2,6 +2,7 @@
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
-- Theodor-Adrian Stana
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
......@@ -159,7 +160,7 @@ package i2c_slave_pkg is
component i2c_slave_core
generic(g_WB_CLK_PERIOD : TIME := 50 ns);
port (
clk : in STD_LOGIC;
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
......@@ -181,7 +182,7 @@ package i2c_slave_pkg is
end component;
component i2c_regs
port (wb_clk : in STD_LOGIC;
port (wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
......@@ -243,6 +244,7 @@ package i2c_slave_pkg is
function f_LT (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_LT;
function f_ch_endian(val : std_logic_vector) return std_logic_vector;
function f_STD_LOGIC_VECTOR(r_register : in r_CTR0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : in r_LT) return STD_LOGIC_VECTOR;
......@@ -296,4 +298,15 @@ package body i2c_slave_pkg is
end function;
function f_ch_endian(val : std_logic_vector)
return std_logic_vector is
variable retval : std_logic_vector(31 downto 0);
begin
retval( 7 downto 0) := val(31 downto 24);
retval(15 downto 8) := val(23 downto 16);
retval(23 downto 16) := val(15 downto 8);
retval(31 downto 24) := val( 7 downto 0);
return retval;
end function;
end i2c_slave_pkg;
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 6016b221
......@@ -36,7 +36,7 @@ entity i2c_slave_top is
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
......@@ -95,7 +95,7 @@ begin
s_CTR0 <= f_CTR0(s_CTR0_slv);
inst_i2c_slave_core: i2c_slave_core
port map(clk => wb_clk,
port map(clk_i => wb_clk_i,
rst_i => wb_rst_i,
sda_oen => sda_oen,
......@@ -122,7 +122,7 @@ begin
wr_done_i => s_wr_done,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_clk_i => wb_clk_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
......@@ -156,9 +156,9 @@ begin
s_rst_i2c <= s_reset_extensor(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk)
p_rst_extender : process(wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
s_reset_extensor <= (others => '1');
else
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ 6016b221
......@@ -17,6 +17,7 @@ entity i2c_master_driver is
g_SCL_PERIOD : TIME := 250 us;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
......@@ -283,13 +284,23 @@ begin
s_sda_master_o <= '0';
end procedure;
variable first : boolean := true;
begin
if (first = true) then
wait until rst_n = '1';
first := false;
end if;
if start_i = '1' then
assert false report "mst start" severity note;
start_I2c;
elsif pause_i = '1' then
assert false report "mst pause" severity note;
pause_I2C;
elsif write_i = '1' then
assert false report "mst write" severity note;
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
......@@ -320,6 +331,7 @@ begin
wait until rising_edge(tb_clk);
s_write_done <= '0';
elsif read_i = '1' then
assert false report "mst read" severity note;
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
......@@ -357,7 +369,9 @@ begin
wait until rising_edge(tb_clk);
s_read_done <= '0';
end if;
wait until rising_edge(tb_clk);
end process;
end;
hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
View file @ 6016b221
......@@ -66,6 +66,7 @@ package i2c_tb_pkg is
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
......
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