sw: Updated xil_multiboot.py library script

Changes: - added progress string to output of read & write, instead of long address dumps - more descriptive output in read and write - increased timeout on IPROG command

sw: Updated xil_multiboot.py library script
Changes: - added progress string to output of read & write, instead of long address dumps - more descriptive output in read and write - increased timeout on IPROG command
60f4ce9b · Theodor-Adrian Stana · c4f821f6 · 60f4ce9b
Commit 60f4ce9b authored Oct 23, 2014 by Theodor-Adrian Stana
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Showing with 35 additions and 9 deletions

xil_multiboot.py software/multiboot/lib-multiboot/xil_multiboot.py +35 -9

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--- a/software/multiboot/lib-multiboot/xil_multiboot.py
+++ b/software/multiboot/lib-multiboot/xil_multiboot.py
@@ -27,6 +27,7 @@ import time
 from functools import partial
 from comm_type import *
 from flash_m25p import *
+import os

 #===============================================================================
 MB_CR_OFS = 0x00
@@ -48,19 +49,35 @@ class XilMultiboot:
            self.bitstream = param[4]
            self.flash = FlashM25P(self.comm, self.elma, self.slot, self.mb_base)

+    #
+    # Print read or write progress to screen
+    #
+    def _progress(self, sa, ea, ca):
+        actual = ca - sa
+        total = ea - sa
+        progress = (float(actual)/float(total)) * 100
+        if (progress > 100.00):
+            progress = 100.00
+        sys.stdout.write("\r  %3.2f%% (0x%06x)" % (progress, ca))
+        sys.stdout.flush()
+
    #
    # Read from flash
    #
    def read(self, sa, ea):
        # Ask for and open bitstream file
-        fname = raw_input("Output file name: ")
+        fname = raw_input("Output file name for flash readout: ")
        f = open(fname,'wb')

        # Read the data and dump to file
+        print("Reading flash contents from board in slot %d" % self.slot)
        dat = []
        for i in range(sa, ea, 256):
            dat += self.flash.read(i, 256)
-            print("(r:%d) 0x%06x" % (self.slot, i))
+            self._progress(sa, ea, i)
+        i += 256
+        self._progress(sa, ea, i)
+        print("")
        dat = ''.join(map(chr,dat))
        f.write(dat)
        f.close()
@@ -70,20 +87,21 @@ class XilMultiboot:
    #
    def write(self, addr):

-        print("Writing bitstream...")
+        print("Writing bitstream to board in slot %d" % self.slot)

        # Ask for and open bitstream file
-        fname = self.bitstream
-        f = open(fname,'rb')
+        f = open(self.bitstream,'rb')
+        sta = addr
+        tot = os.path.getsize(self.bitstream)
+        end = sta + tot

        # Start reading input file 256 bytes at a time and write to flash
        for dat in iter(partial(f.read, 256), ''):
            dat = [int(d.encode("hex"), 16) for d in dat]
-            print("(w:%d) 0x%x" % (self.slot, addr))
+            self._progress(sta, end, addr)

            # Erase on sector boundary
            if not (addr % 0x10000):
-                print('erase')
                self.flash.serase(addr)
                while (self.flash.rsr() & 0x01):
                    pass
@@ -96,6 +114,9 @@ class XilMultiboot:
            # increment to next page address
            addr += 256

+        self._progress(sta, end, addr)
+        print("")
+
        # Close file handle
        f.close()
        print("DONE!")
@@ -116,7 +137,7 @@ class XilMultiboot:

            # Set timeout...
            t0 = time.time()
-            t1 = t0 + 20
+            t1 = t0 + 60

            # and wait for the FPGA to gracefully respond, or die trying
            while (1):
@@ -140,7 +161,7 @@ class XilMultiboot:
        print("Press 'q' to end config reg readout")
        while 1:
            try:
-                reg = raw_input('Address: 0x')
+                reg = raw_input('Address (hex): ')
                reg = int(reg, 16)
                if (reg < 0x00) or (reg > 0x22):
                    raise ValueError
@@ -156,3 +177,8 @@ class XilMultiboot:
                    break
                print("Please input a hex value in the range [0x00, 0x22] or 'q' to quit")

+    #
+    # Set bitstream file path
+    #
+    def set_bitstream_file(self, path):
+        self.bitstream = path