Commit 65ced44e authored by Carlos Gil Soriano's avatar Carlos Gil Soriano

Added missed files before merging. Some .do files for the waveforms.

parent a9e62b25
......@@ -25,18 +25,18 @@
</file>
<file xil_pn:name="../rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../test/i2c_slave_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="28"/>
......@@ -54,8 +54,8 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
......@@ -70,11 +70,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../test/i2c_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -82,7 +82,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../test/i2c_bit_tb.vhd" xil_pn:type="FILE_VHDL">
......
......@@ -9,32 +9,35 @@ add wave -noupdate -expand -group {I2C interface} /i2c_slave_top_tb/uut/sda_oen
add wave -noupdate -expand -group {I2C interface} -radix unsigned /i2c_slave_top_tb/uut/i2c_addr_i
add wave -noupdate /i2c_slave_top_tb/uut/wb_clk
add wave -noupdate /i2c_slave_top_tb/uut/wb_rst_i
add wave -noupdate -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_stb_i
add wave -noupdate -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_cyc_i
add wave -noupdate -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_we_i
add wave -noupdate -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_sel_i
add wave -noupdate -group {Wishbone Slave} -radix unsigned /i2c_slave_top_tb/uut/wb_slave_addr_i
add wave -noupdate -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_data_o
add wave -noupdate -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_data_i
add wave -noupdate -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_ack_o
add wave -noupdate -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_err_o
add wave -noupdate -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_rty_o
add wave -noupdate -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_stb_o
add wave -noupdate -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_cyc_o
add wave -noupdate -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_we_o
add wave -noupdate -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_sel_o
add wave -noupdate -group {Wishbone Master} -radix unsigned /i2c_slave_top_tb/uut/wb_master_addr_o
add wave -noupdate -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_data_i
add wave -noupdate -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_data_o
add wave -noupdate -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_ack_i
add wave -noupdate -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_err_i
add wave -noupdate -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_rty_i
add wave -noupdate -divider Registers
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_stb_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_cyc_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_we_i
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_sel_i
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_addr_i
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_data_o
add wave -noupdate -expand -group {Wishbone Slave} -radix hexadecimal /i2c_slave_top_tb/uut/wb_slave_data_i
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_ack_o
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_err_o
add wave -noupdate -expand -group {Wishbone Slave} /i2c_slave_top_tb/uut/wb_slave_rty_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_stb_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_cyc_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_we_o
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_sel_o
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_addr_o
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_data_i
add wave -noupdate -expand -group {Wishbone Master} -radix hexadecimal /i2c_slave_top_tb/uut/wb_master_data_o
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_ack_i
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_err_i
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/wb_master_rty_i
add wave -noupdate -expand -group {Wishbone Master} /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate /i2c_slave_top_tb/uut/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate -divider Registers
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_CTR0
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_LT
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_DRXA
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_DRXB
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_DTX
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/s_pf_wb_data
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/CTR0_o
add wave -noupdate -group i2c_regs /i2c_slave_top_tb/uut/inst_i2c_regs/DTX_o
......@@ -77,6 +80,10 @@ add wave -noupdate -expand -group byte_counter /i2c_slave_top_tb/uut/inst_i2c_sl
add wave -noupdate -expand -group byte_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/rst_i
add wave -noupdate -expand -group byte_counter /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/en_i
add wave -noupdate -expand -group byte_counter -radix unsigned /i2c_slave_top_tb/uut/inst_i2c_slave_core/byte_counter_8/cnt_o
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/clk_i
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/rst_i
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/en_i
add wave -noupdate -group watchdog /i2c_slave_top_tb/uut/inst_i2c_slave_core/watchdog_counter_8/cnt_o
add wave -noupdate -divider {MCU signals}
add wave -noupdate /i2c_slave_top_tb/uut/pf_wb_addr_o
add wave -noupdate /i2c_slave_top_tb/uut/wr_done_o
......@@ -90,12 +97,35 @@ add wave -noupdate -group i2c_driver -radix hexadecimal /i2c_slave_top_tb/i2c_dr
add wave -noupdate -group i2c_driver -radix hexadecimal /i2c_slave_top_tb/i2c_driver/wr_data_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/start_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/write_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/read_i
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/start_done_o
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/write_done_o
add wave -noupdate -group i2c_driver /i2c_slave_top_tb/i2c_driver/read_done_o
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_regs/s_CTR0
add wave -noupdate -radix hexadecimal /i2c_slave_top_tb/uut/inst_i2c_slave_core/s_DRX_slv
add wave -noupdate /i2c_slave_top_tb/wb_driver/wb_data_i
add wave -noupdate /i2c_slave_top_tb/wb_driver/wb_data_o
add wave -noupdate /i2c_slave_top_tb/wb_driver/data_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_addr_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_clk_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_rst_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_stb_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_cyc_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_sel_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_we_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_ack_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_rty_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/wb_err_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/data_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/addr_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/write_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/write_done_o
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/read_i
add wave -noupdate -group wb_driver /i2c_slave_top_tb/wb_driver/read_done_o
add wave -noupdate /i2c_slave_top_tb/s_feedback_wb_bus
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {147050000 ps} 0}
configure wave -namecolwidth 193
WaveRestoreCursors {{Cursor 1} {1030400000 ps} 0}
configure wave -namecolwidth 325
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -109,4 +139,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1870304 ps} {194025244 ps}
WaveRestoreZoom {765068158 ps} {1416341376 ps}
This diff is collapsed.
......@@ -4,26 +4,3 @@
0 OK WRSR DATA SR register received matches with expected
0 -- WRDI End of TX: WRDI received
1 -- WREN Start of TX: WREN received
1 OK PP INST PP instruction received matches with expected
1 OK PP ADDR Address received matches with expected
1 -- WRDI End of TX: WRDI received
2 -- WREN Start of TX: WREN received
2 OK SE INST SE instruction received matches with expected
2 OK SE ADDR Address received matches with expected
2 -- WRDI End of TX: WRDI received
3 -- WREN Start of TX: WREN received
3 OK BE INST BE instruction received matches with expected
3 -- WRDI End of TX: WRDI received
4 -- WREN Start of TX: WREN received
4 OK RDSR INST RDSR instruction received matches with expected
4 -- WRDI End of TX: WRDI received
4 OK RDSR READ SR_m25p32 matches with expected
5 -- WREN Start of TX: WREN received
5 OK RDID INST RDID instruction received matches with expected
5 -- WRDI End of TX: WRDI received
5 OK RDID READ RDID matches with expected
6 -- WREN Start of TX: WREN received
6 OK READ INST READ instruction received matches with expected
6 OK READ ADDR Address received matches with expected
6 -- WRDI End of TX: WRDI received
6 OK READ READ READ matches with expected
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