Commit 66296379 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Renamed userguide* to ug* and made modifications to ug doc

The modifications can be read from the .pdf doc, Revision history
section. First `make' the ug, then go to this section to see the
modifications
parent 0878b3d6
FILE=userguide-conv-ttl-blo
FILE=ug-conv-ttl-blo
all:
$(MAKE) -C fig
......
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill April 15, 2014
\hfill August 11, 2014
\vspace*{3cm}
......
......@@ -39,14 +39,14 @@
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......@@ -69,6 +69,11 @@
08-04-2014 & 2.10 & Changed max. pulse repetition frequency, replaced the timetag FIFO for a
ring buffer \\
15-04-2014 & 2.11 & Updated Section~\ref{sec:reprog-fwstat} \\
11-08-2014 & 2.20 & Various to make the document clearer. Made description in Table~\ref{tbl:syserr}
more concise; moved Figure~\ref{fig:sr-switches} from Section~\ref{sec:switches}
to Section~\ref{sec:diag-sw-rtmdet}; made slight modifications to Figure~\ref{fig:man-trig-fsm}
to make it fit on its page; added reference to schematics and OHWR project page
in Additional Documents section (under Section~\ref{sec:intro}) \\
\hline
\end{tabular}
}
......@@ -174,6 +179,8 @@ part of the VME crate to the front module.
\subsection*{Additional documentation}
\begin{itemize}
\item CONV-TTL-BLO OHWR Project Page \cite{ctb-proj}
\item CONV-TTL-BLO Schematics on CERN EDMS \cite{sch}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\item CONV-TTL-BLO HDL Guide \cite{ctb-hdlguide}
\end{itemize}
......@@ -328,8 +335,8 @@ When a pulse is repeated on the output connector of a channel, the pulse status
There are eight switches provided on-board the CONV-TTL-BLO, only two of which are
used. Figure~\ref{fig:switches} shows the switches and highlights the used ones, which
are also listed in Table~\ref{tbl:switches}. The status of all on-board switches can be
read from the board's status register (SR -- see Appendix~\ref{app:conv-regs-sr}.
Figure~\ref{fig:sr-switches} shows how the switches map to the SR.
read from the board's status register (SR -- see Appendix~\ref{app:conv-regs-sr} and
Section~\ref{sec:diag-sw-rtmdet}).
\begin{figure}[htbp]
\centerline{\includegraphics[scale=.65]{fig/switches}}
......@@ -358,12 +365,6 @@ Figure~\ref{fig:sr-switches} shows how the switches map to the SR.
}
\end{table}
\begin{figure}[h]
\centerline{\includegraphics[width=.5\textwidth]{fig/sr-switches}}
\caption{Switch mapping to the SR}
\label{fig:sr-switches}
\end{figure}
Note that both switches in Table~\ref{tbl:switches} are board-wide switches; selecting
one position or the other yields a selection valid for all six pulse replication channels.
......@@ -842,6 +843,20 @@ iso.3.6.1.4.1.37968.1.1.8.2.2.1.2.114 = STRING: "abcde"
iso.3.6.1.4.1.37968.1.1.8.2.2.1.2.114 = STRING: "000ABCDE"
\end{verbatim}
%%--------------------------------------------------------------------------------------
%% SUBSEC: Comm timeout
%%--------------------------------------------------------------------------------------
\subsection{Communication timeout}
\label{sec:comm-timeout}
The CONV-TTL-RS485 FPGA implements an I$^2$C slave that decodes the protocol
to access the registers. The I$^2$C slave also implements a watchdog timer that
resets the slave logic if the communication takes too long to complete.
Currently, the timeout is set to 24~ms. Should the timeout occur, a system error bit is set
in the board status register (see Section~\ref{sec:diag-syserr}) and the
\textit{ERR} bicolor LED is lit red.
%==============================================================================
% SEC: Diagonstics
%==============================================================================
......@@ -960,7 +975,7 @@ The state of the on-board switches and that of the RTM detection lines can
also be read from the SR (see Appendix~\ref{app:conv-regs-sr}).
In the case of the switches, the raw state of the FPGA inputs is reflected on
the SR bits. Since an ON switch pulls the line to GND, a '0' value on one
the SR bits (Figure~\ref{fig:sr-switches}). Since an ON switch pulls the line to GND, a '0' value on one
of the switch bits means the switch is on.
In the case of the RTM detection lines~\cite{rtm-det}, the lines reflect the
......@@ -969,7 +984,13 @@ actual status of the RTM detection line, prior to it being inverted on the board
state in the SR will be a logic '1', and if it is pulled low by an RTMM/P, its
state in the SR will be a logic '0'.
\begin{figure}[h]
\begin{figure}
\centerline{\includegraphics[width=.5\textwidth]{fig/sr-switches}}
\caption{Switch mapping to the SR}
\label{fig:sr-switches}
\end{figure}
\begin{figure}
\centerline{\includegraphics[width=.85\textwidth]{fig/rtm-det}}
\caption{RTM detection lines to status register}
\label{fig:rtm-det}
......@@ -983,7 +1004,10 @@ state in the SR will be a logic '0'.
One channel is allocated on the input of each counter, after the OR gate preceding
the pulse generator. The input counter logic, which is repeated on each channel,
is shown in Figure~\ref{fig:pulse-cnt}.
is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a
TTL or a blocking input, the pulse counter is incremented and stored to the channel's
pulse counter register (CHxPCR -- see Appendix~\ref{app:conv-regs}). The CHxPCR is a
read-write register that can be written at any time via I$^2$C with a user-defined value.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
......@@ -991,11 +1015,6 @@ is shown in Figure~\ref{fig:pulse-cnt}.
\label{fig:pulse-cnt}
\end{figure}
On a rising edge of a pulse from either a TTL or a blocking input, the pulse
counter is incremented and stored to the channel's pulse counter register
(CHxPCR -- see Appendix~\ref{app:conv-regs}). The CHxPCR is a read-write register
that can be written at any time via I$^2$C with a user-defined value.
%------------------------------------------------------------------------------
% SUBSEC: Pulse counters
%------------------------------------------------------------------------------
......@@ -1051,6 +1070,7 @@ value.
\end{table}
%------------------------------------------------------------------------------
\pagebreak
\subsubsection{Timetag storage delay}
%------------------------------------------------------------------------------
......@@ -1115,7 +1135,7 @@ buffer, while the write pointer points to the next buffer location to be written
Figure~\ref{fig:timetag-buf-mech} shows the operation of the ring buffer.
\begin{figure}[t]
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/timetag-buf-mech}}
\caption{Ring buffer mechanics, example with four-sample-deep buffer}
\label{fig:timetag-buf-mech}
......@@ -1195,12 +1215,6 @@ should only be used when debugging the connection between two CONV-TTL-BLO board
or between a CONV-TTL-BLO and another receiver. This is why manual pulse
triggering is password-protected.
In order to manually trigger a pulse, the user should write five bytes to the board's control
register at address \textbf{0x004} (CR -- see Appendix~\ref{app:conv-regs-cr}), as shown in
Figure~\ref{tbl:man-trig}. The MPT field is dual-purpose, as shown in
Figure~\ref{fig:cr-mpt}. Until the magic sequence is input, it should be written with the
bytes in the magic sequence. After that, it should be written with the channel number.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/cr-mpt}}
\caption{MPT field in the CR}
......@@ -1223,6 +1237,12 @@ bytes in the magic sequence. After that, it should be written with the channel n
}
\end{table}
In order to manually trigger a pulse, the user should write five bytes to the board's control
register at address \textbf{0x004} (CR -- see Appendix~\ref{app:conv-regs-cr}), as shown in
Table~\ref{tbl:man-trig}. The MPT field is dual-purpose, as shown in
Figure~\ref{fig:cr-mpt}. Until the magic sequence is input, it should be written with the
bytes in the magic sequence. After that, it should be written with the channel number.
Figure~\ref{fig:man-trig-fsm} shows the manual pulse triggering logic. In order for a
pulse to be triggered, five write cycles to the MPT field must be done. If the fifth cycle is
a channel number in the range 1..6, one and only one pulse is generated by the PG
......@@ -1232,7 +1252,7 @@ number is not in the range 1..6, no pulse is generated on any channel and no
error is reported.
\begin{figure}[h]
\centerline{\includegraphics[width=.55\textwidth]{fig/man-trig-fsm}}
\centerline{\includegraphics[width=.46\textwidth]{fig/man-trig-fsm}}
\caption{Manual pulse triggering logic}
\label{fig:man-trig-fsm}
\end{figure}
......@@ -1240,19 +1260,20 @@ error is reported.
%------------------------------------------------------------------------------
% SUBSEC: System Errors
%------------------------------------------------------------------------------
\pagebreak
\subsection{System errors}
\label{sec:diag-syserr}
Various system errors are defined on converter boards. When such an error occurs,
the ERR LED on the front panel lights up in \textit{red}. At this point, the user
should connect to the converter board to see exactly what caused the system error.
should connect to the converter board (Section~\ref{sec:comm}) to see exactly what
caused the system error.
The system errors defined for the CONV-TTL-BLO, together with the relevant bits
set when the error occurs, are shown in Table~\ref{tbl:syserr}.
\begin{table}[h]
\caption{System errors on the CONV-TTL-BLO}
\label{tbl:syserr}
\caption{\label{tbl:syserr} System errors on the CONV-TTL-BLO}
\centerline
{
\rowcolors{2}{white}{gray!25}
......@@ -1261,22 +1282,12 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
\multicolumn{1}{c}{\textbf{Error}} & \multicolumn{1}{c}{\textbf{Register}} &
\multicolumn{1}{c}{\textbf{Description}} \\
\hline
I$^2$C timeout & SR.I2C\_WDTO & The I$^2$C communication controller contains a watchdog
timer which resets the I$^2$C communication in case
it takes too long to complete a transfer. The longest
I$^2$C transfer (using \textit{writemregs}) should take
no longer than approx. 4~ms. If a transfer is not completed
within 24~ms, this error is thrown. \\
I$^2$C error & SR.I2C\_ERR & This error is thrown in case a non-memory-mapped address
is accessed via I$^2$C. \\
Missed pulse & SR.PMISS & As shown in Figure~\ref{fig:pg-op}, the PG block rejects
input pulses within a period of $T_{min}$. If any pulses
arrive within $T_{min}$ of another pulse, they are not
replicated on the output and this error is thrown. \newline
Use the \textbf{tsdiff.py} script to diagnose the channel
which caused this error. \\
I$^2$C timeout & SR.I2C\_WDTO & An I$^2$C transfer is not completed
within 24~ms (see Section~\ref{sec:comm-timeout}) \\
I$^2$C error & SR.I2C\_ERR & Attempted to access a non-memory-mapped address via I$^2$C \\
Missed pulse & SR.PMISS & Input pulse rejected (see Figure~\ref{fig:pg-op}) \\
\hline
\end{tabular}
\end{tabular}
}
\end{table}
......@@ -1727,7 +1738,7 @@ one-wire timings. The value for the current version of the gateware is
\nocite{ohwr}
\nocite{sch}
\bibliographystyle{ieeetr}
\bibliography{userguide-conv-ttl-blo}
\bibliography{ug-conv-ttl-blo}
\end{document}
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