Skip to content

C
Conv TTL Blocking
Commit 67ca4cac authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
Browse files
Options

Readbacks of image1 are OK in every subcomponent.

parent 3bcc3dfb
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 13493 additions and 13215 deletions
hdl/IMAGES/image1/project/image1.gise
View file @ 67ca4cac
......@@ -60,7 +60,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354387693" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1354387693">
<transform xil_pn:end_ts="1354715194" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1354715193">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -112,7 +112,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1354387693" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1354387693">
<transform xil_pn:end_ts="1354715194" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1354715194">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd"/>
......@@ -152,7 +152,7 @@
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
</transform>
<transform xil_pn:end_ts="1354387694" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1354387693">
<transform xil_pn:end_ts="1354715195" xil_pn:in_ck="-8135161928864423195" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1354715194">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="image1_top_tb.fdo"/>
......
hdl/IMAGES/image1/project/image1.xise
View file @ 67ca4cac
......@@ -209,6 +209,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Do File Behavioral" xil_pn:value="waveform/wave.do" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/project/waveform/wave.do
View file @ 67ca4cac
This diff is collapsed.
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 67ca4cac
......@@ -52,7 +52,7 @@ package image1_pkg is
--! will be processed as an access to such register (indeed, like
--! accessing to byte 0).
--! ==================================
--! M25P32 [0800-0FFF]
--! M25P32 [0200-03FF]
--! MULTIBOOT [0080-00CF]
--! I2C_SLAVE [0040-007F]
--! ==================================
......@@ -61,19 +61,19 @@ package image1_pkg is
constant c_ADDR_I2C_SLAVE : t_wishbone_address := X"00000040";
--! 64 words per page: 6 + 1 bits
constant c_MASK_M25P32 : t_wishbone_address := X"FFFFFFE0";
constant c_MASK_M25P32 : t_wishbone_address := X"FFFFFE00";
constant c_MASK_MULTIBOOT : t_wishbone_address := X"FFFFFFC0";
constant c_MASK_I2C_SLAVE : t_wishbone_address := X"FFFFFFC0";
constant c_addresses : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (c_ADDR_MULTIBOOT,
c_ADDR_M25P32,
c_ADDR_I2C_SLAVE);
:= (c_ADDR_M25P32,
c_ADDR_MULTIBOOT,
c_ADDR_I2C_SLAVE);
constant c_masks : t_wishbone_address_array(c_NUM_SLAVES - 1 downto 0)
:= (c_MASK_MULTIBOOT,
c_MASK_M25P32,
c_MASK_I2C_SLAVE);
:= (c_MASK_M25P32,
c_MASK_MULTIBOOT,
c_MASK_I2C_SLAVE);
component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
......@@ -216,7 +216,8 @@ package image1_pkg is
-- function check_sys_cfg return BOOLEAN;
function f_RENESAS_I2C_ADDRESSING(VME_slot : UNSIGNED(4 downto 0))
return STD_LOGIC_VECTOR;
end image1_pkg;
package body image1_pkg is
......@@ -235,4 +236,20 @@ package body image1_pkg is
-- return TRUE;
-- end check_sys_cfg;
--! @brief Translation function for i2c_addressing
--! The specification of this criteria can be found in
--! Samuel's document "Specification. Access to board data
--! using SNMP and I2C" sent to Mihai Savu.
--! @param VME_slot VME_slot (FPGA_GA[x] pins) in which the board is
--! inserted
function f_RENESAS_I2C_ADDRESSING(VME_slot : UNSIGNED(4 downto 0))
return STD_LOGIC_VECTOR is
variable v_tmp : NATURAL;
variable v_return : STD_LOGIC_VECTOR(6 downto 0);
begin
v_tmp := 95 - to_integer(VME_slot);
v_return := STD_LOGIC_VECTOR(to_unsigned(v_tmp, 7));
return v_return;
end function;
end image1_pkg;
hdl/IMAGES/image1/rtl/image1_top.vhd
View file @ 67ca4cac
......@@ -102,7 +102,7 @@ begin
-- s_check_cfg <= check_sys_cfg;
s_i2c_addr <= "00"&FPGA_GA;
s_i2c_addr <= f_RENESAS_I2C_ADDRESSING(UNSIGNED(FPGA_GA));
s_led_err_o <= '1' when s_ok_RTMM = '1' AND s_ok_RTMP = '1'
else '0';
......@@ -154,15 +154,17 @@ begin
p_reset_PLL_chain : process(s_clk.PLL_IN) is
begin
if rising_edge(s_clk.PLL_IN) then
s_rst.PLL(0) <= '0';
for i in 1 to c_RST_PLL_CLKS - 1 loop
s_rst.PLL(i) <= s_rst.PLL(i-1);
end loop;
s_rst.PLL <= (others => '1');
if s_rst.PLL(c_RST_PLL_CLKS - 1) = '1' then
end if;
s_rst.PLL(0) <= '0';
for i in 1 to c_RST_PLL_CLKS - 1 loop
s_rst.PLL(i) <= s_rst.PLL(i-1);
end loop;
end if;
if s_rst.PLL(c_RST_PLL_CLKS - 1) = '1' then
end if;
end if;
end process p_reset_PLL_chain;
......@@ -171,14 +173,18 @@ begin
p_reset_A_chain : process(s_clk.SYS_A) is
begin
if rising_edge(s_clk.SYS_A) then
s_rst.SYS_A(0) <= '0';
for i in 1 to c_RST_A_CLKS - 1 loop
s_rst.SYS_A(i) <= s_rst.SYS_A(i-1);
end loop;
if s_locked = '0' then
s_rst.SYS_A <= (others => '1');
else
s_rst.SYS_A(0) <= '0';
for i in 1 to c_RST_A_CLKS - 1 loop
s_rst.SYS_A(i) <= s_rst.SYS_A(i-1);
end loop;
if s_rst.SYS_A(c_RST_A_CLKS - 1) = '1' then
end if;
if s_rst.SYS_A(c_RST_A_CLKS - 1) = '1' then
end if;
end if;
end if;
end process p_reset_A_chain;
......@@ -187,14 +193,18 @@ begin
p_reset_B_chain : process(s_clk.SYS_B) is
begin
if rising_edge(s_clk.SYS_B) then
s_rst.SYS_B(0) <= '0';
for i in 1 to c_RST_B_CLKS - 1 loop
s_rst.SYS_B(i) <= s_rst.SYS_B(i-1);
end loop;
if s_locked = '0' then
s_rst.SYS_B <= (others => '1');
else
s_rst.SYS_B(0) <= '0';
for i in 1 to c_RST_B_CLKS - 1 loop
s_rst.SYS_B(i) <= s_rst.SYS_B(i-1);
end loop;
if s_rst.SYS_B(c_RST_B_CLKS - 1) = '1' then
end if;
if s_rst.SYS_B(c_RST_B_CLKS - 1) = '1' then
end if;
end if;
end if;
end process p_reset_B_chain;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 67ca4cac
......@@ -63,25 +63,26 @@ architecture behavior of image1_top_tb is
signal s_wr_data : STD_LOGIC_VECTOR(c_WR_DATA_LENGTH - 1 downto 0)
:= (others => '0');
signal s_rd_data : STD_LOGIC_VECTOR(c_RD_DATA_LENGTH - 1 downto 0);
signal s_i2c_driver_start : STD_LOGIC := '0';
signal s_i2c_driver_start_done : STD_LOGIC;
signal s_i2c_driver_pause : STD_LOGIC := '0';
signal s_i2c_driver_pause_done : STD_LOGIC;
signal s_i2c_driver_write : STD_LOGIC := '0';
signal s_i2c_driver_write_done : STD_LOGIC;
signal s_i2c_driver_read : STD_LOGIC := '0';
signal s_i2c_driver_read_done : STD_LOGIC;
signal s_I2C_driver_ctrl : I2C_master_driver_ctrl
:= c_I2C_master_driver_ctrl_default;
signal s_I2C_driver_ctrl_done : I2C_master_driver_ctrl;
signal wb_clk : STD_LOGIC;
signal s_rst_SYS_A : STD_LOGIC_VECTOR(c_RST_A_CLKS - 1 downto 0);
signal s_rst : STD_LOGIC;
signal s_I2C_regs : t_I2C_regs;
begin
s_FPGA_GA <= "00001";
s_FPGA_GAP <= '1';
s_I2C_master_i <= s_I2C_slave_o;
s_I2C_slave_i <= s_I2C_master_o;
s_I2C_master_i <= s_I2C_slave_o;
s_I2C_slave_i <= s_I2C_master_o;
s_rst <= s_rst_SYS_A(c_RST_A_CLKS - 1);
--! Clock process definitions
p_FPGA_CLK :process
......@@ -96,7 +97,17 @@ begin
p_sig_spy : process is
begin
init_signal_spy("/uut/s_clk.SYS_A", "wb_clk", 1);
init_signal_spy("/uut/s_rst.SYS_A(c_RST_A_CLKS - 1)", "s_rst", 1);
init_signal_spy("/uut/s_rst.SYS_A", "s_rst_SYS_A", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_CTR0",
"s_I2C_regs.CTR0", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_LT",
"s_I2C_regs.LT", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_DRXA",
"s_I2C_regs.DRXA", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_DRXB",
"s_I2C_regs.DRXB", 1);
init_signal_spy("/uut/inst_i2c_slave/inst_i2c_regs/s_DTX",
"s_I2C_regs.DTX", 1);
wait;
end process p_sig_spy;
......@@ -104,6 +115,8 @@ begin
-- Instantiate the Unit Under Test (UUT)
i2c_driver: i2c_master_driver
generic map(g_SCL_PERIOD => c_SCL_I2C_DRIVER_PERIOD,
g_LOG_PATH => "../test/log/i2c_master_driver.txt")
port map(tb_clk => wb_clk,
sda_master_i => s_I2C_master_i.SDA,
......@@ -115,14 +128,14 @@ begin
wr_data_i => s_wr_data,
rd_data_o => s_rd_data,
start_i => s_i2c_driver_start,
start_done_o => s_i2c_driver_start_done,
pause_i => s_i2c_driver_pause,
pause_done_o => s_i2c_driver_pause_done,
write_i => s_i2c_driver_write,
write_done_o => s_i2c_driver_write_done,
read_i => s_i2c_driver_read,
read_done_o => s_i2c_driver_read_done);
start_i => s_i2c_driver_ctrl.START,
pause_i => s_i2c_driver_ctrl.PAUSE,
write_i => s_i2c_driver_ctrl.WRITE,
read_i => s_i2c_driver_ctrl.READ,
start_done_o => s_i2c_driver_ctrl_done.START,
pause_done_o => s_i2c_driver_ctrl_done.PAUSE,
write_done_o => s_i2c_driver_ctrl_done.WRITE,
read_done_o => s_i2c_driver_ctrl_done.READ);
uut: image1_top
generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
......@@ -178,10 +191,10 @@ begin
procedure start_I2C is
begin
s_i2c_driver_start <= '1';
wait until rising_edge(s_i2c_driver_start_done);
s_I2C_driver_ctrl.START <= '1';
wait until rising_edge(s_I2C_driver_ctrl_done.START);
wait until rising_edge(wb_clk);
s_i2c_driver_start <= '0';
s_I2C_driver_ctrl.START <= '0';
end procedure;
procedure write_I2C(i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
......@@ -192,10 +205,10 @@ begin
s_i2c_addr_op <= i2c_addr;
s_wishbone_addr <= wb_addr;
s_wr_data <= wr_data;
s_i2c_driver_write <= '1';
s_I2C_driver_ctrl.WRITE <= '1';
wait until rising_edge(wb_clk);
s_i2c_driver_write <= '0';
wait until rising_edge(s_i2c_driver_write_done);
s_I2C_driver_ctrl.WRITE <= '0';
wait until rising_edge(s_I2C_driver_ctrl_done.WRITE);
wait until rising_edge(wb_clk);
end procedure;
......@@ -213,22 +226,19 @@ begin
end procedure;
procedure read_I2C(vme_slot : UNSIGNED(4 downto 0);
wb_addr : STD_LOGIC_VECTOR(s_wishbone_addr'length - 1 downto 0);
wr_data : STD_LOGIC_VECTOR(s_wr_data'length - 1 downto 0)) is
wb_addr : STD_LOGIC_VECTOR(s_wishbone_addr'length - 1 downto 0)) is
variable v_i2c_addr : STD_LOGIC_VECTOR(7 downto 0);
begin
v_i2c_addr(7 downto 6) := "00";
v_i2c_addr(5 downto 1) := STD_LOGIC_VECTOR(vme_slot);
v_i2c_addr(7 downto 1) := f_RENESAS_I2C_ADDRESSING(vme_slot);
v_i2c_addr(0) := '0';
wait until rising_edge(wb_clk);
-- i2c_master_driver
s_i2c_addr_op <= v_i2c_addr;
s_wishbone_addr <= wb_addr;
s_wr_data <= wr_data;
s_i2c_driver_read <= '1';
s_I2C_driver_ctrl.READ <= '1';
wait until rising_edge(wb_clk);
s_i2c_driver_read <= '0';
wait until rising_edge(s_i2c_driver_read_done);
s_I2C_driver_ctrl.READ <= '0';
wait until rising_edge(s_I2C_driver_ctrl_done.READ);
wait until rising_edge(wb_clk);
end procedure;
......@@ -238,17 +248,67 @@ begin
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
--! First we place a write
--! We read addr 1 (LT) via I2C
--! Then, the core internally prefetchs via wishbone and then
--! write the register into I2C to the master
--! Please check in the wave.do file the internal register
--! against the s_DTX register in the i2c_master_driver!
start_I2C;
-- --! Try to write into DTX addr position
-- write_I2C(s_FPGA_GA, X"0002", X"B16B00B5");
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_CTR0_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_LT_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_DTX_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_DRXB_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_DRXA_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_CTR0_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_CTR1_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_STAT_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_MBA_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_GBA_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_MBA_ICAP_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_GBA_ICAP_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_M25P32_FMI_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_M25P32_SR_m25p32_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_M25P32_DATA_READ_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
read_I2C(UNSIGNED(s_FPGA_GA), c_M25P32_DATA_WRITE_addr);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
start_I2C;
--
-- start_I2C;
-- --! We read addr 1 (LT) via I2C
-- --! Then, the core internally prefetchs via wishbone and then
-- --! write the register into I2C to the master
-- read_I2C(s_FPGA_GA, X"BAB1", X"B16B00B5");
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
-- --! Try to write into DTX addr position
-- write_I2C(UNSIGNED(s_FPGA_GA), c_MULTIBOOT_MBA_addr, X"B16B00B5");
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
end process;
end;
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ 67ca4cac
......@@ -14,6 +14,8 @@ use work.multiboot_pkg.ALL;
package image1_top_tb_pkg is
constant c_SCL_I2C_DRIVER_PERIOD : TIME := 10 us;
constant c_NUMBER_OF_CHANNELS : NATURAL
:= work.image1_pkg.c_NUMBER_OF_CHANNELS;
......@@ -113,6 +115,16 @@ package image1_top_tb_pkg is
RTMP : STD_LOGIC_VECTOR(2 downto 0);
end record;
type t_I2C_regs is
record
CTR0 : work.i2c_slave_pkg.r_CTR0;
LT : work.i2c_slave_pkg.r_LT;
DRXA : STD_LOGIC_VECTOR(work.i2c_slave_pkg.r_DRX'a_length - 1 downto 0);
DRXB : STD_LOGIC_VECTOR(work.i2c_slave_pkg.r_DRX'a_length - 1 downto 0);
DTX : STD_LOGIC_VECTOR(work.i2c_slave_pkg.r_DTX'a_length - 1 downto 0);
end record;
constant c_fpga_en_default : t_fpga_en := (GEN => '0',
BLO => '0',
TTL => '0',
......@@ -150,10 +162,11 @@ package image1_top_tb_pkg is
--! c_MULTIBOOT_GBA_addr [0090]
--! c_MULTIBOOT_MBA_ICAP_addr [0094]
--! c_MULTIBOOT_GBA_ICAP_addr [0098]
--! c_M25P32_FMI_addr [0800]
--! c_M25P32_SR_m25p32_addr [0804]
--! c_M25P32_DATA_READ_addr [0808]
--! c_M25P32_DATA_WRITE_addr [081C - 8480]
--! c_M25P32_FMI_addr [0200]
--! c_M25P32_SR_m25p32_addr [0204]
--! c_M25P32_DATA_READ_addr [0208]
--! c_M25P32_DATA_WRITE_addr [0300 - 03FF]
--! ==================================
constant c_I2C_CTR0_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"01"& STD_LOGIC_VECTOR(work.i2c_slave_pkg.c_CTR0_addr) & "00";
......@@ -180,11 +193,15 @@ package image1_top_tb_pkg is
constant c_MULTIBOOT_GBA_ICAP_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"00"&"10"& STD_LOGIC_VECTOR(work.multiboot_pkg.c_GBA_ICAP_addr) &"00";
constant c_M25P32_FMI_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_FMI_addr &"00";
:= X"0"&"001"& work.m25p32_pkg.c_FMI_addr &"00";
constant c_M25P32_SR_m25p32_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_SR_m25p32_addr &"00";
:= X"0"&"001"& work.m25p32_pkg.c_SR_m25p32_addr &"00";
constant c_M25P32_DATA_READ_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_DATA_READ_addr &"00";
:= X"0"&"001"& work.m25p32_pkg.c_DATA_READ_addr &"00";
constant c_M25P32_DATA_WRITE_addr : STD_LOGIC_VECTOR(15 downto 0)
:= X"0"&'1'& work.m25p32_pkg.c_DATA_WRITE_addr &"00";
:= X"0"&"001"& work.m25p32_pkg.c_DATA_WRITE_addr &"00";
end image1_top_tb_pkg;
package body image1_top_tb_pkg is
end image1_top_tb_pkg;
hdl/IMAGES/image1/test/log/i2c_master_driver.txt 0 → 100644
View file @ 67ca4cac
1 OK READ [ADDRESS|0]
1 OK READ WISHBONE HIGH
1 OK READ WISHBONE LOW
1 OK READ [ADDRESS|0]
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
3 OK READ [ADDRESS|0]
3 OK READ WISHBONE HIGH
3 OK READ WISHBONE LOW
3 OK READ [ADDRESS|0]
4 OK READ [ADDRESS|0]
4 OK READ WISHBONE HIGH
4 OK READ WISHBONE LOW
4 OK READ [ADDRESS|0]
5 OK READ [ADDRESS|0]
5 OK READ WISHBONE HIGH
5 OK READ WISHBONE LOW
5 OK READ [ADDRESS|0]
6 OK READ [ADDRESS|0]
6 OK READ WISHBONE HIGH
6 OK READ WISHBONE LOW
6 OK READ [ADDRESS|0]
7 OK READ [ADDRESS|0]
7 OK READ WISHBONE HIGH
7 OK READ WISHBONE LOW
7 OK READ [ADDRESS|0]
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 67ca4cac
......@@ -60,8 +60,6 @@ entity i2c_regs is
LT_i : in STD_LOGIC_VECTOR (r_LT'a_length -1 downto 0);
DRXA_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DTX_o : out STD_LOGIC_VECTOR (r_DTX'a_length - 1 downto 0);
load_TX : out STD_LOGIC;
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
......@@ -94,11 +92,8 @@ signal s_wb_slave_err : STD_LOGIC := '0';
signal s_CTR0_slv : STD_LOGIC_VECTOR (r_CTR0'a_length - 1 downto 0);
signal s_CTR0 : r_CTR0 := c_CTR0_default;
signal s_LT : r_LT;
signal s_DRXA : STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
signal s_DRXB : STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
signal s_DTX : STD_LOGIC_VECTOR (r_DTX'a_length - 1 downto 0);
signal s_load_TX : STD_LOGIC;
signal s_wb_master_we_o : STD_LOGIC;
......@@ -119,8 +114,7 @@ begin
wb_slave_err_o <= s_wb_slave_err;
CTR0_o <= s_CTR0_slv;
DTX_o <= s_DTX;
load_TX <= s_load_TX;
pf_wb_data_o <= s_DTX;
--! @brief Process that controls the retries of the wishbone interface
--! @param wb_clk Main clock
......@@ -153,16 +147,13 @@ begin
wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0');
wb_master_addr_o <= (others => '0');
-- s_DRXA <= (others => '0');
-- s_DRXB <= (others => '0');
case i2c_master_WB_BASIC_fsm is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd(15 downto 8) <= DRXB_i(15 downto 8);
s_wb_addr_rd(7 downto 0) <= DRXB_i(23 downto 16);
s_wb_addr_rd(15 downto 0) <= DRXA_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
......@@ -174,26 +165,23 @@ begin
wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT =>
pf_wb_data_o <= wb_master_data_i;
s_DTX <= wb_master_data_i;
when S2P_WB_WR_RQT =>
s_DRXA <= DRXA_i;
s_DRXB <= DRXB_i;
null;
when S2_WB_WR_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= s_DRXB;
wb_master_addr_o(7 downto 0) <= s_DRXA(31 downto 24);
wb_master_addr_o(15 downto 8) <= s_DRXA(23 downto 16);
wb_master_data_o <= DRXA_i;
wb_master_addr_o(15 downto 0) <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= s_DRXB;
wb_master_addr_o(7 downto 0) <= s_DRXA(31 downto 24);
wb_master_addr_o(15 downto 8) <= s_DRXA(23 downto 16);
wb_master_data_o <= DRXA_i;
wb_master_addr_o(15 downto 0) <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
null;
when others =>
......@@ -214,47 +202,42 @@ begin
s_wb_slave_ack <= '0';
s_wb_slave_rty <= '0';
s_wb_slave_err <= '0';
s_load_TX <= '0';
else
s_wb_slave_ack <= '0';
s_wb_slave_rty <= '0';
s_wb_slave_err <= '0';
s_load_TX <= '0';
if (wb_slave_stb_i = '1' and wb_slave_cyc_i = '1')
and s_wb_slave_ack = '0'
and s_wb_slave_rty = '0'
and s_wb_slave_err = '0' then
case wb_slave_we_i is
when '1' =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
s_CTR0 <= f_CTR0(wb_slave_data_i);
when c_DTX_addr =>
s_DTX <= wb_slave_data_i;
s_load_TX <= '1';
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
when others =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
when c_LT_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_LT);
when c_DTX_addr =>
wb_slave_data_o <= s_DTX;
when c_DRXA_addr =>
wb_slave_data_o <= s_DRXA;
when c_DRXB_addr =>
wb_slave_data_o <= s_DRXB;
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
end case;
if ( (wb_slave_stb_i = '1' and wb_slave_cyc_i = '1')
and s_wb_slave_ack = '0'
and s_wb_slave_rty = '0'
and s_wb_slave_err = '0') then
case wb_slave_we_i is
when '1' =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
s_CTR0 <= f_CTR0(wb_slave_data_i);
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
when others =>
s_wb_slave_ack <= '1';
case s_wb_slave_addr is
when c_CTR0_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
when c_LT_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_LT);
when c_DTX_addr =>
wb_slave_data_o <= s_DTX;
when c_DRXA_addr =>
wb_slave_data_o <= DRXA_i;
when c_DRXB_addr =>
wb_slave_data_o <= DRXB_i;
when others =>
s_wb_slave_ack <= '0';
s_wb_slave_err <= '1';
end case;
end case;
end if;
end if;
end if;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 67ca4cac
......@@ -75,8 +75,6 @@ entity i2c_slave_core is
LT_o : out STD_LOGIC_VECTOR (r_LT'a_length - 1 downto 0);
DRXA_o : out STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_o : out STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DTX_i : in STD_LOGIC_VECTOR (r_DTX'a_length - 1 downto 0);
load_TX : in STD_LOGIC;
-- Alarms for controlling the i2c states
pf_wb_addr_o : out STD_LOGIC;
......@@ -160,18 +158,13 @@ signal s_byte_cnt : NATURAL;
signal s_byte_cnt_rst : STD_LOGIC;
signal s_byte_cnt_en : STD_LOGIC := '0';
-- TX FIFO (FIFO_dispatcher) signals
signal s_tx_fifo_load_TX : STD_LOGIC;
signal s_tx_fifo_flush : STD_LOGIC;
signal s_tx_fifo_oen : STD_LOGIC;
signal s_tx_fifo_reg_o : STD_LOGIC_VECTOR (c_DATA_WIDTH -1 downto 0);
-- Interrupting signals (i2c_bit.vhd)
signal s_start_o : STD_LOGIC;
signal s_pause_o : STD_LOGIC;
signal s_rcved_o : STD_LOGIC;
signal s_pf_wb_data : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
signal s_pf_wb_data_arr : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
signal s_watchdog_cnt_rst : STD_LOGIC;
signal s_watchdog_cnt_slv : STD_LOGIC_VECTOR(c_WATCHDOG_WIDTH - 1 downto 0);
......@@ -230,8 +223,10 @@ begin
p_sda_o: process(i2c_SLA_fsm,
s_bit_cnt_slv(0))
variable v_bit_inv : UNSIGNED(2 downto 0);
variable v_bit_order : NATURAL;
-- variable v_bit_inv : UNSIGNED(2 downto 0);
-- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0);
variable v_pf_wb_data : STD_LOGIC_VECTOR(0 to 31);
begin
case i2c_SLA_fsm is
when S2A_I2C_ADDR_ACK =>
......@@ -243,9 +238,11 @@ begin
when S5W1A_I2C_ADDR_ACK =>
s_sda_o <= '0';
when S5W2_WRITE_SDA =>
v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(2 downto 0)));
v_bit_order := to_integer(v_bit_inv);
s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
-- v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(2 downto 0)));
-- v_bit_order := to_integer(v_bit_inv);
-- s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0);
s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
when others =>
s_sda_o <= '1';
end case;
......@@ -281,10 +278,10 @@ begin
procedure shift_DRX is
begin
s_DRX_slv(s_DRX_slv'length - 1) <= s_rcved_o;
for i in 1 to s_DRX_slv'length - 1 loop
s_DRX_slv(i-1) <= s_DRX_slv(i);
s_DRX_slv(i) <= s_DRX_slv(i-1);
end loop;
s_DRX_slv(0) <= s_rcved_o;
end procedure;
begin
......@@ -367,21 +364,8 @@ begin
end if;
end process;
DRXA_o <= s_DRXA_slv;
DRXB_o <= s_DRXB_slv;
-- tx_fifo_i2c: FIFO_dispatcher
-- generic map(g_data_width => c_DATA_WIDTH,
-- g_dispatcher_depth => c_TX_STACK_DEPTH)
-- port map(reg_i(7 downto 0) => s_DTX_slv(31 downto 24),
-- reg_i(15 downto 8) => s_DTX_slv(23 downto 16),
-- reg_i(23 downto 16) => s_DTX_slv(15 downto 8),
-- reg_i(31 downto 24) => s_DTX_slv(7 downto 0),
-- clk => clk,
-- load => s_tx_fifo_load_TX,
-- flush => s_tx_fifo_flush,
-- oen_i => s_tx_fifo_oen,
-- reg_o => s_tx_fifo_reg_o);
DRXA_o <= s_DRXA_slv;
DRXB_o <= s_DRXB_slv;
--! @brief process to update the signals that drive bit_counter_8
--! @param i2c_SLA_fsm Current value of the i2c fsm
......@@ -437,15 +421,7 @@ begin
s_bit_cnt_rst <= '1';
end if;
when S5W2_WRITE_SDA =>
if s_byte_cnt = s_CTR0.BIA then
if i2c_SLA_fsm_d0 = S3A_WISHBONE_ADDR_ACK then
s_byte_cnt_rst <= '1';
end if;
end if;
if i2c_SLA_fsm_d0 = S5W1A_I2C_ADDR_ACK
or i2c_SLA_fsm_d0 = S5W2A_WRITE_SDA_ACK then
s_bit_cnt_rst <= '1';
end if;
null;
when S5W2A_WRITE_SDA_ACK =>
if i2c_SLA_fsm_d0 = S5W2_WRITE_SDA then
s_bit_cnt_rst <= '1';
......@@ -581,11 +557,9 @@ begin
when S2_I2C_ADDR =>
if s_bit_done = '1' then
if s_bit_cnt = 7 then
if s_DRX_slv(s_DRX_slv'length - 1 downto
s_DRX_slv'length - 1 - 6) = "0000000"
or s_DRX_slv(s_DRX_slv'length - 1 downto
s_DRX_slv'length - 1 - 6) =
s_i2c_addr(7 downto 1) then
if s_DRX_slv(6 downto 0) = "0000000"
or s_DRX_slv(6 downto 0) =
STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR) then
i2c_SLA_fsm <= S2A_I2C_ADDR_ACK;
else
i2c_SLA_fsm <= S2NA_I2C_ADDR_NACK;
......@@ -596,12 +570,10 @@ begin
when S2A_I2C_ADDR_ACK =>
if s_bit_done = '1' then
i2c_SLA_fsm <= S3_WISHBONE_ADDR;
check_start_stop;
end if;
when S2NA_I2C_ADDR_NACK =>
if s_bit_done = '1' then
i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
check_start_stop;
end if;
when S3_WISHBONE_ADDR =>
if s_bit_done = '1' then
......@@ -616,7 +588,6 @@ begin
i2c_SLA_fsm <= S3_WISHBONE_ADDR;
else
i2c_SLA_fsm <= S4_DETECT_OPERATION;
check_start_stop;
end if;
end if;
when S4_DETECT_OPERATION =>
......@@ -643,7 +614,6 @@ begin
i2c_SLA_fsm <= S5R_READ_SDA;
else
i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
check_start_stop;
end if;
end if;
when S5W0_RESTART =>
......@@ -651,11 +621,9 @@ begin
when S5W1_I2C_ADDR =>
if s_bit_done = '1' then
if s_bit_cnt = 7 then
if s_DRX_slv(s_DRX_slv'length - 1 downto
s_DRX_slv'length - 1 - 6) = "0000000"
or s_DRX_slv(s_DRX_slv'length - 1 downto
s_DRX_slv'length - 1 - 6) =
s_i2c_addr(7 downto 1) then
if s_DRX_slv(6 downto 0) = "0000000"
or s_DRX_slv(6 downto 0) =
STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR) then
i2c_SLA_fsm <= S5W1A_I2C_ADDR_ACK;
else
i2c_SLA_fsm <= S5W1NA_I2C_ADDR_NACK;
......@@ -666,16 +634,14 @@ begin
when S5W1A_I2C_ADDR_ACK =>
if s_bit_done = '1' then
i2c_SLA_fsm <= S5W2_WRITE_SDA;
check_start_stop;
end if;
when S5W1NA_I2C_ADDR_NACK =>
if s_bit_done = '1' then
i2c_SLA_fsm <= S6_WAIT_START_PAUSE;
check_start_stop;
end if;
when S5W2_WRITE_SDA =>
if s_bit_done = '1' then
if s_bit_cnt = 7 then
if s_bit_cnt = 8 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
end if;
--! It can be removed, never reached
......@@ -706,8 +672,6 @@ begin
i2c_SLA_fsm <= R0_RESET;
check_start_stop;
end if;
else
--!TODO Implement here a watchdog
end if;
when S7_PAUSE_DETECT =>
i2c_SLA_fsm <= R0_RESET;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 67ca4cac
......@@ -173,9 +173,7 @@ package i2c_slave_pkg is
LT_o : out STD_LOGIC_VECTOR (r_LT'a_length - 1 downto 0);
DRXA_o : out STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_o : out STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DTX_i : in STD_LOGIC_VECTOR (r_DTX'a_length - 1 downto 0);
load_TX : in STD_LOGIC;
pf_wb_addr_o : out STD_LOGIC;
pf_wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
rd_done_o : out STD_LOGIC;
......@@ -212,8 +210,6 @@ package i2c_slave_pkg is
LT_i : in STD_LOGIC_VECTOR (r_LT'a_length - 1 downto 0);
DRXA_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DRXB_i : in STD_LOGIC_VECTOR (r_DRX'a_length - 1 downto 0);
DTX_o : out STD_LOGIC_VECTOR (r_DTX'a_length - 1 downto 0);
load_TX : out STD_LOGIC;
pf_wb_addr_i : in STD_LOGIC;
pf_wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 67ca4cac
......@@ -74,9 +74,7 @@ architecture Behavioral of i2c_slave_top is
signal s_DRXA : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_DRXB : STD_LOGIC_VECTOR(r_DRX'a_length - 1 downto 0);
signal s_DTX : STD_LOGIC_VECTOR(r_DTX'a_length - 1 downto 0);
signal s_load_TX : STD_LOGIC;
signal s_pf_wb_addr : STD_LOGIC;
signal s_pf_wb_data : STD_LOGIC_VECTOR(31 downto 0);
signal s_rd_done : STD_LOGIC;
......@@ -109,9 +107,7 @@ begin
LT_o => s_LT_slv,
DRXA_o => s_DRXA,
DRXB_o => s_DRXB,
DTX_i => s_DTX,
load_tx => s_load_tx,
pf_wb_addr_o => s_pf_wb_addr,
pf_wb_data_i => s_pf_wb_data,
rd_done_o => s_rd_done,
......@@ -152,8 +148,6 @@ begin
LT_i => s_LT_slv,
DRXA_i => s_DRXA,
DRXB_i => s_DRXB,
DTX_o => s_DTX,
load_tx => s_load_tx,
i2c_addr_i => i2c_addr_i);
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ 67ca4cac
......@@ -14,7 +14,8 @@ entity i2c_master_driver is
generic(g_WR_DATA_LENGTH : NATURAL := 32;
g_RD_DATA_LENGTH : NATURAL := 32;
g_WB_ADDR_LENGTH : NATURAL := 16;
g_SCL_PERIOD : TIME := 250 us);
g_SCL_PERIOD : TIME := 250 us;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
sda_master_i : in STD_LOGIC;
......@@ -48,7 +49,7 @@ architecture Behavioral of i2c_master_driver is
DATA3);
file s_file_handler : TEXT;
constant c_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt";
--! constant c_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt";
constant sep : CHARACTER := ht;
signal s_scl_clk : STD_LOGIC := '1';
......@@ -62,9 +63,13 @@ architecture Behavioral of i2c_master_driver is
signal s_active_link : STD_LOGIC := '0';
signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0);
signal s_DTX : STD_LOGIC_VECTOR(0 to 31) := (others => '0');
begin
file_open(s_file_handler, c_LOG_PATH, WRITE_MODE);
file_open(s_file_handler, g_LOG_PATH, WRITE_MODE);
sda_master_o <= s_sda_master_o;
scl_master_o <= s_scl_clk when s_active_link = '1'
......@@ -74,6 +79,8 @@ begin
write_done_o <= s_write_done;
read_done_o <= s_read_done;
rd_data_o <= s_DTX;
scl_clk_process: process
begin
s_scl_clk <= not(s_scl_clk);
......@@ -83,7 +90,7 @@ begin
p_sda: process
variable v_bit_number : NATURAL := 0;
variable v_write_data : STD_LOGIC_VECTOR(g_RD_DATA_LENGTH - 1 downto 0);
variable v_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0);
--! @brief Function that returns strings for the acked field to be
--! logged.
......@@ -114,6 +121,17 @@ begin
return v_return;
end function;
function order_i2c_addr_op(
i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0))
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(7 downto 0);
begin
for i in 0 to 7 loop
v_return(7-i) := i2c_addr_op(i);
end loop;
return v_return;
end function;
--! @brief Function to reorder data before being sent by driver
--! through SDA
--! @param data Data to be reordered before being sent
......@@ -149,7 +167,7 @@ begin
procedure send_byte(byte : STD_LOGIC_VECTOR(7 downto 0)) is
begin
--! This comes from a falling edge
for i in 0 to 7 loop
for i in 7 downto 0 loop
wait for g_SCL_PERIOD/4;
s_sda_master_o <= byte(i);
wait until falling_edge(s_scl_clk);
......@@ -184,10 +202,10 @@ begin
wait until falling_edge(s_scl_clk);
end procedure;
begin
if start_i = '1' then
--! @brieg Procedure to start/restart I2C communication
procedure start_I2c is
begin
s_sda_master_o <= '1';
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
......@@ -197,22 +215,87 @@ begin
s_start_done <= '1';
wait until rising_edge(tb_clk);
s_start_done <= '0';
elsif pause_i = '1' then
end procedure;
--! @brief Procedure to pause I2c communication
procedure pause_I2C is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
s_sda_master_o <= '0';
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '1';
s_active_link <= '1';
--! We allow one clock to let i2c_slave_core.vhd to react
wait until rising_edge(tb_clk);
s_pause_done <= '1';
wait until rising_edge(tb_clk);
s_pause_done <= '0';
s_active_link <= '0';
end procedure;
procedure read_bit is
variable v_bit_rcv : STD_LOGIC;
begin
wait until rising_edge(s_scl_clk);
v_bit_rcv := sda_master_i;
for i in 0 to (g_SCL_PERIOD/2)/(1 ns) - 1 loop
if v_bit_rcv /= sda_master_i then
--! Here we report an error
end if;
wait for 1 ns;
end loop;
wait until falling_edge(s_scl_clk);
s_DTX(s_DTX'length - 1) <= v_bit_rcv;
end procedure;
procedure shift_bit is
begin
for i in 1 to s_DTX'length - 1 loop
s_DTX(i-1) <= s_DTX(i);
end loop;
end procedure;
procedure read_byte is
begin
for i in 0 to 7 loop
read_bit;
shift_bit;
end loop;
--! At the end we are just in the falling edge of scl
end procedure;
procedure place_ack is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
wait until falling_edge(s_scl_clk);
s_sda_master_o <= '1';
end procedure;
procedure place_nack is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '1';
s_active_link <= '1';
wait until falling_edge(s_scl_clk);
s_pause_done <= '1';
wait for 1 ns;
s_pause_done <= '0';
s_sda_master_o <= '0';
end procedure;
begin
if start_i = '1' then
start_I2c;
elsif pause_i = '1' then
pause_I2C;
elsif write_i = '1' then
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
send_byte(i2c_addr_op_i);
v_i2c_addr_op := i2c_addr_op_i;
v_i2c_addr_op(0) := '0';
send_byte(v_i2c_addr_op);
check_ack(s_test_id, "WRITE", ADDRESS_0);
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
......@@ -232,8 +315,47 @@ begin
--! 7.- Send DATA3
send_byte(wr_data_i(31 downto 24));
check_ack(s_test_id, "WRITE", DATA3);
s_active_link <= '0';
pause_I2C;
s_write_done <= '1';
wait until rising_edge(tb_clk);
s_write_done <= '0';
elsif read_i = '1' then
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
v_i2c_addr_op := i2c_addr_op_i;
v_i2c_addr_op(0) := '0';
send_byte(v_i2c_addr_op);
check_ack(s_test_id, " READ", ADDRESS_0);
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, " READ", WISHBONE_HIGH);
--! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, " READ", WISHBONE_LOW);
--! 4.- We have to place a start condition
start_I2c;
--! 5.- Send [ADDRESS|1]
v_i2c_addr_op(7 downto 1) := i2c_addr_op_i(7 downto 1);
v_i2c_addr_op(0) := '1';
send_byte(v_i2c_addr_op);
check_ack(s_test_id, " READ", ADDRESS_0);
--! 6.- Read DATA0
read_byte;
place_ack;
--! 7.- Read DATA1
read_byte;
place_ack;
--! 8.- Read DATA2
read_byte;
place_ack;
--! 9.- Read DATA3
read_byte;
place_ack;
pause_I2C;
s_read_done <= '1';
wait until rising_edge(tb_clk);
s_read_done <= '0';
end if;
wait until rising_edge(tb_clk);
end process;
......
hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
View file @ 67ca4cac
......@@ -63,7 +63,8 @@ package i2c_tb_pkg is
generic(g_WR_DATA_LENGTH : NATURAL := c_WR_DATA_LENGTH;
g_RD_DATA_LENGTH : NATURAL := c_RD_DATA_LENGTH;
g_WB_ADDR_LENGTH : NATURAL := c_WB_ADDR_LENGTH;
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD);
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
sda_master_i : in STD_LOGIC;
......@@ -85,6 +86,20 @@ package i2c_tb_pkg is
read_done_o : out STD_LOGIC);
end component;
type I2C_master_driver_ctrl is
record
START : STD_LOGIC;
PAUSE : STD_LOGIC;
WRITE : STD_LOGIC;
READ : STD_LOGIC;
end record;
constant c_I2C_master_driver_ctrl_default : I2C_master_driver_ctrl
:=(START => '0',
PAUSE => '0',
WRITE => '0',
READ => '0');
end i2c_tb_pkg;
package body i2c_tb_pkg is
......
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ 67ca4cac
......@@ -90,6 +90,7 @@ package m25p32_pkg is
constant c_ADDR_FOOTER_PAD : STD_LOGIC_VECTOR(c_BYTES_PER_PAGE_BITS - 1
downto 0) := (others => '0');
--! Mapping of the registers
-- 5 downto 2
constant c_WB_ADDR_PADDING : STD_LOGIC_VECTOR(c_WORDS_PER_PAGE_BITS - 1
downto 2) := (others => '0');
----------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment