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Conv TTL Blocking
Commit 68b71f60 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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updated pts hdlguide

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doc/pts/pts_hdlguide.pdf
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doc/pts/pts_hdlguide.tex
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......@@ -41,7 +41,7 @@
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
03-05-2013 & 0.1 & First draft \\
27-06-2013 & 0.2 & Changed title page, layout, and updated info \\
28-06-2013 & 0.2 & Changed title page, layout, and updated info \\
\hline
\end{tabular}
}
......@@ -61,6 +61,7 @@
\section*{List of Abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
I$^2$C & Inter-Integrated Circuit (bus) \\
PTS & Production Test Suite \\
SysMon & (ELMA) System Monitor \\
\end{tabular}
......@@ -89,7 +90,7 @@ for the CONV-TTL-BLO PTS project \textcolor{red}{REFERENCE}.
The PTS system is contained within a rack containing an ELMA crate, the laptop with the
PTS software installed on it and all other accessories necessary for running tests. More
information about the PTS system can be found in \textcolor{red}{REFER USER GUIDE}.
information about the PTS system can be found in \cite{ctb-ug}.
The ELMA crate within the PTS contains a system monitor (SysMon) board that monitors
voltage levels, temperatures and controls fan speeds for the crate fans. The crate
......@@ -100,7 +101,7 @@ accessed through the serial (I$^2$C) interface on the VME P1 connector. The PTS
PTS laptop connects to the crate through \textit{telnet} and sends \textit{readreg} and
\textit{writereg} commands to the crate; the commands are translated by the SysMon to
I$^2$C transfers to the CONV-TTL-BLO. More information about this can be found in
\cite{ctb-ug} and \cite{sysmon-ug}.
\cite{ctb-ug} and \cite{sysmon-i2c}.
%======================================================================================
% SEC: Memory map
......@@ -159,7 +160,6 @@ peripheral devices in the following sections.
%======================================================================================
% SEC: Memory map
%======================================================================================
\pagebreak
\section{PTS General-Purpose Registers}
\label{sec:pts_regs}
......@@ -188,20 +188,25 @@ The board ID register contains 32 read-and-writable bits which can be
used to identify the board as the CONV-TTL-BLO. It is by default set to
read as the ASCII string \textbf{BLO2}, the hex value 0x424C4F32.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pts-csr}}
\caption{PTS CSR}
\label{fig:pts-csr}
\end{figure}
Figure~\ref{fig:pts-csr} shows the control and status register of PTS.
It consists of 16 bits of control data and 16 bits of status data. The first
four bits are used to enable various test functionality. The reset bit can be
used to reset all of the logic inside the FPGA when set (logic high). Caution
should therefore be taken when writing the CSR, as an erroneous write might
result in the whole logic resetting itself. When the logic is reset via a write
to this bit, the \textit{writereg} telnet command will return a \textit{Not acknowledged!},
as the reset bit also resets the \textit{elma\_i2c} module.
result in the whole logic resetting itself.
When the logic is reset via a write to this bit, the \textit{writereg} telnet
command will return a \textit{Not acknowledged!}, as the reset bit also resets
the \textit{elma\_i2c} module.
The RTM field in the CSR contains the status of the RTM detection lines and is
relevant within the context of the blocking pulse and RTM interface test.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pts-csr}}
\caption{PTS CSR}
\label{fig:pts-csr}
\end{figure}
\begin{table}[h]
\caption{CSR fields}
......@@ -222,20 +227,15 @@ as the reset bit also resets the \textit{elma\_i2c} module.
SLDEN & R/W & \textbf{1} -- enable status LED sequencing \newline
\textbf{0} -- disable status LED sequencing \\
RST & R/W & \textbf{1} -- Reset FPGA logic \newline
\textbf{Note:} Will reset \textit{all} FPGA logic; therefore, it also resets itself. \\
\textbf{Note:} Will reset \textit{all} FPGA logic; also resets itself. \\
\hline
\end{tabular}
}
\end{table}
The RTM field in the CSR can be used to read the status of the RTM detection
lines and is relevant within the context of the blocking pulse and RTM interface
test.
%======================================================================================
% SEC: One-wire master
%======================================================================================
\pagebreak
\section{One-Wire Master}
\label{sec:onewire}
......@@ -247,7 +247,6 @@ are described in the module's documentation \cite{onewire}.
%======================================================================================
% SEC: SPI master
%======================================================================================
\pagebreak
\section{SPI Master}
\label{sec:spi}
......@@ -258,7 +257,6 @@ interface. More information can be found in the SPI master core's documentation
%======================================================================================
% SEC: SPI master
%======================================================================================
\pagebreak
\section{Clock Information Counters}
\label{sec:clk-info}
......@@ -296,9 +294,8 @@ module. This register is a read-only register which should return the hex value
%======================================================================================
% SEC: I2C master
%======================================================================================
\pagebreak
\section{I$2$C Master}
\label{sec:clk-info}
\label{sec:i2c}
An I$2$C master interface is implemented to send commands to the SFP EEPROM. The
OpenCores I$2$C master core is used to implement the interface. More details about the
......@@ -307,7 +304,6 @@ module and the access registers can be found via its online documentation \cite{
%======================================================================================
% SEC: Pulse counters
%======================================================================================
\pagebreak
\section{Pulse Counters}
\label{sec:pulse-cnt}
......@@ -470,23 +466,21 @@ the release version of the firmware.
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\pagebreak
\section{Getting Around the Code}
\label{sec:get-around}
All of the PTS-specific firmware can be found in the \textit{conv-ttl-blo/hdl/pts/}
folder. The top-level file, \textit{conv_ttl_blo_v2.vhd}, is the main-part of the firmware
and thus shall be the topic of this short section, where its structure and guidelines
for making changes are given. Most of the top-level ports of the file have been named
according to the schematic file netlist names. The exceptions from this are due to
either net names that could not be syntactically represented in VHDL, or net names
that have been made clearer in VHDL code. Input ports are assigned to
architecture signals and signals are assigned to output ports in each code section,
as appropriate. Ports and signals usually follow the coding guidelines at
folder. The top-level file, \textit{conv\_ttl\_blo\_v2.vhd}, is the main-part of the firmware
the topic of this section, where its structure and guidelines for making changes are given.
Most of the top-level ports of the file have been named according to the schematic file netlist
names. The exceptions from this are due to either net names that could not be syntactically
represented in VHDL, or net names that have been made clearer in VHDL code. Input ports are
assigned to architecture signals and signals are assigned to output ports in each code section,
as appropriate. Ports and signals usually follow the coding guidelines at
\cite{coding-guidelines}.
\begin{figure}[h]
\centerline{\includegraphics[scale=.9]{fig/declarative}}
\centerline{\includegraphics[scale=.8]{fig/declarative}}
\caption{Declarative part of VHDL architecture}
\label{fig:declarative}
\end{figure}
......@@ -500,7 +494,7 @@ stant declarations, followed by component declarations, after which the var-
ious signals are declared.
\begin{figure}[h]
\centerline{\includegraphics[scale=.7]{fig/body}}
\centerline{\includegraphics[scale=.6]{fig/body}}
\caption{Body of VHDL architecture}
\label{fig:body}
\end{figure}
......@@ -514,6 +508,9 @@ instantiated, followed by logic necessary for each of the tests comprising PTS.
%======================================================================================
% Bibliography
%======================================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{pts_hdlguide}
......
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