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Commit 6d5780ef authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Updated multiboot and pulse test scripts 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 8f2b83fe
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test/multiboot/README.txt 0 → 100644
View file @ 6d5780ef
Before using multiboot.py, you must first generate a compatible bitstream file
it can read. This can be done by running the binary converter tool from
Micron. Download the M25P64 VHDL models from:
http://cern.ch/go/xl8m
unzip, and run converter1.1.exe from the "code/" folder.
To run the converter tool on Linux, use Wine.
Then
%> python multiboot.py
Slot no.? <give slot number of CONV-TTL-BLO card here>
Read config reg? (y/n) <'y' to read configuration registers>
Read first page? (y/n) <'y' to read the first page from the MultiBoot address
you will give later>
Write to flash? (y/n) <'y' to write bitstream data>
Are you sure? (y/n) <asks you twice, since writing takes reaaaly long>
Issue IPROG? (y/n)
Multiboot bitstream address(hex): <hex bitstream address, nominally "170000">
<if you answered 'y' on both write questions:>
Input file name: <give here the name of the file you just generated using
converter1.1.exe>
The tool will now start sending your bitstream, outputting the page address
it is currently writing to. Go grab a coffee, since this will take at least
12 mins, maybe even more if your network connection is not that good, or
you're using Windows
test/multiboot/asdf.txt deleted 100644 → 0
View file @ 8f2b83fe
This source diff could not be displayed because it is too large. You can view the blob instead.
test/multiboot/multiboot.py
View file @ 6d5780ef
......@@ -171,68 +171,38 @@ def flash_rsr():
return ret
#=============================================================================#
# MAIN "FUNCTION"
if __name__ == "__main__":
ip = "192.168.20.22" # raw_input("Crate IP? ")
user = "admin" # raw_input("Username? ")
pwd = "ADMIN" # raw_input("Password? ")
# Wait for proper slot number
while 1:
try:
slot = raw_input("Slot no.? ")
slot = int(slot)
ctb = VBCP(ip, user, pwd, slot)
break
except TypeError as e:
print "Please input a decimal slot number."
except SlotError as e:
print e.strerror
except KeyboardInterrupt:
sys.exit();
except:
print "Unexpected error: ", sys.exc_info()[0]
# Ask for multiboot address
while 1:
try:
multiboot_addr = raw_input("MultiBoot bitstream address (hex): ")
multiboot_addr = int(multiboot_addr, 16)
print '0x%06x' % multiboot_addr
break
except TypeError as e:
print "Please input a hexadecimal address!"
except KeyboardInterrupt:
sys.exit()
except:
print "Unexpected error: ", sys.exc_info()[0]
ts = time.time()
# Open VBCP connection
ctb.open_conn()
# read from flash
print "BEFORE"
#
# Read from flash
#
def _read(addr):
print "Reading 256 bytes from 0x%06X" % addr
tr0 = time.time()
rd = flash_read(multiboot_addr,256)
rd = flash_read(addr,256)
tr1 = time.time()
rd = "".join(["0x%06X " % b for b in rd])
rd = "".join(["%02X" % b for b in rd])
print rd
#
# Write to flash
#
def _write(addr):
# Ookay, now we start to write the flash
print "WRITE"
print "Writing bitstream..."
# Prepare time arrays, to calculate average time each operation takes
addr = multiboot_addr
tdat = []
twr = []
twa = []
te = []
tp = []
# Open bitstream file
f = open("conv.txt",'r')
# Ask for and open bitstream file
fname = raw_input("Input file name: ")
f = open(fname,'r')
tw0 = time.time()
......@@ -302,11 +272,14 @@ if __name__ == "__main__":
print "wait time: %2.6f" % float(sum(twa)/len(twa)) #(t5-t4)
print "page write time: %2.6f" % float(sum(tp)/len(tp))
print "total write time: %2.6f" % float(tw1-tw0)
# Finally, issue the reprogramming (IPROG) command
#
# Start IPROG sequence
#
def _iprog(addr):
print "Issuing IPROG command..."
ctb.write(MB_BASE+MB_GBBAR_OFS, 0x44 | (0x0b << 24))
ctb.write(MB_BASE+MB_MBBAR_OFS, multiboot_addr | (0x0b << 24))
ctb.write(MB_BASE+MB_MBBAR_OFS, addr | (0x0b << 24))
ctb.write(MB_BASE+MB_CR_OFS, 0x10000)
try:
ctb.write(MB_BASE+MB_CR_OFS, 0x20000)
......@@ -315,7 +288,7 @@ if __name__ == "__main__":
# Set timeout to be sixty seconds from now...
t0 = time.time()
t1 = t0 + 60
t1 = t0 + 20
# and wait for the FPGA to gracefully respond, or die trying
while (1):
......@@ -323,15 +296,126 @@ if __name__ == "__main__":
if (time.time() >= t1):
print "Timeout, IPROG unsuccessful!"
break
if ((ctb.read(0x4) & 0xFFFF) == 0x0200):
if ((ctb.read(0x4) & 0xFFFF) > 0x0200):
print "IPROG successful!"
break
except NAckError:
continue
# Close VBCP connection and print final values
def _rdcfgreg():
print "Press 'q' to end config reg readout"
while 1:
try:
reg = raw_input('Address (hex): ')
reg = int(reg, 16)
if (reg < 0x00) or (reg > 0x22):
raise ValueError
ctb.write(MB_BASE+MB_CR_OFS, (1 << 6) | reg)
val = ctb.read(MB_BASE+MB_SR_OFS)
if (val & (1 << 16)):
print "REG(0x%02X) = 0x%04X" % (reg, val & 0xFFFF)
else:
print "Status invalid!"
except ValueError:
if (reg == 'q'):
break
print "Please input a hex value in the range [0x00, 0x22] or 'q' to quit"
#=============================================================================#
# MAIN "FUNCTION"
if __name__ == "__main__":
ip = "192.168.20.22" # raw_input("Crate IP? ")
user = "admin" # raw_input("Username? ")
pwd = "ADMIN" # raw_input("Password? ")
# Wait for proper slot number
while 1:
try:
slot = raw_input("Slot no.? ")
slot = int(slot)
ctb = VBCP(ip, user, pwd, slot)
break
except TypeError as e:
print "Please input a decimal slot number."
except SlotError as e:
print e.strerror
except KeyboardInterrupt:
sys.exit();
except:
print "Unexpected error: ", sys.exc_info()[0]
# Open VBCP connection
ctb.open_conn()
# Set MB_BASE to value in pulsetest bitstream, if this bitstream is present
if (ctb.read(0x04) & 0xFFFF == 0x9999):
MB_BASE = 0x300;
# Read config reg, if user wants to
while 1:
rdcfgreg = raw_input("Read config reg? (y/n) ")
if (rdcfgreg == 'y'):
_rdcfgreg()
break
elif (rdcfgreg == 'n'):
break
# Ask else to do (read/write/iprog)
while 1:
rd = raw_input("Read first page? (y/n) ")
if (rd == 'y') or (rd == 'n'):
break
while 1:
wr = raw_input("Write to flash? (y/n) ")
if (wr == 'y'):
while 1:
wr = raw_input("Are you sure? (y/n) ")
if (wr == 'y') or (wr == 'n'):
break
break
elif (wr == 'n'):
break
while 1:
iprog = raw_input("Issue IPROG? (y/n) ")
if (iprog == 'y') or (iprog == 'n'):
break
# Ask for multiboot address
while 1:
try:
multiboot_addr = raw_input("MultiBoot bitstream address (hex): ")
multiboot_addr = int(multiboot_addr, 16)
print '0x%06x' % multiboot_addr
break
except ValueError as e:
print "Please input a hexadecimal address!"
except KeyboardInterrupt:
sys.exit()
except:
print "Unexpected error: ", sys.exc_info()[0]
# Now do something based on user selection
# read from flash
if (rd == 'y'):
_read(multiboot_addr)
# write to flash
if (wr == 'y'):
_write(multiboot_addr)
# Finally, issue the reprogramming (IPROG) command
if (iprog == 'y'):
_iprog(multiboot_addr)
# Close VBCP connection
ctb.close_conn()
# Woohoo!
tf = time.time()
print "run time: %2.6f" % float(tf-ts)
test/multiboot/outp.txt deleted 100644 → 0
View file @ 8f2b83fe
writereg 4 37 100
writereg 4 37 500
writereg 4 37 100
writereg 4 37 5d8
writereg 4 37 500
writereg 4 37 500
writereg 4 37 500
writereg 4 37 100
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
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writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
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writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
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writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
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128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
128
writereg 4 37 100
writereg 4 37 505
writereg 4 37 500
128
writereg 4 37 100
test/pulsetest/pulsetest.py
View file @ 6d5780ef
......@@ -89,70 +89,85 @@ if __name__ == "__main__":
# Setup channel delays and frequencies
farr = [0,0,0,0,0,0]
inp = ""
while (inp != 'y') and (inp != 'n'):
inp = raw_input("Enable channel 1? (y/n) ")
if (inp == 'y'):
chen |= (1 << 0);
freq = input(" freq (Hz): ")
farr[0] = freq
freq = (1/(8*(10**(-9))))/freq
ctb.write(C1FREQREG, int(freq))
#print freq
#print hex(int(freq))
inp = ""
while (inp != 'y') and (inp != 'n'):
inp = raw_input("Enable channel 2? (y/n) ")
if (inp == 'y'):
chen |= (1 << 1);
freq = input(" freq (Hz): ")
farr[1] = freq
freq = (1/(8*(10**(-9))))/freq
ctb.write(C2FREQREG, int(freq))
#print freq
#print hex(int(freq))
inp = ""
while (inp != 'y') and (inp != 'n'):
inp = raw_input("Enable channel 3? (y/n) ")
if (inp == 'y'):
chen |= (1 << 2);
freq = input(" freq (Hz): ")
farr[2] = freq
freq = (1/(8*(10**(-9))))/freq
ctb.write(C3FREQREG, int(freq))
#print freq
#print hex(int(freq))
inp = ""
while (inp != 'y') and (inp != 'n'):
inp = raw_input("Enable channel 4? (y/n) ")
if (inp == 'y'):
chen |= (1 << 3);
freq = input(" freq (Hz): ")
farr[3] = freq
freq = (1/(8*(10**(-9))))/freq
ctb.write(C4FREQREG, int(freq))
#print freq
#print hex(int(freq))
inp = ""
while (inp != 'y') and (inp != 'n'):
inp = raw_input("Enable channel 5? (y/n) ")
if (inp == 'y'):
chen |= (1 << 4);
freq = input(" freq (Hz): ")
farr[4] = freq
freq = (1/(8*(10**(-9))))/freq
ctb.write(C5FREQREG, int(freq))
#print freq
#print hex(int(freq))
#inp = ""
#while (inp != 'y') and (inp != 'n'):
# inp = raw_input("Enable channel 1? (y/n) ")
#if (inp == 'y'):
# chen |= (1 << 0);
# freq = input(" freq (Hz): ")
# if (freq > 166000):
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[0] = freq
# freq = 1/(freq * 8*(10**(-9)))
# ctb.write(C1FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
#inp = ""
#while (inp != 'y') and (inp != 'n'):
# inp = raw_input("Enable channel 2? (y/n) ")
#if (inp == 'y'):
# chen |= (1 << 1);
# freq = input(" freq (Hz): ")
# if (freq > 166000):
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[1] = freq
# freq = 1/(freq * 8*(10**(-9)))
# ctb.write(C2FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
#inp = ""
#while (inp != 'y') and (inp != 'n'):
# inp = raw_input("Enable channel 3? (y/n) ")
#if (inp == 'y'):
# chen |= (1 << 2);
# freq = input(" freq (Hz): ")
# if (freq > 166000):
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[2] = freq
# freq = 1/(freq * 8*(10**(-9)))
# ctb.write(C3FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
#inp = ""
#while (inp != 'y') and (inp != 'n'):
# inp = raw_input("Enable channel 4? (y/n) ")
#if (inp == 'y'):
# chen |= (1 << 3);
# freq = input(" freq (Hz): ")
# if (freq > 166000):
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[3] = freq
# freq = 1/(freq * 8*(10**(-9)))
# ctb.write(C4FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
#inp = ""
#while (inp != 'y') and (inp != 'n'):
# inp = raw_input("Enable channel 5? (y/n) ")
#if (inp == 'y'):
# chen |= (1 << 4);
# freq = input(" freq (Hz): ")
# if (freq > 166000):
# freq = 166000
# print "Automatically setting channel frequency to 166 kHz."
# farr[4] = freq
# freq = 1/(freq * 8*(10**(-9)))
# ctb.write(C5FREQREG, int(freq))
# #print freq
# #print hex(int(freq))
inp = ""
while (inp != 'y') and (inp != 'n'):
......@@ -161,8 +176,11 @@ if __name__ == "__main__":
if (inp == 'y'):
chen |= (1 << 5);
freq = input(" freq (Hz): ")
if (freq > 166000):
freq = 166000
print "Automatically setting channel frequency to 166 kHz."
farr[5] = freq
freq = (1/(8*(10**(-9))))/freq
freq = 1/(freq * 8*(10**(-9)))
ctb.write(C6FREQREG, int(freq))
#print freq
#print hex(int(freq))
......@@ -210,7 +228,7 @@ if __name__ == "__main__":
# time.time() returns time since start of epoch
# in seconds, so add secs, mins and hrs to that
start_time = time.time()
end_time = start_time + secs + 60*mins + 3600*hrs
end_time = start_time + secs + 60*mins + 3600*hrs
# Generate output file named according to current time
fname = time.strftime("p-%Y-%m-%d-%Hh%M", time.localtime()) + ".txt"
......@@ -239,19 +257,19 @@ if __name__ == "__main__":
f.write("------------------------------------------------------------\r\n")
secs = int(end_time - start_time)
print "pulses sent:"
print "ch 1: %d" % (secs * farr[0])
print "ch 2: %d" % (secs * farr[1])
print "ch 3: %d" % (secs * farr[2])
print "ch 4: %d" % (secs * farr[3])
print "ch 5: %d" % (secs * farr[4])
print "ch 6: %d" % (secs * farr[5])
print "ch 1: %d (%d)" % (secs * farr[0], farr[0])
print "ch 2: %d (%d)" % (secs * farr[1], farr[1])
print "ch 3: %d (%d)" % (secs * farr[2], farr[2])
print "ch 4: %d (%d)" % (secs * farr[3], farr[3])
print "ch 5: %d (%d)" % (secs * farr[4], farr[4])
print "ch 6: %d (%d)" % (secs * farr[5], farr[5])
f.write("pulses sent:\n")
f.write("ch 1: %d\n" % (secs * farr[0]))
f.write("ch 2: %d\n" % (secs * farr[1]))
f.write("ch 3: %d\n" % (secs * farr[2]))
f.write("ch 4: %d\n" % (secs * farr[3]))
f.write("ch 5: %d\n" % (secs * farr[4]))
f.write("ch 6: %d\n" % (secs * farr[5]))
f.write("ch 1: %d (%d)\n" % (secs * farr[0], farr[0]))
f.write("ch 2: %d (%d)\n" % (secs * farr[1], farr[1]))
f.write("ch 3: %d (%d)\n" % (secs * farr[2], farr[2]))
f.write("ch 4: %d (%d)\n" % (secs * farr[3], farr[3]))
f.write("ch 5: %d (%d)\n" % (secs * farr[4], farr[4]))
f.write("ch 6: %d (%d)\n" % (secs * farr[5], farr[5]))
f.write("------------------------------------------------------------\r\n")
# Read counter registers
......
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