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Conv TTL Blocking
Commit 6e24c17a authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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DOC: Editorial changes to user guide, clarification of RTM line description in memory map

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doc/ug/conv_regs.tex
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...@@ -164,9 +164,9 @@ Eg: SW1.1-- SR.SWITCHES[0] \\ SW1.2-- SR.SWITCHES[1] \\ ...@@ -164,9 +164,9 @@ Eg: SW1.1-- SR.SWITCHES[0] \\ SW1.2-- SR.SWITCHES[1] \\
\item \begin{small} \item \begin{small}
{\bf {\bf
RTM RTM
} [\emph{read-only}]: RTM detection lines cite{rtm-det} } [\emph{read-only}]: RTM detection lines \cite{rtm-det}
\\ \\
1 bit per RTM output channel \\ 1 -- line active \\ 0 -- line inactive Signals RTM presence and type of RTM board. See~\cite{rtm-det} for interpretation \\ 1 -- line active \\ 0 -- line inactive
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
...@@ -276,7 +276,7 @@ RST\_UNLOCK ...@@ -276,7 +276,7 @@ RST\_UNLOCK
\item \begin{small} \item \begin{small}
{\bf {\bf
RST RST
} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1 } [\emph{read/write}]: Reset bit - active only if RST-UNLOCK is 1
\\ \\
1 -- initiate logic reset \\ 0 -- no reset 1 -- initiate logic reset \\ 0 -- no reset
\end{small} \end{small}
......
doc/ug/ug-conv-ttl-blo.tex
View file @ 6e24c17a
...@@ -1167,6 +1167,8 @@ actual status of the RTM detection line, prior to it being inverted on the board ...@@ -1167,6 +1167,8 @@ actual status of the RTM detection line, prior to it being inverted on the board
(Figure~\ref{fig:rtm-det}). So, if an RTM detection line is \textit{Open}, its (Figure~\ref{fig:rtm-det}). So, if an RTM detection line is \textit{Open}, its
state in the SR will be a logic '1', and if it is pulled low by an RTMM/P, its state in the SR will be a logic '1', and if it is pulled low by an RTMM/P, its
state in the SR will be a logic '0'. state in the SR will be a logic '0'.
See~\cite{rtm-det} for an up-to-date interpretation of the RTM line 6-bit (3 for RTMM
board and 3 for RTMP board) pattern.
\begin{figure} \begin{figure}
\centerline{\includegraphics[width=.5\textwidth]{fig/sr-switches}} \centerline{\includegraphics[width=.5\textwidth]{fig/sr-switches}}
...@@ -1178,7 +1180,7 @@ state in the SR will be a logic '0'. ...@@ -1178,7 +1180,7 @@ state in the SR will be a logic '0'.
\centerline{\includegraphics[width=.85\textwidth]{fig/rtm-det}} \centerline{\includegraphics[width=.85\textwidth]{fig/rtm-det}}
\caption{RTM detection lines to status register} \caption{RTM detection lines to status register}
\label{fig:rtm-det} \label{fig:rtm-det}
\end{figure} \end{figure}`
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
% SUBSEC: Pulse counters % SUBSEC: Pulse counters
...@@ -1198,8 +1200,7 @@ Each channel is assigned two counters after the OR gate preceding ...@@ -1198,8 +1200,7 @@ Each channel is assigned two counters after the OR gate preceding
the pulse generator. The input counter logic, which is repeated on each channel, the pulse generator. The input counter logic, which is repeated on each channel,
is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a
TTL or a blocking input, the corresponding pulse counter is incremented and stored to one of the TTL or a blocking input, the corresponding pulse counter is incremented and stored to one of the
two channel pulse counter registers (CHxTTLPCR or CHxBLOPCR -- see Appendix~\ref{app:conv-regs}). The CHxPCR two channel pulse counter registers (CHxTTLPCR or CHxBLOPCR -- see Appendix~\ref{app:conv-regs}). The CHxTTLPCR/CHxBLOPCR is a read-write register that can be written at any time via I$^2$C with a user-defined value.
is a read-write register that can be written at any time via I$^2$C with a user-defined value.
\begin{figure}[h] \begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}} \centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
...@@ -1231,7 +1232,7 @@ The architecture of the time-tagging mechanism is shown in Figure~\ref{fig:timet ...@@ -1231,7 +1232,7 @@ The architecture of the time-tagging mechanism is shown in Figure~\ref{fig:timet
Every time a pulse arrives on a channel, a timetag sample is stored to a 128-deep Every time a pulse arrives on a channel, a timetag sample is stored to a 128-deep
ring buffer. While this ring buffer is not entirely accessible in the addressing ring buffer. While this ring buffer is not entirely accessible in the addressing
space of the FPGA, it can be read sample by sample by reading the TBCYR, TBL/HR and space of the FPGA, it can be read sample by sample by reading the TBCYR, TBLR/TBHR and
TBMR registers (see Appendix~\ref{app:conv-regs}). At the same time the timestamp is TBMR registers (see Appendix~\ref{app:conv-regs}). At the same time the timestamp is
stored into the time-tag buffer, it is also stored to the latest timestamp registers stored into the time-tag buffer, it is also stored to the latest timestamp registers
(CHxLTS*R -- see Appendix~\ref{app:conv-regs}). (CHxLTS*R -- see Appendix~\ref{app:conv-regs}).
...@@ -1263,7 +1264,7 @@ consists of a cycles value, which counts 8~ns cycles, and a TAI seconds value. ...@@ -1263,7 +1264,7 @@ consists of a cycles value, which counts 8~ns cycles, and a TAI seconds value.
Obtained and configurable via WR \\ Obtained and configurable via WR \\
Local & 8~ns & Local, unsynchronized timetag \newline Local & 8~ns & Local, unsynchronized timetag \newline
Obtained by counting the ticks of a 125~MHz clock signal \newline Obtained by counting the ticks of a 125~MHz clock signal \newline
Configurable by writing the TAI value registers (TVL/HR) \\ Configurable by writing the TAI value registers (TVLR/TVHR) \\
\hline \hline
\end{tabular} \end{tabular}
} }
......
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