Commit 706c104c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Add flash_load block

parent cdc38585
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := flash_load.xise
ISE_CRAP := *.b flash_load_summary.html *.tcl flash_load.bld flash_load.cmd_log *.drc flash_load.lso *.ncd flash_load.ngc flash_load.ngd flash_load.ngr flash_load.pad flash_load.par flash_load.pcf flash_load.prj flash_load.ptwx flash_load.stx flash_load.syr flash_load.twr flash_load.twx flash_load.gise flash_load.unroutes flash_load.ut flash_load.xpi flash_load.xst flash_load_bitgen.xwbt flash_load_envsettings.html flash_load_guide.ncd flash_load_map.map flash_load_map.mrp flash_load_map.ncd flash_load_map.ngm flash_load_map.xrpt flash_load_ngdbuild.xrpt flash_load_pad.csv flash_load_pad.txt flash_load_par.xrpt flash_load_summary.xml flash_load_usage.xml flash_load_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=flash_load
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/flash_load.v \
../top/flash_load.ucf \
run.tcl \
flash_load.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "flash_load"
syn_project = "flash_load.xise"
modules = {
"local" : [
"../top"
]
}
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project open flash_load.xise
process run {Generate Programming File} -force rerun_all
files = [
"flash_load.v",
"flash_load.ucf"
]
net "MOSI" LOC = "AB20";
net "MISO" LOC = "AA20";
net "DRCK1" LOC = "Y20";
net "CSB" LOC = "AA3";
module flash_load
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
reg TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN6 BSCAN_SPARTAN6_inst
(
.CAPTURE(CAPTURE),
.DRCK(DRCK1),
.RESET(RESET),
.RUNTEST(),
.SEL(SEL1),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO(TDO1)
);
assign CSB = !(CS_GO && !CS_STOP);
assign RAM_DI = MISO;
always@(posedge DRCK1)
TDO1 <= RAM_DO;
wire rst = CAPTURE || RESET || UPDATE || !SEL1;
always @(negedge DRCK1 or posedge rst)
if (rst)
begin
have_header <= 0;
CS_GO_PREP <= 0;
CS_STOP <= 0;
end
else
begin
CS_STOP <= CS_STOP_PREP;
if (!have_header)
begin
if (header[46:15] == 32'h59a659a6)
begin
len <= {header [14:0],1'b0};
have_header <= 1;
if ({header [14:0],1'b0} != 0)
begin
CS_GO_PREP <= 1;
end
end
end
else if (len != 0)
begin
len <= len -1;
end // if (!have_header)
end // else: !if(CAPTRE || RESET || UPDATE || !SEL1)
always @(posedge DRCK1 or posedge rst)
if (rst)
begin
CS_GO <= 0;
CS_STOP_PREP <= 0;
RAM_WADDR <= 0;
RAM_RADDR <=0;
RAM_WE <= 0;
end
else
begin
RAM_RADDR <= RAM_RADDR + 1;
RAM_WE <= !CSB;
if(RAM_WE)
RAM_WADDR <= RAM_WADDR + 1;
header <= {header[46:0], TDI};
CS_GO <= CS_GO_PREP;
if (CS_GO && (len == 0))
CS_STOP_PREP <= 1;
end // else: !if(CAPTURE || RESET || UPDATE || !SEL1)
endmodule
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