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Conv TTL Blocking
Commit 722c523e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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I2C bridge started working, the top two bytes of sending are masked.

parent 8c7ba3fa
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hdl/IMAGES/image1/project/image1.gise
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hdl/IMAGES/image1/project/image1.xise
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hdl/IMAGES/image1/rtl/image1_core.vhd
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hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 722c523e
library IEEE;
library work;
library modelsim_lib;
use modelsim_lib.util.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL;
......@@ -24,6 +22,7 @@ architecture behavior of image1_top_tb is
constant c_CLK20M : TIME := 50 ns;
constant c_wb_clk_per : time := 20 ns;
--! ========================================================================
--! Signals for the image1_top module
--! ========================================================================
......@@ -75,7 +74,7 @@ architecture behavior of image1_top_tb is
:= c_I2C_master_driver_ctrl_default;
signal s_I2C_driver_ctrl_done : I2C_master_driver_ctrl;
signal wb_clk : STD_LOGIC;
signal wb_clk : STD_LOGIC := '0';
signal s_rst_SYS_A : STD_LOGIC_VECTOR(c_RST_A_CLKS - 1 downto 0);
signal s_rst : STD_LOGIC;
......@@ -91,6 +90,9 @@ architecture behavior of image1_top_tb is
signal s_test : STD_LOGIC;
signal tb_state : t_tb_state;
signal gsr : std_logic;
begin
s_MULTIBOOT_regs_slv <= f_STD_LOGIC_VECTOR(s_MULTIBOOT_regs);
......@@ -122,6 +124,29 @@ begin
wait for c_PLL_IN_PERIOD/2;
end process;
p_gsr: process
begin
gsr <= '1';
wait for 200 ns;
gsr <= '0';
wait;
end process p_gsr;
p_rst: process
begin
s_rst_n <= '0';
wait until gsr = '0';
wait for 5 us;
s_rst_n <= '1';
wait;
end process p_rst;
p_wbclk: process
begin
wb_clk <= not wb_clk;
wait for c_wb_clk_per;
end process p_wbclk;
--! @brief Process to bypass internal signals requiered for correct
--! use of i2c_master_driver
......@@ -170,6 +195,7 @@ begin
generic map(g_SCL_PERIOD => c_SCL_I2C_DRIVER_PERIOD,
g_LOG_PATH => "../test/log/i2c_master_driver.txt")
port map(tb_clk => wb_clk,
rst_n => s_rst_n,
sda_master_i => s_I2C_master_i.SDA,
sda_master_o => s_I2C_master_o.SDA,
......@@ -190,7 +216,7 @@ begin
read_done_o => s_i2c_driver_ctrl_done.READ);
uut: image1_top
generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
-- generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(RST_N => s_RST_N,
CLK20_VCXO => s_CLK20_VCXO,
FPGA_CLK_P => s_FPGA_CLK_P,
......@@ -250,6 +276,7 @@ begin
procedure start_I2C is
begin
s_I2C_driver_ctrl.START <= '1';
assert false report "start condition to master" severity note;
wait until rising_edge(s_I2C_driver_ctrl_done.START);
wait until rising_edge(wb_clk);
s_I2C_driver_ctrl.START <= '0';
......@@ -302,8 +329,9 @@ begin
tb_state <= ST_INIT;
wait until rising_edge(s_rst_n);
initial_inputs;
wait until falling_edge(s_rst);
-- wait until falling_edge(s_rst);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
--! First we place a write
......@@ -313,25 +341,28 @@ begin
--! Please check in the wave.do file the internal register
--! against the s_DTX register in the i2c_master_driver!
--! [0] Reading I2C registers
tb_state <= ST_READ_CTR0;
start_I2C;
assert false report "-------read ctr0" severity note;
read_I2C(s_FPGA_GA, c_I2C_CTR0_addr);
assert false report "-------done!" severity note;
assert false report "Read I2C CTR0" severity note;
assert f_STD_LOGIC_VECTOR(s_I2C_regs.CTR0)
= s_rd_data report "Mismatch in I2C CTR0 readback"
severity Error;
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
-- tb_state <= ST_WRITE_LED;
--
-- start_i2c;
-- assert false report "-------writing" severity note;
-- write_i2c(s_fpga_ga, x"0080", x"00000055");
-- assert false report "-------done!" severity note;
--
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
tb_state <= ST_WRITE_LED;
start_i2c;
assert false report "-------writing" severity note;
write_i2c(s_fpga_ga, x"0080", x"00000055");
assert false report "-------done!" severity note;
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
tb_state <= ST_READ_LED;
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ 722c523e
......@@ -20,7 +20,7 @@ package image1_top_tb_pkg is
:= work.image1_pkg.c_NUMBER_OF_CHANNELS;
component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
-- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
......@@ -37,12 +37,12 @@ package image1_top_tb_pkg is
LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(6 downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(6 downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(6 downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(6 downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
......
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @ 722c523e
......@@ -2,7 +2,14 @@
1 OK READ WISHBONE HIGH
1 OK READ WISHBONE LOW
1 OK READ [ADDRESS|0]
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
2 OK WRITE [ADDRESS|0]
2 OK WRITE WISHBONE HIGH
2 OK WRITE WISHBONE LOW
2 OK WRITE READ DATA 0
2 OK WRITE READ DATA 1
2 OK WRITE READ DATA 2
2 OK WRITE READ DATA 3
3 OK READ [ADDRESS|0]
3 OK READ WISHBONE HIGH
3 OK READ WISHBONE LOW
3 OK READ [ADDRESS|0]
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 722c523e
......@@ -99,15 +99,19 @@ signal s_wb_master_we_o : STD_LOGIC;
signal s_wb_master_ack_retries : STD_LOGIC_VECTOR(c_RETRY_LENGTH - 1 downto 0)
:= (others => '0');
signal s_wb_addr_rd : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
attribute keep : string;
signal wbm_dat_out : std_logic_vector(31 downto 0);
attribute keep of wbm_dat_out : signal is "true";
begin
wb_master_we_o <= s_wb_master_we_o;
s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i);
wb_master_data_o <= wbm_dat_out;
wb_slave_ack_o <= s_wb_slave_ack;
wb_slave_rty_o <= s_wb_slave_rty;
......@@ -161,7 +165,7 @@ begin
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0');
wbm_dat_out <= (others => '0');
wb_master_addr_o <= (others => '0');
s_dtx <= (others => '0');
else
......@@ -191,14 +195,14 @@ begin
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i);
wbm_dat_out <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i);
wbm_dat_out <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
-- null;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 722c523e
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
-- Engineers: Carlos Gil Soriano
-- Theodor-Adrian Stana
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
......@@ -170,15 +171,10 @@ signal s_watchdog_cnt_rst : STD_LOGIC;
signal s_watchdog_cnt_slv : STD_LOGIC_VECTOR(c_WATCHDOG_WIDTH - 1 downto 0);
signal s_watchdog_cnt : NATURAL;
attribute keep : string;
signal s_dummy : std_logic_vector(0 to 31);
attribute keep of s_dummy : signal is "true";
signal txsr : std_logic_vector(31 downto 0);
begin
s_dummy(0 to 31) <= f_ch_endian(s_pf_wb_data(31 downto 0));
s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
......@@ -228,8 +224,22 @@ begin
sda_o <= s_sda_o;
p_sda_o: process(i2c_SLA_fsm,
s_bit_cnt_slv(0))
-- Process to control the TX shift register
-- p_txsr: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- txsr <= (others => '0');
-- elsif (i2c_sla_fsm = S5W1A_I2C_ADDR_ACK) then
-- txsr <= f_ch_endian(pf_wb_data_i);
-- elsif (i2c_sla_fsm = S5W2_WRITE_SDA) then
-- txsr <= txsr(30 downto 0) & '0';
-- end if;
-- end if;
-- end process p_txsr;
p_sda_o: process(i2c_SLA_fsm, txsr)
-- variable v_bit_inv : UNSIGNED(2 downto 0);
-- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0);
......@@ -253,9 +263,11 @@ begin
v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0); -- f_ch_endian(s_pf_wb_data(31 downto 0));
-- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
-- v_pf_wb_data(0 to 31) := f_ch_endian(s_pf_wb_data(31 downto 0));
-- -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
-- s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
s_sda_o <= txsr(31);
when others =>
s_sda_o <= '1';
end case;
......@@ -553,6 +565,7 @@ begin
if rst_i = '1'
or s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
i2c_SLA_fsm <= R0_RESET;
txsr <= (others => '0');
else
case i2c_SLA_fsm is
when R0_RESET =>
......@@ -634,7 +647,7 @@ begin
when S5W1_I2C_ADDR =>
if s_bit_done = '1' then
if s_bit_cnt = 7 then
if s_DRX_slv(6 downto 0) = "0000000"
if s_DRX_slv(6 downto 0) = "0000000" -- ????????????????
or s_DRX_slv(6 downto 0) =
STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR) then
i2c_SLA_fsm <= S5W1A_I2C_ADDR_ACK;
......@@ -645,6 +658,7 @@ begin
check_start_stop;
end if;
when S5W1A_I2C_ADDR_ACK =>
txsr <= f_ch_endian(pf_wb_data_i);
if s_bit_done = '1' then
i2c_SLA_fsm <= S5W2_WRITE_SDA;
end if;
......@@ -654,6 +668,7 @@ begin
end if;
when S5W2_WRITE_SDA =>
if s_bit_done = '1' then
txsr <= txsr(30 downto 0) & '0';
if s_bit_cnt = 8 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
end if;
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ 722c523e
......@@ -17,6 +17,7 @@ entity i2c_master_driver is
g_SCL_PERIOD : TIME := 250 us;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
......@@ -283,13 +284,23 @@ begin
s_sda_master_o <= '0';
end procedure;
variable first : boolean := true;
begin
if (first = true) then
wait until rst_n = '1';
first := false;
end if;
if start_i = '1' then
assert false report "mst start" severity note;
start_I2c;
elsif pause_i = '1' then
assert false report "mst pause" severity note;
pause_I2C;
elsif write_i = '1' then
assert false report "mst write" severity note;
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
......@@ -320,6 +331,7 @@ begin
wait until rising_edge(tb_clk);
s_write_done <= '0';
elsif read_i = '1' then
assert false report "mst read" severity note;
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
......@@ -357,7 +369,9 @@ begin
wait until rising_edge(tb_clk);
s_read_done <= '0';
end if;
wait until rising_edge(tb_clk);
end process;
end;
hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
View file @ 722c523e
......@@ -66,6 +66,7 @@ package i2c_tb_pkg is
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC;
......
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