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Commit 7680408f authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Released V1.0 of Transfer Knowledge document

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doc/TransferKnowledge/report.bib 0 → 100644
View file @ 7680408f
@misc{StdBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{FunSpecs,
author = "C. Gil Soriano",
title = {{Standard Blocking Repeater in VME64x Format, Functional Specifications}},
month = aug,
year = 2012,
note = "{\url{http://www.ohwr.org/documents/104}}"
}
@misc{TechFlyback,
author = "C. Gil Soriano",
title = {{Flyback circuit outputting Standard Blocking for CTDAH}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/110}}"
}
@misc{BlockingMono,
author = "C. Gil Soriano",
title = {{A Triggered Monostable Blocking Oscillator Used in legacy Channel
Repeaters}},
month = aug,
year = 2012,
note = "{\url{http://www.ohwr.org/documents/94}}"
}
@misc{issuesReportV1,
author = "C. Gil Soriano",
title = {{Report of issues in CONV-TTL-BLO v1.0 EDA-02446-V1-0}},
month = oct,
year = 2012,
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/pcb/doc/issues/conv-ttl-blo?rev=basic_trigger_addingGenerics}}"
}
@TECHREPORT{I2Cdoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{I2C Slave to Wishbone Master module}",
month = nov,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/i2c_slave_wb_master/doc/i2cSpecs.pdf}}"
}
@TECHREPORT{SPIdoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{SPI master multifield HDL core}",
month = oct,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/spi_master_multifield/doc/spiSpecs.pdf}}"
}
@TECHREPORT{M25P32doc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{m25p32 manager HDL core}",
month = oct,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/m25p32/doc/m25p32.pdf}}"
}
@TECHREPORT{multibootDoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{Multiboot HDL module}",
month = jan,
year = 2013,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/multiboot/doc/multiboot.pdf}}"
}
@TECHREPORT{ELMAspecI2C,
author = "S. Iglesias Gonsalvez",
institution = "CERN, BE-CO-HT",
title = "{ELMA Crates Specification, Access to board data using
SNMP and I2C}",
month = feb,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/227}}"
}
@TECHREPORT{ELMAsysMonDoc,
institution = "ELMA",
title = "{NEW Sysmon Manual}",
number = "v1.11",
note = "{\url{http://www.ohwr.org/documents/226}}"
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@TECHREPORT{UG381,
institution = "Xilinx Inc.",
title = "{Spartan-6 FPGA SelectIO Resources}",
month = dec,
year = 2010,
number = "v1.4",
note =
"{\url{http://www.xilinx.com/support/documentation/user_guides/ug381.pdf}}"
}
@TECHREPORT{,
institution = "Xilinx Inc.",
title = "{}",
month = jan,
year = 2012,
number = "v0.9",
note =
"{\url{}}"
}
@TECHREPORT{,
institution = "Xilinx Inc.",
title = "{}",
month = jan,
year = 2012,
number = "v0.9",
note =
"{\url{}}"
}
doc/TransferKnowledge/report.tex
View file @ 7680408f
......@@ -14,7 +14,7 @@
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{
\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{January 18, 2012}
\date{January 22, 2012}
\hypersetup{
colorlinks = true,
urlcolor = blue
......@@ -25,6 +25,7 @@
pdfkeywords = {Blocking, Pulse repetition, legacy systems, basic
functionality, extended functionality, ELMA SPI, VHDL}
}
\pagenumbering{roman}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
......@@ -62,16 +63,24 @@
\hline
0.1 & Preliminary version & January 10, 2012\\
\hline
1.0 & Final version & January 18, 2012\\
1.0 & Final version & January 22, 2012\\
\hline
\end{tabularx}
\end{center}
\pagebreak
\pagestyle{plain}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoftables
\pagebreak
\listoffigures
\pagebreak
\pagenumbering{arabic}
\pagestyle{plain}
\setcounter{page}{1}
\section{Level Conversion Circuit project structure}
The project aims to substitute old boards by newer ones which will be able to
......@@ -82,7 +91,7 @@
\begin{itemize}
\item \textbf{Blocking pulse}\\
The Blocking pulse is defined in the document \cite.
The Blocking pulse is defined in the document \cite{StdBlocking}.
\item \textbf{RS485 pulse}\\
The RS485 pulse has to be defined.
\end{itemize}
......@@ -178,6 +187,156 @@
offer an easy-to-plug interface to operators.
\end{itemize}
\pagebreak
\section{Repositories structure}
Both \textit{CONV-TTL-BLO} and \textit{CONV-TTL-RS485} share the same
global structure:
\begin{itemize}
\item \textbf{doc}
\item \textbf{hdl}
\item \textbf{pcb}
\end{itemize}
\subsection{CONV-TTL-BLO}
\begin{itemize}
\item \textbf{doc}\\
It holds all the generic design documentation of the board and files
used in OHWR repo:
\begin{itemize}
\item \textbf{OHWR}\\
This subfolder contains pictures used both in the wiki pages of the
issues section.
\end{itemize}
Some extra subfolders are used: Blocking, HDL and HDLguide. The first
contains the source files and output of the documentation for
\cite{FunSpecs}, \cite{StdBlocking} and \cite{BlockingMono}.\\
\item \textbf{hdl}\\
As \textit{CONV-TTL-BLO} and \textit{CONV-TTL-RS485} will share a lot
of IP cores for either basic or extended functionality, all of the IP
cores are located in \textit{CONV-TTL-BLO}. This repository is depicted
below:\\
\begin{itemize}
\item \textbf{IMAGES}
It contains the top files for basic repetition in
\textit{CONV-TTL-BLO}:
\begin{itemize}
\item \textbf{image0}\\
This is the first bitstream with a very coarse basic repetition.
\item \textbf{image1}\\
It corresponds to the image loaded into the \textit{CONV-TTL-BLO
V1} installed in PS facilities. The logic runs at 200 MHz and the
outputs are glitch-free.
\end{itemize}
\item \textbf{basic\_trigger}\\
It contains the IP core with clocked repetition. It is the core
used in image1 bitstream.\\
\item \textbf{basic\_trigger\_async}\\
It contains the IP core with lowest achievable jitter. No profiling
in the place and route (it can lower the jitter value inyected by
the FPGA).\\
\item \textbf{ctdah\_lib}\\
This is the library that contains generic modules used along the
rest of IP cores within this project.\\
\item \textbf{i2c\_slave\_wb\_master}\\
The I2C slave IP core is located here.\\
\item \textbf{m25p32}\\
The M25P32 IP core is located here. It manages access to the Flash
Memory thanks to the SPI core developed for this project.\\
\item \textbf{multiboot}\\
The multiboot IP core is able to access Xilinx's ICAP primitive to
allow SPI Flash Memory reprogramming from a given set of
locations.\\
\item \textbf{rtm\_detector}\\
Just some files to check for proper RTM detection.\\
\item \textbf{spi\_master\_multifield}\\
The SPI master IP core can be found in this folder. It allows
SPI communication to perform writes and read-backs. It is developed
to be used together with M25P32 module.\\
\item \textbf{trigger}\\
This is the folder to work on the extended trigger functionality.\\
\item \textbf{wr\_core\_demo}\\
Some White Rabbit files to perform a test.\\
\end{itemize}
\item \textbf{pcb}\\
\begin{itemize}
\item \textbf{conv-ttl-blo}\\
Files of \textit{CONV-TTL-BLO V1}.\\
\item \textbf{conv-ttl-blo-v2}\\
Files of \textit{CONV-TTL-BLO V2}.\\
\item \textbf{conv-ttl-rtm}\\
Files of \textit{CONV-TTL-RTM V1}.\\
\item \textbf{conv-ttl-rtm-blo}\\
Files of \textit{CONV-TTL-RTM-BLO V1}.\\
\item \textbf{doc}\\
It contains all the reports of the V2 board reviews and a report
with all the issues found in V1 \cite{issuesReportV1}.\\
\end{itemize}
\end{itemize}
\subsubsection{IP core structure}
Every IP core developed (\textit{i2c\_slave\_wb\_master},
\textit{m25p32}, \textit{multiboot},\textit{spi\_master\_multifield}
and \textit{trigger}) follow the same structure:
\begin{itemize}
\item \textbf{doc}\\
It holds the source files for generating beautiful, LaTeXed
documentation, like this document.\\
\item \textbf{project}\\
It holds all the .xise, .gise files and all the temporary ones.
Inside this folder it can be found a \textit{wave.do} file
(typically inside the \textit{waveform} subfolder).\\
\item \textbf{rtl}\\
It holds all the RTL files. All the IP cores follows the following
design schema:\\
\begin{figure}[!htb]
\begin{center}
\includegraphics[scale=1,keepaspectratio]
{./Figures/IPcoreStruct.png}
\end{center}
\caption{IP core structure}
\end{figure}
The \textit{top} files interconnects the \textit{core} (which has
all the logic, controls the FSMs and the outputs) with the
\textit{regs}, responsible for controlling access to internal
registers via \textit{core} or a \textit{wishbone} interface.\\
Additionally the \textit{package} provides the definition of
constants, register structures (defined as records) and translation
functions for them to/from \textit{std\_logic\_vector}.\\
All the cores follow the ESA and CERN@BE-CO-HT good VHDL practices,
Alessandro Rubini's advices on how to write mantainable code and
the comments are \href{http://www.stack.nl/~dimitri/doxygen/}
{doxygenized}.\\
\item \textbf{test}\\
It holds all the test files but the \textit{wishbone\_driver},
which is located in ctdah\_lib folder. The test is written in VHDL
as is as structured as follows:\\
\begin{figure}[!htb]
\begin{center}
\includegraphics[scale=1,keepaspectratio]
{./Figures/testStruct.png}
\end{center}
\caption{IP core testbench structure}
\end{figure}
The dashed lines of both drivers means that the cores are not
intended to be synthesizable.\\
Some of the testbench generates a log file to quickly check the
result of the test. Some others testbenches make use of
\textit{ModelSim SignalSpy} library to be able to read and check
internal signals of given subcomponents, without the need of
modifying files (either definition of VHDL ports or adding
precompiler lines to the code).\\
\end{itemize}
\subsection{CONV-TTL-RS485}
It follows the same structure as \textit{CONV-TTL-BLO}. The IP cores to be
used in this board correspond to the ones developed for
\textit{CONV-TTL-BLO}.
\pagebreak
\section{Blocking boards replacement: CONV-TTL-BLO}
......@@ -197,7 +356,7 @@
\subsection{CONV-TTL-BLO design}
The functional specifications of CONV-TTL-BLO can be found in
\cite.
\cite{FunSpecs}.
We can divide between basic and extended functionalities.
\subsubsection{Basic functionalities}
Aimed to be fully compliant with legacy systems:
......@@ -207,10 +366,11 @@
\item Provide galvanic isolation in the links.
\item To be glitch-free.
\end{itemize}
The design of the Blocking driver follows a Flyback topology \cite, which
inherently provides galvanic isolation. So as to properly drain up the
remaining built-up magnetic current in the inductor, a snubber circuit
was added \cite.
The design of the Blocking driver follows a Flyback topology
\cite{TechFlyback}, which inherently provides galvanic isolation. So as to
properly drain up the remaining built-up magnetic current in the inductor,
a snubber circuit was added. The snubber circuit can be found in
\cite{BlockingMono}.\\
Because of the Flyback topology, the three-widing coupled inductor was
replaced by a 1:1 coupled inductor. The selection of this coupled inductor
follows the premise of minizing the chances of being out of stock in the
......@@ -440,6 +600,7 @@
The basic functionality is covered in the design used for the
\textit{CONV-TTL-BLO V1} card installed in the test loop in PS
facilities.\\
The IP core has to:
\begin{enumerate}
\item Detect and replicated received pulses once they are not considered
......@@ -450,7 +611,8 @@
The IP core sampling frequency for the inputs is 200MHz. The internal
200MHz system clock is generated from the 125MHz clock. Then the induced
sampled jitter will be 5 ns.\\
sampled jitter will have a maximum value of 5 ns.\\
The following table shows the configuration of the \textit{CONV-TTL-BLO V1}
board installed in the test sage loop in PS facilities:\\
......@@ -459,20 +621,20 @@
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|}
\hline
\textbf{Parameter} & \textbf{Value}\\
\textbf{Parameter} & \textbf{Value}\\
\hline
\hline
Pulse height & 24 volts\\
Pulse height & 24 volts\\
\hline
Pulse length & 1 $\mu$s\\
Pulse length & 1 $\mu$s\\
\hline
Pulse rise time & 75 ns\\
Pulse rise time & 80 ns\\
\hline
Pulse fall time & 95 ns\\
Pulse fall time & 100 ns\\
\hline
Minimum repetition jitter & 5 ns\\
Minimum worst-case repetition jitter & 5 ns\\
\hline
Channel LEDs blinking length & 250 ms\\
Channel LEDs blinking length & 250 ms\\
\hline
\end{tabularx}
\caption{Configuration for \textit{CONV-TTL-BLO V1} in PS safe loop test}
......@@ -481,6 +643,108 @@
\subsubsection{Extended functionality}
As said before, extended functionality consist of three main blocks:
\begin{enumerate}
\item Pulse time-tagging
\item I2C communication: access and monitoring
\item FPGA reprogramming functionality
\end{enumerate}
As points 2 and 3 represented bottlenecks for starting with the PTS,
design priority was given to them.\\
\begin{itemize}
\item \textbf{I2C communication}\\
I2C module is of paramount importance for the development of the rest of
functionalities. Being the link between FPGA and outside world, makes I2C
the first module to develop before PTS can be carried out.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|R|R|}
\hline
\textbf{IP core} & \textbf{Core} & \textbf{Test} &
\textbf{Guide}\\
\hline
\hline
\textit{I2C\_slave\_wb\_master} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/hdl/i2c_slave_wb_master/rtl?rev=master}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/hdl/i2c_slave_wb_master/test?rev=master}{Link} &
\cite{I2Cdoc}\\
\hline
\end{tabularx}
\caption{\textit{I2C\_slave\_wb\_master} IP core files and documents}
\end{center}
\end{table}
The \textit{I2C\_slave\_wb\_master} is an I2C slave core which provides
wishbone master and slave interfaces. The former one serves a bridge from
I2C to internal wishbone modules. The second one lets the
\textit{I2C\_slave\_wb\_master} core registers to be easilly accessed from
the I2C interface by by-passing the I2C wishbone master interface to the
slave. Providing these two interface lets the IP core be consistent and
homogeneous with the rest of cores designed for \textit{CONV-TTL-BLO} and
\textit{CONV-TTL-RS485}.\\
More information about the IP core can be found in its guide \cite{I2Cdoc}.\\
\item \textbf{SPI Flash Memory reprogramming}\\
In order to reprogram the SPI Flash memory different IP cores are
needed.\\
To start off, a SPI master core is needed to place SPI
transactions into the memory. It should be noted that the core developed
for that has taken into account parametric settings to meet timing.\\
Secondly a M25P32 memory handler was designed to write and read from
memory in an easy and optimal way. Memories from the same family can be
used upon some modifications in the package file. Flash pages will be
written from an internal buffer. Thus, the way to program the Flash
memory consist of writing the internal page buffer of the memory handler
and acknowledge a write into a certain page. By doing this,
in all the pages required by the raw bitstream, the new bitstream will
be loaded correctly.\\
The last of the modules corresponds with the ICAP controller, called
multiboot core. This core instanciates the Xilinx's ICAP primitive
according the Xilinx's recommendation and let the user start a load
bitstream process from the I2C via wishbone bridging.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|R|R|}
\hline
\textbf{IP core} & \textbf{Core} & \textbf{Test} &
\textbf{Guide}\\
\hline
\hline
\textit{spi\_master\_multifield} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/spi_master_multifield/rtl}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/spi_master_multifield/test}{Link} &
\cite{SPIdoc}\\
\hline
\textit{m25p32} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/m25p32/rtl}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/m25p32/test}{Link} &
\cite{M25P32doc}\\
\hline
\textit{multiboot} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/multiboot/rtl}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/multiboot/test}{Link} &
\cite{multibootDoc}\\
\hline
\end{tabularx}
\caption{SPI Flash Memory reprogramming IP cores}
\end{center}
\end{table}
\end{itemize}
\pagebreak
\section{RS485 boards replacement: CONV-TTL-RS485}
\subsection{Legacy boards}
......@@ -541,7 +805,7 @@
\end{itemize}
\pagebreak
\section{Rear Transition Module Motherboard}
\section{CONV-TTL-RTM: RTM Motherboard}
The motherboard is shared between both the CONV-TTL-BLO and the
CONV-TTL-RS485. It provides connection to piggybacks from the VME64X P2
connector.
......@@ -558,7 +822,7 @@
\href{https://edms.cern.ch/file/1160628/1/NewSysmon_Usermanual_Rev_1.11_16.02.2012.pdf}{[EDMS].}
\subsection{How to communicate}
The way ELMA crate System Monitor communicate follows the instruction
specified to Mihai Savu in \cite.
specified to Mihai Savu in \cite{ELMAspecI2C}.
Hence, to communicate effectively with both the CONV-TTL-BLO and
CONV-TTL-RS485 will consist of:
\begin{enumerate}
......@@ -566,8 +830,17 @@
\item Two bytes for Wishbone Addressing.
\item Four bytes of data.
\end{enumerate}
A complete explanation of the comunication is found in the documentation
of I2C VHDL core specifically done for this project \cite.
To send the I2C commands from ELMA crate, firstly it should be accessed via
telnet. It should be noted that the crate must be connected to the CERN
socket in which the SysMon is registered to, otherwise the device will
not have access to the network. Once accessed via telnet, two commands
can be issued \textit{writereg} and \textit{readreg}, both specified in
\cite{ELMAsysMonDoc}.\\
A comprehensive explanation of the comunication is found in the
documentation of I2C VHDL core specifically done for this project
\cite{I2Cdoc}.
\subsection{Problems}
\begin{itemize}
......@@ -589,14 +862,14 @@
Issue \textbf{537}
\end{itemize}
\pagebreak
\section{People involved in Level Conversion Circuits}
Success in a project is due to the joint work of a team. A list of all the
people involved in the project can be found in the table below.\\
I would like to take advantage of this line to thank them all again for
their help and work.\\
people involved in the project can be found in the table below. I would like
to take advantage of this line to thank them all again for their help and
work.\\
\begin{table}[!htb]
\begin{center}
......@@ -609,7 +882,7 @@
\hline
\textbf{Matthieu Cattin } & Technical supervision - Installation\\
\hline
\textbf{Tomasz Wlostoski} & Technical help\\
\textbf{Tomasz Wlostowski} & Technical help\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{Installation
......@@ -659,4 +932,51 @@
\end{center}
\end{table}
\appendix
\section{Development roadmap}
\subsection{CONV-TTL-BLO}
\begin{enumerate}
\item \textbf{Remote reprogramming}\\
Remote reprogramming is the key to wind up the development of the IP core
chain needed to perform the PTS in the boards.\\
To achieve this, the \textit{i2c\_slave\_wb\_master}, \textit{m25p32} and
\textit{multiboot} cores should be put together and thoroughly tested. It
should be noted that good understanding of Xilinx's ICAP is needed
\cite{UG380}.\\
\item \textbf{PTS}\\
After having a stable bitstream with the basic repetition plus the IP
core chain indicated above, PTS will be "easilly" carried out. That will
involve quite a lot of work.\\
Unlike other projects, such as \textit{SPEC}, in which the PTS could
send commads directly from the host computer, now the commands should be
by-passed over telnet to the SysMon.\\
\item \textbf{Pulse time-tagging}\\
To precisely time-tagging a White Rabbit core must be included in the
FPGA, then all the pulses will be logged and they will be accessible via
I2C. \textit{trigger} core should be worked on to finally meet the
requirements.\\
\item \textbf{Reduce jitter}\\
Reducing jitter means using either the asynchronous solutions in
\textit{basic\_trigger\_async} or writing an IP core using the SerDes
functionality in Xilinx's Spartan 6. A good look on \cite{} is
recommended.
\end{enumerate}
\subsection{CONV-TTL-RS485}
\begin{enumerate}
\item \textbf{Strongly discuss about datagrams parsing}\\
\textit{CONV-TTL-RS485} will offer more functionalities than
\textit{CONV-TTL-BLO}. Correct dimensioning of the
application memory should be taken into account. The memory
requirements will depend upon Jean-Claude's need for parsing
datagrams and place orders into the accelerators. External
memories could be used to improve performance.\\
\item \textbf{Producing a V2}\\
It should be kept in mind that, in order to improve jitter perfomance,
same changes in FPGA I/Os as in \textit{CONV-TTL-BLO V2} apply.\\
\end{enumerate}
\pagebreak
\bibliography{report}{}
\bibliographystyle{unsrt}
\end{document}
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