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Commit 7cc28d23 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Updated the documentation of SPI module.

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hdl/spi_master_multifield/doc/spiSpecs.tex
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......@@ -47,7 +47,8 @@
The core is specially targeted for
writing blocks of EEPROM memories which typically requiere three fields.\\
writing blocks of EEPROM memories which typically requiere three fields. In
the case you are using a m25p32 memory, please refer to \textit{m25p32 core}\\
\end{abstract}
\vspace{2cm}
......@@ -95,6 +96,8 @@ Please see the CERN OHL variable.1.1 for applicable conditions.\\
\section{Structure}
The SPI module contains several blocks related the following way:\\
-- spi\_master\_pkg.vhd
-- spi\_master\_top.vhd
----- spi\_master\_regs.vhd
......@@ -216,18 +219,20 @@ same contents over the SPI).
\hline
5-3 & x & Reserved & \textbf{"000"} \\
\hline
6 & \textbf{SEND\_DATA} & DATA bytes will be sent in & \textbf{'0'} \\
6 & \textbf{READ\_MISO} & READ bytes from MISO line & \textbf{'0'} \\
\hline
7 & \textbf{SEND\_DATA} & DATA bytes will be sent in & \textbf{'0'} \\
& & a write operation & \\
\hline
7 & \textbf{SEND\_ADDR} & ADDR bytes will be sent in & \textbf{'0'} \\
8 & \textbf{SEND\_ADDR} & ADDR bytes will be sent in & \textbf{'0'} \\
& & a write operation & \\
\hline
8 & \textbf{SEND\_INST} & INST bytes will be sent in & \textbf{'0'} \\
9 & \textbf{SEND\_INST} & INST bytes will be sent in & \textbf{'0'} \\
& & a write operation & \\
\hline
9 & \textbf{SEND\_OP} & perform a SEND OPeration & \textbf{'0'} \\
10 & \textbf{SEND\_OP} & perform a SEND OPeration & \textbf{'0'} \\
\hline
11-10 & y & Reserved & \textbf{"00"} \\
11 & y & Reserved & \textbf{"00"} \\
\hline
15-12 & \textbf{CLK\_DIV} & CLocK DIVider & \textbf{X"0"} \\
\hline
......@@ -252,15 +257,19 @@ send.\\
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
0 & \textbf{SENT\_DATA} & DATA was SENT & \textbf{'0'} \\
0 & \textbf{MISO\_DUP} & MOSI Data UPdate & \textbf{'0'} \\
\hline
1 & \textbf{READ\_DONE} & READ process DONE & \textbf{'0'} \\
\hline
2 & \textbf{SENT\_DATA} & DATA was SENT & \textbf{'0'} \\
\hline
1 & \textbf{SENT\_ADDR} & ADDRess was SENT & \textbf{'0'} \\
3 & \textbf{SENT\_ADDR} & ADDRess was SENT & \textbf{'0'} \\
\hline
2 & \textbf{SENT\_INST} & INSTruction was SENT & \textbf{'0'} \\
4 & \textbf{SENT\_INST} & INSTruction was SENT & \textbf{'0'} \\
\hline
3 & \textbf{SENT\_OP } & OPeration was SENT & \textbf{'0'} \\
5 & \textbf{SENT\_OP } & OPeration was SENT & \textbf{'0'} \\
\hline
11-4 & x & Reserved & \textbf{X"00"} \\
11-6 & x & Reserved & \textbf{X"00"} \\
\hline
15-12 & \textbf{CLK\_DIV} & CLocK DIVision & \textbf{X"0"} \\
\hline
......@@ -272,7 +281,8 @@ send.\\
\subsection{SPI3}
The SPI3 register is a read-only register.\\
It holds the data received by the MISO pin.
It holds the data received by the MISO pin. Valid data can be read as soon as
\textit{rd\_SPI3\_o} output in \textit{spi\_master\_core.vhd} goes high.
\begin{table}[!htb]
\begin{center}
......@@ -320,7 +330,7 @@ The internal registers map over the wishbone interface is as follows:\\
It consists on writing the SPI0 register first, and then the SPI1 register.
\textbf{Order must be preserved}.\\
Status of the operation can be followed via SPI2 register. SPI3 register offer
Status of the operation can be followed via SPI2 register. SPI3 register offers
the data read from the MISO line.\\
\subsubsection{SPI0 register}
......
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