Skip to content

C
Conv TTL Blocking
Commit 7ee393fc authored by gilsoriano's avatar gilsoriano
Browse files
Options

New trigger for edge detection and level contention. Debugging phase.

parent 4bcd1c14
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1290 additions and 906 deletions
hdl/ctdah_lib/rtl/ctdah_pkg.vhd
View file @ 7ee393fc
......@@ -13,28 +13,40 @@ use IEEE.STD_LOGIC_1164.all;
package ctdah_pkg is
component gc_clk_divider is
generic( g_clk_division_logSize : NATURAL := 8);
generic( g_CLK_DIVISION_LOGSIZE : NATURAL := 8);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
oe_n_i : in STD_LOGIC;
clk_o : out STD_LOGIC;
divider_i : in STD_LOGIC_VECTOR (g_clk_division_logSize - 1 downto 0) --Divides by twice the value specified
divider_i : in STD_LOGIC_VECTOR (g_CLK_DIVISION_LOGSIZE - 1 downto 0) --Divides by twice the value specified
);
end component;
component gc_counter is
generic(
g_data_width: NATURAL
);
port (
g_DATA_WIDTH : NATURAL);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_data_width-1 downto 0)
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end component;
component gc_debouncer is
generic (
g_LENGTH : INTEGER := 6);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in STD_LOGIC_VECTOR(g_LENGTH-1 downto 0)
);
end component;
component gc_ff is
port(
Q : out STD_LOGIC;
......@@ -43,46 +55,68 @@ package ctdah_pkg is
D : in STD_LOGIC
);
end component;
component gc_monostable is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(31 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end component;
component gc_RAM is
generic(g_DATA_WIDTH : INTEGER := 32;
g_ADDR_WIDTH : INTEGER := 8);
port(clka : in STD_LOGIC;
wea : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
dina : in STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
doutb : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0));
end component;
component FIFO_dispatcher is
generic(
g_data_width : NATURAL := 8;
g_dispatcher_depth : NATURAL := 4
);
g_DATA_WIDTH : NATURAL := 8;
g_DISPATCHER_DEPTH : NATURAL := 4);
port (
reg_i : in STD_LOGIC_VECTOR (g_dispatcher_depth*g_data_width-1 downto 0);
reg_i : in STD_LOGIC_VECTOR (g_DISPATCHER_DEPTH*g_DATA_WIDTH - 1 downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
flush : in STD_LOGIC;
oen_i : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
reg_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end component;
component FIFO_stack is
generic(
g_data_width : NATURAL := 8;
g_stack_depth : NATURAL := 8
g_DATA_WIDTH : NATURAL := 8;
g_STACK_DEPTH : NATURAL := 8
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
reg_i : in STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_stack_depth*g_data_width - 1 downto 0)
reg_o : out STD_LOGIC_VECTOR (g_STACK_DEPTH*g_DATA_WIDTH - 1 downto 0)
);
end component;
component FIFO_simple is
generic(
g_data_width : NATURAL := 8
g_DATA_WIDTH : NATURAL := 8
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
reg_i : in STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
reg_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end component;
......
hdl/ctdah_lib/rtl/gc_counter.vhd
View file @ 7ee393fc
......@@ -42,13 +42,13 @@ use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
g_data_width: NATURAL
g_DATA_WIDTH: NATURAL
);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_data_width-1 downto 0)
cnt_o : out STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0)
);
end gc_counter;
......@@ -59,7 +59,7 @@ begin
main_proc: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_data_width-1 downto 0);
variable cnt_s : UNSIGNED(g_DATA_WIDTH - 1 downto 0);
begin
......
hdl/trigger/project/project.xise 0 → 100755
View file @ 7ee393fc
This diff is collapsed.
hdl/trigger/rtl/debouncer.vhd deleted 100755 → 0
View file @ 4bcd1c14
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:26:32 10/07/2011
-- Design Name: Basic debouncer
-- Module Name: debouncer - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debouncer is
generic (
g_LENGTH : INTEGER := 6
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(g_LENGTH-1 downto 0)
);
end debouncer;
architecture Behavioral of debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(g_LENGTH - 1 downto 0);
component gc_ff
port (
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
begin
ff1: gc_ff
port map(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
ff2: gc_ff
port map(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
-- Metastability solved here
delay_line: for i in 1 to g_LENGTH-1 generate
D_Flip_Flop : gc_ff
port map (
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output <= '0';
else
if ( (delay_s and glitch_mask) = glitch_mask) then
output <= '1';
else
output <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
hdl/trigger/rtl/gc_RAM.vhd deleted 100755 → 0
View file @ 4bcd1c14
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gc_RAM is
generic(
g_DATA_WIDTH : INTEGER := 32;
g_ADDR_WIDTH : INTEGER := 8;
g_ADDR_SIZE : INTEGER := 256
);
port(
clka : in STD_LOGIC;
wea : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
dina : in STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
doutb : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end gc_RAM;
architecture Behavioural of gc_RAM is
type ram_type is array(g_ADDR_SIZE - 1 downto 0) of STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
signal RAM: ram_type;
begin
write_proc: process (clka)
begin
if rising_edge(clka) then
if rstb = '1' then
erase_loop: for i in 0 to g_ADDR_SIZE - 1 loop
RAM(i) <= (others => '0');
end loop erase_loop;
else
RAM(conv_integer(addra)) <= dina;
end if;
else
end if;
end process;
read_proc: process (clkb)
begin
if rising_edge(clkb) then
if rstb = '1' then
doutb <= (others => '0');
elsif addrb = addra then
doutb <= dina;
else
doutb <= RAM(conv_integer(addrb));
end if;
else
end if;
end process;
end Behavioural;
hdl/trigger/rtl/gc_ff.vhd deleted 100755 → 0
View file @ 4bcd1c14
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:26:32 10/07/2011
-- Design Name: Basic debouncer
-- Module Name: debouncer - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_ff is
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end gc_ff;
architecture Behavioral of gc_ff is
begin
reg_proc: process(C)
begin
if rising_edge(C) then
if CLR = '1' then
Q <= '0';
else
Q <= D;
end if;
else
end if;
end process;
end Behavioral;
hdl/trigger/rtl/monostable.vhd deleted 100755 → 0
View file @ 4bcd1c14
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:00:11 10/12/2011
-- Design Name: Basic monostable
-- Module Name: monostable - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: A basic monostable circuit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity monostable is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(31 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end monostable;
architecture Behavioral of monostable is
type fsm is (S0_WAITING, S1_OK, S2_FORBIDDEN);
signal blo_pulse_fsm : fsm;
signal s_count_max : UNSIGNED (32 downto 0);
signal s_count_max2 : UNSIGNED (32 downto 0);
signal s_count : UNSIGNED (32 downto 0);
signal write_tt_s : STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
write_tt_o <= write_tt_s;
if (rst = '1') then
output <= '0';
write_tt_s <= '0';
blo_pulse_fsm <= S0_WAITING;
else
case blo_pulse_fsm is
when S0_WAITING =>
if input = '1' then
blo_pulse_fsm <= S1_OK;
s_count_max <= unsigned('0' & std_logic_vector(pulse_len));
s_count_max2 <= unsigned(std_logic_vector(pulse_len) & '0');
s_count(32 downto 1) <= (others => '0');
s_count(0) <= '1';
output <= '1';
write_tt_s <= '1';
else
end if;
when S1_OK =>
s_count <= s_count + 1;
write_tt_s <= '0';
if s_count = s_count_max then
blo_pulse_fsm <= S2_FORBIDDEN;
output <= '0';
else
end if;
when S2_FORBIDDEN =>
s_count <= s_count + 1;
if s_count = s_count_max2 then
blo_pulse_fsm <= S0_WAITING;
else
end if;
when others =>
end case;
end if;
else
end if;
end process;
end Behavioral;
hdl/trigger/rtl/trigger_core.vhd
View file @ 7ee393fc
This diff is collapsed.
hdl/trigger/rtl/trigger_pkg.vhd 0 → 100755
View file @ 7ee393fc
This diff is collapsed.
hdl/trigger/rtl/trigger_regs.vhd
View file @ 7ee393fc
This diff is collapsed.
hdl/trigger/rtl/trigger_top.vhd
View file @ 7ee393fc
......@@ -21,8 +21,11 @@
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.trigger_pkg.ALL;
entity trigger_top is
......@@ -35,7 +38,7 @@ entity trigger_top is
utc_i : in STD_LOGIC_VECTOR(95 downto 0);
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
......@@ -52,116 +55,42 @@ end trigger_top;
architecture Behavioral of trigger_top is
constant c_RAM_SIZE : UNSIGNED(15 downto 0) := X"0100";
constant c_MAX_GLITCH_STAGES : INTEGER := 6;
constant c_DEFAULT_GLITCH_MASK : UNSIGNED(c_MAX_GLITCH_STAGES-1 downto 0) := "000011";--(others => '1');
-- Let's assume that a 20MHz clock is used in wishbone
constant c_MIN_PULSE_LENGTH : INTEGER := 20;
constant c_MAX_PULSE_LENGTH : INTEGER := 40;
constant c_DEFAULT_PULSE_LENGTH : INTEGER := 30;
constant c_TAGS_DATA_WIDTH : INTEGER := 96;
signal STATUS_s : STD_LOGIC_VECTOR (31 downto 0);
signal CTR0_s : STD_LOGIC_VECTOR (31 downto 0);
signal CTR1_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM0_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM1_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM2_s : STD_LOGIC_VECTOR (31 downto 0);
signal write_tt_s : STD_LOGIC;
signal ramTT_s : STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH - 1 downto 0);
signal ramID_s : STD_LOGIC_VECTOR(31 downto 0);
component trigger_regs
generic(
g_MAX_GLITCH_STAGES : INTEGER := c_MAX_GLITCH_STAGES;
g_DEFAULT_GLITCH_MASK : UNSIGNED (c_MAX_GLITCH_STAGES - 1 downto 0) := c_DEFAULT_GLITCH_MASK;
g_MIN_PULSE_LENGTH : INTEGER := c_MIN_PULSE_LENGTH;
g_MAX_PULSE_LENGTH : INTEGER := c_MAX_PULSE_LENGTH;
g_DEFAULT_PULSE_LENGTH : INTEGER := c_DEFAULT_PULSE_LENGTH
);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
-- Terminating signals
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (2 downto 0);
STATUS_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM0_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_o : out STD_LOGIC_VECTOR (31 downto 0);
signal s_CTR0 : r_CTR0;
signal s_CTR1 : r_CTR1;
signal s_CTR2 : r_CTR2;
signal s_RAM0 : r_RAM0;
signal s_RAM1 : r_RAM1;
signal s_RAM2 : r_RAM2;
ramTT_i : in STD_LOGIC_VECTOR (95 downto 0);
ramID_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
signal write_tt_s : STD_LOGIC;
signal ramTT_s : STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH*8 - 1 downto 0);
signal ramID_s : STD_LOGIC_VECTOR(31 downto 0);
component trigger_core is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
begin
led_o : out STD_LOGIC;
core: trigger_core
port map(
pulse_i => pulse_i,
pulse_o => pulse_o,
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
led_o => led_o,
write_tt_o : out STD_LOGIC;
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
write_tt_o => write_tt_s,
component TT_RAMhandler is
generic (
g_TAGS_DATA_WIDTH : INTEGER := 96
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
CTR2_o => CTR2_s
);
port (
utc_i : in STD_LOGIC_VECTOR(g_TAGS_DATA_WIDTH - 1 downto 0);
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_i : in STD_LOGIC;
ramTT_o : out STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH - 1 downto 0);
ramID_o : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
registers: trigger_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_clk_i => wb_clk_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_ack_o => wb_ack_o,
......@@ -173,7 +102,6 @@ begin
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
STATUS_o => STATUS_s,
CTR0_o => CTR0_s,
CTR1_o => CTR1_s,
RAM0_o => RAM0_s,
......@@ -184,41 +112,5 @@ begin
ramID_i => ramID_s
);
core: trigger_core
port map(
pulse_i => pulse_i,
pulse_o => pulse_o,
led_o => led_o,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
write_tt_o => write_tt_s,
STATUS_i => STATUS_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
RAM0_i => RAM0_s,
RAM1_i => RAM1_s,
RAM2_i => RAM2_s
);
ram_handler: TT_RAMhandler
port map(
utc_i => utc_i,
STATUS_i => STATUS_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
RAM0_i => RAM0_s,
RAM1_o => RAM1_s,
RAM2_i => RAM2_s,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
write_tt_i => write_tt_s,
ramTT_o => ramTT_s,
ramID_o => ramID_s
);
end Behavioral;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment