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Conv TTL Blocking
Commit 8ab2fb99 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add firmware for SFP EEPROM test and input to reset module.

parent af840442
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Showing with 303 additions and 226 deletions
hdl/pts/rtl/pts_regs.vhd
View file @ 8ab2fb99
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Wed Apr 10 18:39:48 2013
-- Created : Mon Apr 15 10:57:27 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
......@@ -29,6 +29,8 @@ entity pts_regs is
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'current test' in reg: 'control register'
pts_ctrl_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'reset' in reg: 'control register'
pts_ctrl_rst_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID'
pts_id_bits_o : out std_logic_vector(31 downto 0)
);
......@@ -37,6 +39,7 @@ end pts_regs;
architecture syn of pts_regs is
signal pts_ctrl_crrt_test_int : std_logic_vector(3 downto 0);
signal pts_ctrl_rst_int : std_logic ;
signal pts_id_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
......@@ -66,7 +69,8 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_ctrl_crrt_test_int <= "0000";
pts_id_bits_int <= x"424c4f32";
pts_ctrl_rst_int <= '0';
pts_id_bits_int <= x"424C4F32";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -82,8 +86,10 @@ begin
when '0' =>
if (wb_we_i = '1') then
pts_ctrl_crrt_test_int <= wrdata_reg(3 downto 0);
pts_ctrl_rst_int <= wrdata_reg(31);
end if;
rddata_reg(3 downto 0) <= pts_ctrl_crrt_test_int;
rddata_reg(31) <= pts_ctrl_rst_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -111,7 +117,6 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
......@@ -136,6 +141,8 @@ begin
wb_dat_o <= rddata_reg;
-- current test
pts_ctrl_crrt_test_o <= pts_ctrl_crrt_test_int;
-- reset
pts_ctrl_rst_o <= pts_ctrl_rst_int;
-- bits
pts_id_bits_o <= pts_id_bits_int;
rwaddr_reg <= wb_adr_i;
......
hdl/pts/rtl/pts_regs.wb
View file @ 8ab2fb99
......@@ -15,6 +15,14 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "reset";
prefix = "rst";
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ 8ab2fb99
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365749981" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365750007" xil_pn:in_ck="-952039140557355708" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1365749981">
<transform xil_pn:end_ts="1366030730" xil_pn:in_ck="-952039140557355708" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366030704">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1365750007" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1365750007">
<transform xil_pn:end_ts="1366030730" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366030730">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1365750018" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1365750007">
<transform xil_pn:end_ts="1366030741" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366030730">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1365750119" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1365750018">
<transform xil_pn:end_ts="1366030831" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366030741">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1365750179" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1365750119">
<transform xil_pn:end_ts="1366030895" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366030831">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1365750206" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1365750179">
<transform xil_pn:end_ts="1366030923" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366030895">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1365750179" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1365750166">
<transform xil_pn:end_ts="1366030895" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366030883">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ 8ab2fb99
......@@ -346,25 +346,25 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../rtl/pts_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../rtl/clk_info_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -415,7 +415,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -430,7 +430,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -460,25 +460,25 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -535,16 +535,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -553,7 +553,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -595,7 +595,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -631,19 +631,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
</files>
......
hdl/pts/top/conv_ttl_blo_v2.ucf
View file @ 8ab2fb99
This diff is collapsed.
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ 8ab2fb99
This diff is collapsed.
hdl/reset_gen/rtl/reset_gen.vhd
View file @ 8ab2fb99
......@@ -54,6 +54,7 @@ entity reset_gen is
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end entity reset_gen;
......@@ -91,7 +92,10 @@ begin
p_rst_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (cnt_en = '1') then
if (rst_i = '1') then
cnt_en <= '1';
cnt <= (others => '0');
elsif (cnt_en = '1') then
rst_n_o <= '0';
cnt <= cnt + 1;
if (cnt = g_reset_time) then
......
hdl/reset_gen/sim/run.do
View file @ 8ab2fb99
......@@ -9,5 +9,5 @@ radix -hexadecimal
add wave *
# do wave.do
run 250 ms
run 250 us
wave zoomfull
hdl/reset_gen/sim/testbench.vhd
View file @ 8ab2fb99
......@@ -48,7 +48,7 @@ architecture behav of testbench is
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 20 ns;
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
......@@ -63,6 +63,7 @@ architecture behav of testbench is
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
......@@ -71,6 +72,7 @@ architecture behav of testbench is
-- Signal declarations
--============================================================================
signal clk, rst_n : std_logic := '0';
signal rst : std_logic := '0';
--==============================================================================
-- architecture begin
......@@ -81,11 +83,12 @@ begin
DUT: reset_gen
generic map
(
g_reset_time => 2500000
g_reset_time => 125
)
port map
(
clk_i => clk,
rst_i => rst,
rst_n_o => rst_n
);
......@@ -95,6 +98,21 @@ begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- RESET STIMULI
p_rst_ctrl: process is
begin
rst <= '0';
wait for 20 us;
rst <= '1';
wait for 15 us;
rst <= '0';
wait for 22 us;
rst <= '1';
wait for 12 us;
rst <= '0';
wait;
end process p_rst_ctrl;
end architecture behav;
--==============================================================================
......
hdl/reset_gen/sim/transcript
View file @ 8ab2fb99
# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-38-generic-pae
# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-40-generic-pae
# //
# // Copyright 1991-2011 Mentor Graphics Corporation
# // All Rights Reserved.
......@@ -9,6 +9,7 @@
# //
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
......@@ -23,9 +24,8 @@ do run.do
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# ** Error: testbench.vhd(89): near ";": expecting ',' or ')'
# ** Error: testbench.vhd(93): Statement cannot be labeled.
# ** Error: testbench.vhd(99): VHDL Compiler exiting
# ** Error: testbench.vhd(92): (vcom-1035) Formal port "rst_i" has OPEN or no actual associated with it.
# ** Error: testbench.vhd(116): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 4
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
......@@ -48,33 +48,6 @@ do run.do
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3812) Design is being optimized...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.reset_gen(behav)#1
# hexadecimal
# 0 ps
# 1050 ms
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity reset_gen
# -- Compiling architecture behav of reset_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
......@@ -84,7 +57,7 @@ do run.do
# Loading work.reset_gen(behav)#1
# hexadecimal
# 0 ps
# 1050 ms
# 262500 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -102,7 +75,6 @@ do run.do
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -111,7 +83,7 @@ do run.do
# Loading work.reset_gen(behav)#1
# hexadecimal
# 0 ps
# 262500 us
# 262500 ns
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -138,4 +110,4 @@ do run.do
# Loading work.reset_gen(behav)#1
# hexadecimal
# 0 ps
# 262500 us
# 262500 ns
hdl/reset_gen/syn/conv_ttl_blo_v2.gise
View file @ 8ab2fb99
......@@ -74,35 +74,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4270760611179553538" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4270760611179553538" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1722646998977239105" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1722646998977239105" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8095105047644196288" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8095105047644196288" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490825" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-8227463789215646005" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021469" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-8227463789215646005" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490836" xil_pn:in_ck="-7001770647288949855" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2562262252355265488" xil_pn:start_ts="1362490825">
<transform xil_pn:end_ts="1366021479" xil_pn:in_ck="-7001770647288949855" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2562262252355265488" xil_pn:start_ts="1366021469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -120,11 +120,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1362490836" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1847258329610505493" xil_pn:start_ts="1362490836">
<transform xil_pn:end_ts="1366021479" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1847258329610505493" xil_pn:start_ts="1366021479">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362490844" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-6129093030515200254" xil_pn:start_ts="1362490836">
<transform xil_pn:end_ts="1366021488" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-6129093030515200254" xil_pn:start_ts="1366021479">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -133,7 +133,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362490869" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1362490844">
<transform xil_pn:end_ts="1366021512" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366021488">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -146,7 +146,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1362490901" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1362490869">
<transform xil_pn:end_ts="1366021544" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366021512">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -160,7 +160,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362490921" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1362490901">
<transform xil_pn:end_ts="1366021564" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366021544">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -171,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1362490901" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1362490891">
<transform xil_pn:end_ts="1366021544" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366021534">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/reset_gen/top/conv_ttl_blo_v2.vhd
View file @ 8ab2fb99
......@@ -123,6 +123,7 @@ architecture Behavioral of conv_ttl_blo_v2 is
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
......@@ -170,6 +171,7 @@ begin
port map
(
clk_i => clk_125,
rst_i => '0',
rst_n_o => rst_n
);
......
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