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Commit 8ec83b57 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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I2C write seems to work fine, read is still a problem. Creating secondary branch… 

I2C write seems to work fine, read is still a problem. Creating secondary branch to fix bicolor LEDs and switching to it.
parent d80c5f82
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Showing with 1041 additions and 292 deletions
.gitignore 0 → 100644
View file @ 8ec83b57
captures/
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
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hdl/IMAGES/image1/project/image1.gise
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hdl/IMAGES/image1/project/image1.xise
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......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_regs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -469,7 +469,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_regs" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 8ec83b57
......@@ -265,7 +265,7 @@ begin
-- !!!!!
led_front_n <= leds_from_trig or (not trigleds);
led_front_n <= not trigleds;
......@@ -334,7 +334,7 @@ begin
scl_oen => i2c_slave_o.SCL_OE,
scl_i => i2c_slave_i.SCL_I,
scl_o => i2c_slave_o.SCL_O,
wb_clk => s_clk.SYS_A,
wb_clk_i => s_clk.SYS_A,
wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
wb_master_stb_o => s_slave_i(c_MASTER_I2C_SLAVE).stb,
wb_master_cyc_o => s_slave_i(c_MASTER_I2C_SLAVE).cyc,
......
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 8ec83b57
......@@ -170,7 +170,7 @@ package image1_pkg is
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
......@@ -205,7 +205,7 @@ package image1_pkg is
component m25p32_top
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
......@@ -237,7 +237,7 @@ package image1_pkg is
--! Set it up accordingly.
g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
port(wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 8ec83b57
......@@ -20,7 +20,7 @@ end image1_top_tb;
architecture behavior of image1_top_tb is
type t_tb_state is (ST_INIT, ST_READ_CTR0, ST_WRITE_LED);
type t_tb_state is (ST_INIT, ST_READ_CTR0, ST_WRITE_LED, ST_READ_LED);
constant c_CLK20M : TIME := 50 ns;
......@@ -324,17 +324,24 @@ begin
severity Error;
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
tb_state <= ST_WRITE_LED;
-- tb_state <= ST_WRITE_LED;
--
-- start_i2c;
-- assert false report "-------writing" severity note;
-- write_i2c(s_fpga_ga, x"0080", x"00000055");
-- assert false report "-------done!" severity note;
--
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
tb_state <= ST_READ_LED;
start_i2c;
assert false report "-------writing" severity note;
write_i2c(s_fpga_ga, x"0080", x"00000055");
assert false report "-------reading" severity note;
read_i2c(s_fpga_ga, x"0080");
assert false report "-------done!" severity note;
wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
--
-- start_I2C;
-- read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_DTX_addr);
-- assert False report "Reading I2C DTX" severity Warning;
......
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @ 8ec83b57
......@@ -2,10 +2,7 @@
1 OK READ WISHBONE HIGH
1 OK READ WISHBONE LOW
1 OK READ [ADDRESS|0]
2 OK WRITE [ADDRESS|0]
2 OK WRITE WISHBONE HIGH
2 OK WRITE WISHBONE LOW
2 OK WRITE READ DATA 0
2 OK WRITE READ DATA 1
2 OK WRITE READ DATA 2
2 OK WRITE READ DATA 3
2 OK READ [ADDRESS|0]
2 OK READ WISHBONE HIGH
2 OK READ WISHBONE LOW
2 OK READ [ADDRESS|0]
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 8ec83b57
......@@ -29,7 +29,7 @@ use IEEE.NUMERIC_STD.ALL;
use work.i2c_slave_pkg.ALL;
entity i2c_regs is
port (wb_clk : in STD_LOGIC;
port (wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
......@@ -117,10 +117,10 @@ begin
pf_wb_data_o <= s_DTX;
--! @brief Process that controls the retries of the wishbone interface
--! @param wb_clk Main clock
p_wb_master_retries: process (wb_clk)
--! @param wb_clk_i Main clock
p_wb_master_retries: process (wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if i2c_master_WB_BASIC_fsm = S3_WB_ACK then
s_wb_master_ack_retries(0) <= '1';
for i in 1 to c_RETRY_LENGTH - 1 loop
......@@ -139,21 +139,39 @@ begin
--! read/written when repetitions of the
--! wishbone master interface happen.
--! @param i2c_master_WB_BASIC_fsm fsm of the wishone master interface
wbmaster_comb_proc: process(i2c_master_WB_BASIC_fsm)
wbmaster_comb_proc : process(wb_clk_i)
-- function f_le2be(val : std_logic_vector(31 downto 0))
-- return std_logic_vector(31 downto 0) is
-- variable retval;
-- begin
-- retval( 7 downto 0) <= val(31 downto 24);
-- retval(15 downto 8) <= val(23 downto 16);
-- retval(23 downto 16) <= val(15 downto 8);
-- retval(31 downto 24) <= val(7 downto 0);
--
-- return retval;
-- end function;
begin
if rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
s_wb_master_we_o <= '0';
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0');
wb_master_addr_o <= (others => '0');
s_dtx <= (others => '0');
else
case i2c_master_WB_BASIC_fsm is
when R0_RESET =>
null;
when S0_IDLE =>
null;
when S1P_WB_RD_RQT =>
s_wb_addr_rd(15 downto 0) <= DRXA_i(23 downto 8);
s_wb_addr_rd <= DRXA_i(23 downto 8);
when S1_WB_RD_RQT =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
......@@ -173,29 +191,34 @@ begin
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= DRXA_i;
wb_master_addr_o(15 downto 0) <= DRXB_i(15 downto 0);
wb_master_data_o <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP =>
wb_master_cyc_o <= '1';
wb_master_stb_o <= '1';
s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F";
wb_master_data_o <= DRXA_i;
wb_master_addr_o(15 downto 0) <= DRXB_i(15 downto 0);
wb_master_data_o <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK =>
null;
-- null;
wb_master_cyc_o <= '0';
wb_master_stb_o <= '0';
s_wb_master_we_o <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
--! @brief Process to rule slave wishbone outputs
--! @param wb_clk Main clock
p_wb_slave: process (wb_clk)
--! @param wb_clk_i Main clock
p_wb_slave: process (wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if i2c_master_WB_BASIC_fsm = R0_RESET then
s_CTR0 <= c_CTR0_default;
s_CTR0.I2C_ADDR <= UNSIGNED(i2c_addr_i);
......@@ -246,10 +269,10 @@ begin
--! @brief This is the process that controls the wishbone master interface
--! which bridges the i2c interface with the wishbone interface.
--! @param wb_clk Main clock
p_master_fsm: process(wb_clk)
--! @param wb_clk_i Main clock
p_master_fsm: process(wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
--! Here is the part in which we propagate the reset, let one-clock
--! for it.
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 8ec83b57
......@@ -60,7 +60,7 @@ use work.ctdah_pkg.ALL;
entity i2c_slave_core is
generic(g_WB_CLK_PERIOD : TIME := 50 ns);
port (
clk : in STD_LOGIC;
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
-- I2C pins
sda_oen : out STD_LOGIC;
......@@ -170,15 +170,22 @@ signal s_watchdog_cnt_rst : STD_LOGIC;
signal s_watchdog_cnt_slv : STD_LOGIC_VECTOR(c_WATCHDOG_WIDTH - 1 downto 0);
signal s_watchdog_cnt : NATURAL;
attribute keep : string;
signal s_dummy : std_logic_vector(0 to 31);
attribute keep of s_dummy : signal is "true";
begin
s_dummy(0 to 31) <= f_ch_endian(s_pf_wb_data(31 downto 0));
s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i;
inst_i2c_bit : i2c_bit
port map(rst_i => rst_i,
wb_clk_i => clk,
wb_clk_i => clk_i,
sda_i => sda_i,
scl_i => scl_i,
start_o => s_start_o,
......@@ -189,7 +196,7 @@ begin
bit_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
port map (clk_i => clk,
port map (clk_i => clk_i,
rst_i => s_bit_cnt_rst,
en_i => s_bit_done,
cnt_o => s_bit_cnt_slv);
......@@ -198,7 +205,7 @@ begin
byte_counter_8: gc_counter
generic map (g_data_width => c_DATA_WIDTH)
port map (clk_i => clk,
port map (clk_i => clk_i,
rst_i => s_byte_cnt_rst,
en_i => s_byte_cnt_en,
cnt_o => s_byte_cnt_slv);
......@@ -207,7 +214,7 @@ begin
watchdog_counter_8: gc_counter
generic map (g_data_width => c_WATCHDOG_WIDTH)
port map (clk_i => clk,
port map (clk_i => clk_i,
rst_i => s_watchdog_cnt_rst,
en_i => c_WATCHDOG_ENABLE,
cnt_o => s_watchdog_cnt_slv);
......@@ -227,6 +234,8 @@ begin
-- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0);
variable v_pf_wb_data : STD_LOGIC_VECTOR(0 to 31);
-- variable v_pf_wb_data : std_logic_vector(31 downto 0);
begin
case i2c_SLA_fsm is
when S2A_I2C_ADDR_ACK =>
......@@ -241,7 +250,11 @@ begin
-- v_bit_inv := UNSIGNED(not(s_bit_cnt_slv(2 downto 0)));
-- v_bit_order := to_integer(v_bit_inv);
-- s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0);
v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0); -- f_ch_endian(s_pf_wb_data(31 downto 0));
-- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
when others =>
s_sda_o <= '1';
......@@ -273,8 +286,8 @@ begin
s_DRXB_slv <= s_DRX_slv(r_DRX'a_length*2 - 1 downto r_DRX'a_length);
--! @brief Process to store the incoming data
--! @param clk Clock that samples the data
p_store_FIFO: process(clk)
--! @param clk_i Clock that samples the data
p_store_FIFO: process(clk_i)
procedure shift_DRX is
begin
......@@ -285,7 +298,7 @@ begin
end procedure;
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
if s_bit_done = '1' then
case i2c_SLA_fsm is
when S2_I2C_ADDR =>
......@@ -317,19 +330,19 @@ begin
end generate gen_i2c;
p_delays : process(clk)
p_delays : process(clk_i)
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
i2c_SLA_fsm_d0 <= i2c_SLA_fsm;
end if;
end process;
--! @brief Process to generate the pf_wb_addr_o signal.
--! @param clk Main clock
p_pf_wb_addr: process(clk)
--! @param clk_i Main clock
p_pf_wb_addr: process(clk_i)
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
pf_wb_addr_o <= '0';
if i2c_SLA_fsm = S5W1A_I2C_ADDR_ACK
and i2c_SLA_fsm_d0 = S5W1_I2C_ADDR then
......@@ -339,10 +352,10 @@ begin
end process;
--! @brief Process to generate the rd_done_o signal.
--! @param clk Main clock
p_rd_done: process(clk)
--! @param clk_i Main clock
p_rd_done: process(clk_i)
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
rd_done_o <= '0';
if i2c_SLA_fsm = S6_WAIT_START_PAUSE
and i2c_SLA_fsm_d0 = S5RA_READ_SDA_ACK then
......@@ -352,10 +365,10 @@ begin
end process;
--! @brief Process to generate the wr_done_o signal.
--! @param clk Main clock
p_wr_done: process(clk)
--! @param clk_i Main clock
p_wr_done: process(clk_i)
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
wr_done_o <= '0';
if i2c_SLA_fsm = S6_WAIT_START_PAUSE
and i2c_SLA_fsm_d0 = S5W3_NACK then
......@@ -483,10 +496,10 @@ begin
end process;
--! @brief Watchdog reset process
--! @param clk Main clock
p_watchdog_rst: process(clk)
--! @param clk_i Main clock
p_watchdog_rst: process(clk_i)
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
s_watchdog_cnt_rst <= '0';
if rst_i = '1' then
s_watchdog_cnt_rst <= '1';
......@@ -503,11 +516,11 @@ begin
--! @brief Small process that records the length of a
--! bit over the I2C interface.
--! @param clk Main clock
p_LT_SCLP: process(clk)
--! @param clk_i Main clock
p_LT_SCLP: process(clk_i)
variable v_count : STD_LOGIC_VECTOR(23 downto 0);
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
if i2c_SLA_fsm = R0_RESET then
s_LT.SCLP <= c_LT_default.SCLP;
else
......@@ -523,8 +536,8 @@ begin
end process;
--! @brief Process to set the next fsm
--! @param clk Clock that rules the fsm transitions
fsm_proc: process(clk)
--! @param clk_i Clock that rules the fsm transitions
fsm_proc: process(clk_i)
procedure check_start_stop is
begin
......@@ -536,7 +549,7 @@ begin
end procedure;
begin
if rising_edge(clk) then
if rising_edge(clk_i) then
if rst_i = '1'
or s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
i2c_SLA_fsm <= R0_RESET;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 8ec83b57
......@@ -2,6 +2,7 @@
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
-- Theodor-Adrian Stana
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
......@@ -159,7 +160,7 @@ package i2c_slave_pkg is
component i2c_slave_core
generic(g_WB_CLK_PERIOD : TIME := 50 ns);
port (
clk : in STD_LOGIC;
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
......@@ -181,7 +182,7 @@ package i2c_slave_pkg is
end component;
component i2c_regs
port (wb_clk : in STD_LOGIC;
port (wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_we_o : out STD_LOGIC;
......@@ -243,6 +244,7 @@ package i2c_slave_pkg is
function f_LT (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_LT;
function f_ch_endian(val : std_logic_vector) return std_logic_vector;
function f_STD_LOGIC_VECTOR(r_register : in r_CTR0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : in r_LT) return STD_LOGIC_VECTOR;
......@@ -296,4 +298,15 @@ package body i2c_slave_pkg is
end function;
function f_ch_endian(val : std_logic_vector)
return std_logic_vector is
variable retval : std_logic_vector(31 downto 0);
begin
retval( 7 downto 0) := val(31 downto 24);
retval(15 downto 8) := val(23 downto 16);
retval(23 downto 16) := val(15 downto 8);
retval(31 downto 24) := val( 7 downto 0);
return retval;
end function;
end i2c_slave_pkg;
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 8ec83b57
......@@ -36,7 +36,7 @@ entity i2c_slave_top is
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_master_stb_o : out STD_LOGIC;
......@@ -95,7 +95,7 @@ begin
s_CTR0 <= f_CTR0(s_CTR0_slv);
inst_i2c_slave_core: i2c_slave_core
port map(clk => wb_clk,
port map(clk_i => wb_clk_i,
rst_i => wb_rst_i,
sda_oen => sda_oen,
......@@ -122,7 +122,7 @@ begin
wr_done_i => s_wr_done,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_clk_i => wb_clk_i,
wb_master_we_o => wb_master_we_o,
wb_master_stb_o => wb_master_stb_o,
......@@ -156,9 +156,9 @@ begin
s_rst_i2c <= s_reset_extensor(2**c_RST_EXTENSOR - 1);
--! A shift with reset, consumes just a few SLICEX in Spartan6.
p_rst_extender : process(wb_clk)
p_rst_extender : process(wb_clk_i)
begin
if rising_edge(wb_clk) then
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
s_reset_extensor <= (others => '1');
else
......
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