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Conv TTL Blocking
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Conv TTL Blocking
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913ef863
Commit
913ef863
authored
Nov 14, 2013
by
Theodor-Adrian Stana
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additions to second presentation file
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50bce627
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design-review/pres-2.txt
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913ef863
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@@ -2,6 +2,38 @@
1.1. Folder structure
conv-ttl-blo/
- conv-ttl-blo-gw/
-- doc/
--- hdlguide/
--- xil_multiboot/
--- <...>/
-- ip_cores/
--- general-cores/
-- modules/
--- ctb_pulse_gen/
--- glitch_filt/
--- reset_gen/
--- vbcp_wb/
--- xil_multiboot/
-- sim/
--- ctb_pulse_gen/
--- glitch_filt/
--- <...>/
-- syn/
--- release/
--- pulsetest/
--- regtest/
-- top/
--- release/
--- pulsetest/
--- regtest/
- doc/
-- userguide/
-- hwguide/
- pcb/
- software/
1.2. reset_gen
- reset bit already available, only needs to be connected
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@@ -15,20 +47,31 @@
- (eva) agreed with clearer `falling' and `rising' signal naming
- (eva) FSM seems clearer if the outputs are set in same process as
the states
- (javier) misalignment margin in i2c master?
1.4. vbcp_wb
- (eva, javier) will change signal names to reflect they are pulses
- (tom) i2c master informed about WB error by NACK
- watchdog addition (wait for 2.)
1.5. ctb_pulse_gen
- (javier) constant naming -- prefer `hardcoded' constants in code?
1.6. multiboot
- watchdog (wait for 2.)
- will retry the .wb
- no other additions?
1.7. bicolor_led_ctrl
1.8. rtm_detector
- (eva) rtmm signals can already be read in the register, think it's
a good idea to also have separate rtmm_ok signal in reg?
1.8. top-level
- (eva) making the top level only consist of instantiations would
complicate design
- (tom) suggest declaring constants instead of hard-coded constants?
1.9. constraints
- will add clock constraint to .ucf
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