Commit 9aabe050 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

DOC: Minor modifications to manual, to reflect register rename in memory map.…

DOC: Minor modifications to manual, to reflect register rename in memory map. Updated memory map register names
parent 0ed54253
......@@ -24,8 +24,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\noindent { \textit{Last modified by Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}\\
\noindent \rule{\textwidth}{.05cm}
......
......@@ -1060,18 +1060,18 @@ in the board status register (see Section~\ref{sec:diag-syserr}) and the
\label{sec:diag}
This section details the remote diagnostics features implemented via the logic
inside the FPGA on-board the CONV-TTL-BLO. Diagnostics data about a CONV-TTL-BLO
inside the FPGA on-board the CONV-TTL-BLO. Diagnostics data from a CONV-TTL-BLO
can be obtained via the I$^2$C interface detailed in Section~\ref{sec:comm}.
The following diagnostics features are implemented on the CONV-TTL-BLO:
\begin{itemize}
\item converter board identification
\item reading the unique board ID and temperature
\item reading of the FPGA gateware version
\item reading of the PCB hardware version
\item reading the state of the on-board switches
\item reading the state of the RTM detection lines
\item reading the unique board ID and on-board temperature
\item input pulse counters
\item input pulse time-tagging
\item remotely reset the FPGA logic
......@@ -1112,7 +1112,7 @@ the implementation of new blocks. The minor version increments on bug fixes.
%------------------------------------------------------------------------------
% SUBSEC: PCB version
%------------------------------------------------------------------------------
\subsection{PCB version}
\subsection{Hardware version}
\label{sec:diag-pcbvers}
The PCB version is necessary to the operation of the burst mode, see Section\ref{sec:pulse-rep-freq}.
Indeed the FPGA reads out the hardware version,
......@@ -1200,7 +1200,7 @@ Each channel is assigned two counters after the OR gate preceding
the pulse generator. The input counter logic, which is repeated on each channel,
is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a
TTL or a blocking input, the corresponding pulse counter is incremented and stored to one of the
two channel pulse counter registers (CHxTTLPCR or CHxBLOPCR -- see Appendix~\ref{app:conv-regs}). The CHxTTLPCR/CHxBLOPCR is a read-write register that can be written at any time via I$^2$C with a user-defined value.
two channel pulse counter registers (CHxFPPCR or CHxRPPCR -- see Appendix~\ref{app:conv-regs}). The CHxFPPCR/CHxRPPCR is a read-write register that can be written at any time via I$^2$C with a user-defined value.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
......@@ -1959,7 +1959,7 @@ $reg. index = \frac{addr}{4} + 1$
%%------------------------------------------------------------------------------
%% SUBSEC: conv_regs
%%------------------------------------------------------------------------------
\include{conv_regs}
\include{conv-regs}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
......
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