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Commit 9d60a8a1 authored by gilsoriano's avatar gilsoriano
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Testing of reads in m25p32. To work on spi_master_core for generating one-clock… 

Testing of reads in m25p32. To work on spi_master_core for generating one-clock signaling for refreshing of received data.
parent 26d6e6d1
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hdl/m25p32/project/waveform/wave.do
View file @ 9d60a8a1
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hdl/m25p32/rtl/m25p32_core.vhd
View file @ 9d60a8a1
......@@ -42,12 +42,11 @@ use work.m25p32_pkg.ALL;
use work.spi_master_pkg.ALL;
entity m25p32_core is
generic(g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_PAGE_SIZE : NATURAL := c_PAGE_SIZE;
g_READ_LENGTH : NATURAL := c_READ_LENGTH);
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
......@@ -58,13 +57,10 @@ entity m25p32_core is
ss_n_o : out STD_LOGIC;
wr_data_i : in STD_LOGIC_VECTOR(g_PAGE_SIZE*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR(r_SPI3'a_length - 1 downto 0);
SR_m25p32_i : in STD_LOGIC_VECTOR(r_SR_m25p32'a_length - 1 downto 0);
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
rd_SPI3_o : out STD_LOGIC;
OP_o : out STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
FMI_i : in STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
......@@ -91,27 +87,26 @@ signal s_MEM_fsm_d0 : t_m25p32_fsm;
signal s_OP : r_OP;
signal s_FMI : r_FMI;
signal s_wr_data_i : r_page;
--! Registers from spi_master_pkg
signal s_SPI0 : r_SPI0;
signal s_SPI0_d0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : r_SPI1;
signal s_SPI1_d0 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR (15 downto 0);
signal s_SPI3 : r_SPI3;
signal s_SPI3_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI0_slv : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
signal s_SPI1_slv : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
signal s_SPI2_slv : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_SPI3_slv : STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
signal s_rd_SPI3 : STD_LOGIC;
signal s_inst_spi : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
signal s_addr_spi : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
signal s_data_i_spi : STD_LOGIC_VECTOR (8*g_PAGE_SIZE - 1 downto 0);
signal s_data_i_spi : STD_LOGIC_VECTOR (8*g_PAGE_SIZE - 1 downto 0);
signal s_inst_spi_d0 : STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
signal s_addr_spi_d0 : STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
signal s_data_i_spi_d0 : STD_LOGIC_VECTOR (8*g_PAGE_SIZE - 1 downto 0);
signal s_data_i_spi_d0 : STD_LOGIC_VECTOR (8*g_PAGE_SIZE - 1 downto 0);
begin
......@@ -122,21 +117,15 @@ begin
s_SPI0_slv <= f_STD_LOGIC_VECTOR(s_SPI0);
s_SPI1_slv <= f_STD_LOGIC_VECTOR(s_SPI1);
s_SPI2 <= f_SPI2(s_SPI2_slv);
s_SPI3 <= f_SPI3(s_SPI3_slv);
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
SPI2_o <= s_SPI2;
SPI3_o <= s_SPI3;
s_wr_data_i <= f_page(wr_data_i);
rd_data_o <= s_SPI3_slv;
rd_SPI3_o <= s_rd_SPI3;
inst_spi_master_core: spi_master_core
generic map(
g_inst_length => c_INST_LENGTH,
g_addr_length => c_ADDR_LENGTH,
g_data_length => c_PAGE_SIZE,
g_read_length => c_READ_LENGTH
g_clk_i_period => c_CLK_I_PERIOD
) port map(
rst_i => wb_rst_i,
clk_i => wb_clk,
......@@ -145,11 +134,12 @@ begin
addr_i => s_addr_spi,
data_i => s_data_i_spi,
data_o => rd_data_o,
SPI0_i => s_SPI0_slv,
SPI1_i => s_SPI1_slv,
SPI2_o => s_SPI2_slv,
SPI3_o => s_SPI3_slv,
rd_SPI3_o => s_rd_SPI3,
spi_mosi_o => mosi_o,
spi_miso_i => miso_i,
......
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ 9d60a8a1
......@@ -39,8 +39,6 @@
----------------------------------------------------------------------------------
library IEEE;
library work;
......@@ -474,7 +472,6 @@ package m25p32_pkg is
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
rst_i : in STD_LOGIC;
......@@ -484,12 +481,12 @@ package m25p32_pkg is
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (8*g_READ_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (31 downto 0);
rd_SPI3_o : out STD_LOGIC;
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
......
hdl/m25p32/rtl/m25p32_regs.vhd
View file @ 9d60a8a1
......@@ -68,6 +68,8 @@ entity m25p32_regs is
rd_data_i : in STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0);
SR_m25p32_o : out STD_LOGIC_VECTOR (r_SR_m25p32'a_length - 1 downto 0);
rd_SPI3_i : in STD_LOGIC;
OP_i : in STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
FMI_o : out STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
);
......@@ -89,6 +91,8 @@ architecture Behavioral of m25p32_regs is
signal s_wb_rty_o : STD_LOGIC;
signal s_wb_err_o : STD_LOGIC;
signal s_rd_data : STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
begin
wb_ack_o <= s_wb_ack_o;
......@@ -114,11 +118,15 @@ begin
s_wb_ack_o <= '0';
s_wb_rty_o <= '0';
s_wb_err_o <= '0';
s_rd_data <= (others => '0');
else
--! We never retry
s_wb_rty_o <= '0';
if rd_SPI3_i = '1' then
s_rd_data <= rd_data_i;
end if;
if (wb_stb_i = '1' and wb_cyc_i = '1') then
if (s_wb_ack_o or s_wb_rty_o or s_wb_err_o) = '1' then
s_wb_ack_o <= '0';
......@@ -170,7 +178,7 @@ begin
wb_data_o(31 downto r_SR_m25p32'a_length)
<= (others => '0');
when "10" =>
wb_data_o <= rd_data_i;
wb_data_o <= s_rd_data;
when others =>
s_wb_ack_o <= '0';
s_wb_err_o <= '1';
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ 9d60a8a1
......@@ -58,11 +58,7 @@ entity m25p32_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
miso_word_rcv : out STD_LOGIC;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
......@@ -81,18 +77,14 @@ architecture Behavioral of m25p32_top is
signal s_OP : STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
signal s_FMI : STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0);
signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_SPI2 : r_SPI2;
signal s_SPI3 : r_SPI3;
signal s_rd_SPI3 : STD_LOGIC;
component m25p32_core is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_PAGE_SIZE : NATURAL := c_PAGE_SIZE;
g_READ_LENGTH : NATURAL := c_READ_LENGTH);
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
......@@ -103,15 +95,10 @@ architecture Behavioral of m25p32_top is
ss_n_o : out STD_LOGIC;
wr_data_i : in STD_LOGIC_VECTOR (g_PAGE_SIZE*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0);
rd_data_o : out STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
SR_m25p32_i : in STD_LOGIC_VECTOR (r_SR_m25p32'a_length - 1 downto 0);
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
rd_SPI3_o : out STD_LOGIC;
OP_o : out STD_LOGIC_VECTOR (r_OP'a_length - 1 downto 0);
FMI_i : in STD_LOGIC_VECTOR (r_FMI'a_length - 1 downto 0)
......@@ -140,6 +127,8 @@ architecture Behavioral of m25p32_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
rd_SPI3_i : in STD_LOGIC;
wr_data_o : out STD_LOGIC_VECTOR (g_DATA_LENGTH*8 - 1 downto 0);
rd_data_i : in STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0);
......@@ -154,11 +143,6 @@ begin
op_finished_o <= f_OP(s_OP).OPF;
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
SPI2_o <= s_SPI2;
SPI3_o <= s_SPI3;
inst_m25p32_core: m25p32_core
port map (
wb_rst_i => wb_rst_i,
......@@ -173,10 +157,8 @@ begin
rd_data_o => s_rd_data,
SR_m25p32_i => s_SR_m25p32,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
rd_SPI3_o => s_rd_SPI3,
OP_o => s_OP,
FMI_i => s_FMI
);
......@@ -197,6 +179,8 @@ begin
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
rd_SPI3_i => s_rd_SPI3,
wr_data_o => s_wr_data,
rd_data_i => s_rd_data,
SR_m25p32_o => s_SR_m25p32,
......
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ 9d60a8a1
......@@ -20,6 +20,10 @@
library IEEE;
library work;
library modelsim_lib;
use modelsim_lib.util.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
......@@ -35,7 +39,6 @@ architecture Behavioral of m25p32_top_tb is
file s_file_handler : TEXT;
constant c_log_path : STRING := "../test/log/m25p32_top_tb.log";
-- constant c_log_path : STRING := "/home/carlos/log/m25p32_top_tb.log";
constant sep : CHARACTER := ht;
signal wb_rst_i : STD_LOGIC;
......@@ -55,33 +58,46 @@ architecture Behavioral of m25p32_top_tb is
signal s_wb_err : STD_LOGIC;
signal s_spi_mosi : STD_LOGIC;
signal s_spi_miso : STD_LOGIC := '0';
signal s_spi_clk : STD_LOGIC;
signal s_spi_cs_n : STD_LOGIC;
signal s_FMI : r_FMI;
signal s_SR_m25p32 : r_SR_m25p32;
signal s_SR_m25p32_rd : r_SR_m25p32;
signal s_STATUS : r_STATUS;
--! Signals for the spi_analyser
signal s_SPI0 : r_SPI0;
signal s_SPI0_slv : STD_LOGIC_VECTOR(31 downto 0);
signal s_SPI0_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : r_SPI1;
signal s_SPI1_slv : STD_LOGIC_VECTOR(31 downto 0);
signal s_SPI1_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : r_SPI2;
signal s_SPI2_slv : STD_LOGIC_VECTOR(15 downto 0);
signal s_SPI2_slv : STD_LOGIC_VECTOR (15 downto 0);
signal s_SPI3 : r_SPI3;
signal s_SPI3_slv : STD_LOGIC_VECTOR (31 downto 0);
signal s_inst_check : STD_LOGIC_VECTOR (c_INST_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (c_ADDR_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_data_check : STD_LOGIC_VECTOR (c_DATA_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_inst_check : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal s_data_check : STD_LOGIC_VECTOR (2047 downto 0) := (others => '0');
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_data_flag : STD_LOGIC;
signal s_page : r_page;
--! Signals for the spi_slave_writer
signal s_rst_spi_slave_writer : STD_LOGIC;
signal s_bytes_to_wr : NATURAL := 0;
signal s_read : STD_LOGIC_VECTOR (c_READ_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_end_read_flag : STD_LOGIC;
signal s_spi_miso : STD_LOGIC;
signal s_SPI3 : r_SPI3;
signal s_page : r_page;
signal s_op_finished : STD_LOGIC;
......@@ -90,8 +106,28 @@ architecture Behavioral of m25p32_top_tb is
signal test_id : NATURAL := 0;
begin
s_SPI0 <= f_SPI0(s_SPI0_slv);
s_SPI1 <= f_SPI1(s_SPI1_slv);
s_SPI2 <= f_SPI2(s_SPI2_slv);
s_SPI3 <= f_SPI3(s_SPI3_slv);
--! @brief Process to bypass internal signals requiered for correct
--! use of spi_analyser
p_sig_spy : process is
begin
init_signal_spy("/uut/inst_m25p32_core/inst_spi_master_core/SPI0_i",
"s_SPI0_slv", 1);
init_signal_spy("/uut/inst_m25p32_core/inst_spi_master_core/SPI1_i",
"s_SPI1_slv", 1);
init_signal_spy("/uut/inst_m25p32_core/inst_spi_master_core/SPI2_o",
"s_SPI2_slv", 1);
init_signal_spy("/uut/inst_m25p32_core/inst_spi_master_core/SPI3_o",
"s_SPI3_slv", 1);
init_signal_spy("/uut/inst_m25p32_core/inst_spi_master_core/s_STATUS",
"s_STATUS", 1);
wait;
end process p_sig_spy;
--! Connections for the m25p32
uut: m25p32_top port map(
wb_rst_i => wb_rst_i,
......@@ -109,11 +145,6 @@ begin
wb_rty_o => s_wb_rty,
wb_err_o => s_wb_err,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
op_finished_o => s_op_finished,
prom_mosi_o => s_spi_mosi,
......@@ -127,7 +158,8 @@ begin
or s_SPI1.SEND_OP
or s_SPI2.SENT_OP;
tester : spi_analyser port map(
mosi_tester : spi_analyser port map(
rst_i => s_rst_spi_analyser,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
......@@ -145,6 +177,24 @@ begin
end_addr_flag_o => s_end_addr_flag,
end_data_flag_o => s_end_data_flag);
s_rst_spi_slave_writer <= wb_rst_i
or s_op_finished
or s_SPI1.SEND_OP
or s_SPI2.SENT_OP;
miso_tester : spi_slave_writer port map(
rst_i => s_rst_spi_slave_writer,
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
STATUS_i => s_STATUS,
bytes_to_wr_i => s_bytes_to_wr,
read_i => s_read,
end_read_flag_o => s_end_read_flag,
spi_miso_o => s_spi_miso,
spi_clk_i => s_spi_clk);
--! @brief Process that generates the wb_clk
clk_i_process : process
......@@ -170,8 +220,6 @@ begin
s_wb_sel <= (others => '0');
s_wb_data_i <= (others => '0');
s_wb_addr <= (others => '0');
--! And also the miso line
s_spi_miso <= '0';
end procedure;
procedure wishbone_write_SR (reg_data : r_SR_m25p32) is
......@@ -590,8 +638,6 @@ begin
wait_until_completion(trigger);
end procedure;
begin
file_open(s_file_handler, c_log_path, WRITE_MODE);
......@@ -648,6 +694,10 @@ begin
--! [3] Testing BE
check_and_wait(BE, 0, 0, s_op_finished);
--! [4] Testing RDRSR
s_read <= fill_read;
check_and_wait(RDSR, 0, 0, s_op_finished);
assert false report "No error. Simulation ends." severity failure;
end process p_simulation;
......
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
View file @ 9d60a8a1
......@@ -56,13 +56,6 @@ package m25p32_top_tb_pkg is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
--! These lines are offer in top after vpp (VHDL preprocessor) is
--! run with SIMULATION label on.
SPI0_o : out r_SPI0;
SPI1_o : out r_SPI1;
SPI2_o : out r_SPI2;
SPI3_o : out r_SPI3;
op_finished_o : out STD_LOGIC;
prom_mosi_o : out STD_LOGIC;
......@@ -97,13 +90,24 @@ package m25p32_top_tb_pkg is
signal read_data : out STD_LOGIC_VECTOR (31 downto 0);
reg_addr : STD_LOGIC_VECTOR (c_WORDS_PER_PAGE_BITS
downto 0));
function fill_page return r_page;
function fill_read return STD_LOGIC_VECTOR;
end m25p32_top_tb_pkg;
package body m25p32_top_tb_pkg is
--! @brief Procedure to place wishbone writes at a given address.
--! @param wb_clk Wishbone clock signal
--! wb_we Write enable signal
--! wb_stb Strobe signal
--! wb_cyc Cycle signal
--! wb_sel Addres select signal
--! wb_data Data signal to be read from
--! wb_addr Address signal to read from
--! reg_data Data to write into wishbone bus
--! reg_addr Address to read from
procedure wishbone_write (
signal wb_clk : in STD_LOGIC;
signal wb_we : out STD_LOGIC;
......@@ -133,6 +137,16 @@ package body m25p32_top_tb_pkg is
wb_sel <= X"F";
end procedure;
--! @brief Procedure to place wishbone reads at a given address.
--! @param wb_clk Wishbone clock signal
--! wb_we Write enable signal
--! wb_stb Strobe signal
--! wb_cyc Cycle signal
--! wb_sel Addres select signal
--! wb_data Data signal to be read from
--! wb_addr Address signal to read from
--! read_data Signal where to place the read data from wb
--! reg_addr Address to read from
procedure wishbone_read (
signal wb_clk : in STD_LOGIC;
signal wb_we : out STD_LOGIC;
......@@ -161,6 +175,8 @@ package body m25p32_top_tb_pkg is
wb_sel <= X"F";
end procedure;
--! @brief Funtion to fill a page with predefined words.
function fill_page return r_page is
variable v_var0 : r_word := (word_slv => X"DEADBEEF");
variable v_var1 : r_word := (word_slv => X"8BADF00D");
......@@ -183,4 +199,11 @@ package body m25p32_top_tb_pkg is
return v_return;
end function fill_page;
function fill_read return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(c_READ_LENGTH*8 - 1 downto 0);
begin
v_return := X"600D700D";
return v_return;
end function fill_read;
end m25p32_top_tb_pkg;
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ 9d60a8a1
......@@ -46,10 +46,9 @@ use work.ctdah_pkg.ALL;
entity spi_master_core is
generic(
g_INST_LENGTH : NATURAL := 1;
g_ADDR_LENGTH : NATURAL := 3;
g_DATA_LENGTH : NATURAL := 256;
g_READ_LENGTH : NATURAL := 4;
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
rst_i : in STD_LOGIC;
......@@ -59,12 +58,12 @@ entity spi_master_core is
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (8*g_READ_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (31 downto 0);
rd_SPI3_o : out STD_LOGIC;
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
......@@ -82,7 +81,6 @@ signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_SPI2 : r_SPI2;
signal s_SPI2_d0 : r_SPI2;
signal s_SPI3 : r_SPI3;
signal s_PUSH_INST_tmp : STD_LOGIC;
signal s_PUSH_ADDR_tmp : STD_LOGIC;
......@@ -94,33 +92,33 @@ signal s_SPI1_core : r_SPI1;
signal s_SPI1_core_d0 : r_SPI1;
type SPI_clk_fsm is(R0_RESET,
S0_IDLE,
S1_SETUP,
S2_SPI_ACTIVITY,
S3_HOLD);
type SPI_spi_clk_fsm is (S0_IDLE,
S1_START_SPI_CLK,
S2P_INST,
S2_INST,
S3P_ADDR,
S3_ADDR,
S4P_DATA,
S4_DATA,
S5_READ,
S5U_READ,
S6_STOP_SPI_CLK,
Q0_END);
type r_STATUS is
record
clk_fsm : SPI_clk_fsm;
spi_clk_fsm : SPI_spi_clk_fsm;
PULL_INST : STD_LOGIC;
PULL_ADDR : STD_LOGIC;
PULL_DATA : STD_LOGIC;
end record;
--type SPI_clk_fsm is(R0_RESET,
-- S0_IDLE,
-- S1_SETUP,
-- S2_SPI_ACTIVITY,
-- S3_HOLD);
--
--type SPI_spi_clk_fsm is (S0_IDLE,
-- S1_START_SPI_CLK,
-- S2P_INST,
-- S2_INST,
-- S3P_ADDR,
-- S3_ADDR,
-- S4P_DATA,
-- S4_DATA,
-- S5_READ,
-- S5U_READ,
-- S6_STOP_SPI_CLK,
-- Q0_END);
--
--type r_STATUS is
-- record
-- clk_fsm : SPI_clk_fsm;
-- spi_clk_fsm : SPI_spi_clk_fsm;
-- PULL_INST : STD_LOGIC;
-- PULL_ADDR : STD_LOGIC;
-- PULL_DATA : STD_LOGIC;
-- end record;
signal s_STATUS : r_STATUS;
......@@ -133,8 +131,8 @@ constant c_STATUS_DEFAULT : r_STATUS := (clk_fsm => S0_IDLE,
signal s_spi_clk_fsm_d0 : SPI_spi_clk_fsm;
signal s_clk_fsm_d0 : SPI_clk_fsm;
constant c_CS_SU_TICKS : NATURAL := c_CS_SU_SPI/c_CLK_I_PERIOD + 1;
constant c_CS_HOLD_TICKS : NATURAL := c_CS_HOLD_SPI/c_CLK_I_PERIOD + 1;
constant c_CS_SU_TICKS : NATURAL := c_CS_SU_SPI/g_CLK_I_PERIOD + 1;
constant c_CS_HOLD_TICKS : NATURAL := c_CS_HOLD_SPI/g_CLK_I_PERIOD + 1;
signal s_cs_su_count : NATURAL;
signal s_cs_hold_count : NATURAL;
......@@ -144,7 +142,6 @@ signal s_timing_counter_manual_rst_i : STD_LOGIC;
signal s_timing_counter_rst_i : STD_LOGIC;
signal s_timing_counter_cnt : STD_LOGIC_VECTOR(c_COUNTER_DATA_WIDTH
- 1 downto 0);
signal s_write_edge_clk : STD_LOGIC;
signal s_read_edge_counter_clk : STD_LOGIC;
signal s_read_edge_counter_en : STD_LOGIC;
signal s_read_edge_counter_manual_rst_clk : STD_LOGIC;
......@@ -170,12 +167,10 @@ signal s_spi_miso_data : STD_LOGIC_VECTOR(31 downto 0);
begin
data_o <= s_spi_miso_data;
s_SPI0 <= f_SPI0(SPI0_i);
s_SPI1 <= f_SPI1(SPI1_i);
SPI2_o <= f_STD_LOGIC_VECTOR(s_SPI2);
SPI3_o <= f_STD_LOGIC_VECTOR(s_SPI3);
SPI3_o <= s_spi_miso_data;
spi_clk_o <= s_spi_clk_d0 when s_SPI0.CPOL = '0'
else s_spi_clk_n_d0;
......@@ -275,8 +270,6 @@ begin
-----------------------------------------------------------
--! Counter for spi read edges
-----------------------------------------------------------
s_write_edge_clk <= s_spi_clk_d0 when s_SPI0.CPHA = '1'
else s_spi_clk_n_d0;
s_read_edge_counter_clk <= s_spi_clk_d0 when s_SPI0.CPHA = '0'
else s_spi_clk_n_d0;
s_read_edge_counter_rst_i <= s_read_edge_counter_manual_rst_clk
......@@ -391,6 +384,10 @@ begin
s_SPI1_core.y <= c_SPI1_default.y;
s_SPI1_core.CLK_DIV <= c_SPI1_default.CLK_DIV;
s_SPI1_core.z <= c_SPI1_default.z;
s_PUSH_INST_tmp <= c_SPI1_default.PUSH_INST;
s_PUSH_ADDR_tmp <= c_SPI1_default.PUSH_ADDR;
s_PUSH_DATA_tmp <= c_SPI1_default.PUSH_DATA;
else
s_SPI1_core.x <= s_SPI1_core_d0.x;
s_SPI1_core.READ_MISO <= s_SPI1_core_d0.READ_MISO;
......@@ -800,17 +797,36 @@ begin
begin
if rising_edge(s_read_edge_counter_clk) then
if s_STATUS.clk_fsm = R0_RESET then
s_spi_miso_data <= (others => '0');
s_spi_miso_data <= (others => '0');
else
s_spi_miso_data <= (others => '0');
if s_STATUS.spi_clk_fsm = S5_READ then
if s_spi_clk_fsm_d0 = S5_READ then
s_spi_miso_data <= s_spi_miso_data(30 downto 0)
& spi_miso_i;
end if;
end if;
end if;
end process p_miso;
p_rd_miso : process(clk_i)
begin
if rising_edge(clk_i) then
if s_STATUS.clk_fsm = R0_RESET then
s_rd_SPI3 <= '0';
else
s_rd_SPI3 <= '0';
--!TODO: change to one-clock signaling!
if ((UNSIGNED(s_read_edge_counter_cnt) mod r_SPI3'a_length) = 0)
or s_SPI2.SENT_OP = '1' then
if s_rd_SPI3 = '0' then
s_rd_SPI3 <= '1';
end if;
end if;
end if;
end if;
end process p_rd_miso;
-----------------------------------------------------------
--! fsm to determine access to SPI lines
......
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ 9d60a8a1
......@@ -157,6 +157,37 @@ package spi_master_pkg is
attribute a_length of r_SPI3 : type is 32;
type SPI_clk_fsm is(R0_RESET,
S0_IDLE,
S1_SETUP,
S2_SPI_ACTIVITY,
S3_HOLD);
type SPI_spi_clk_fsm is (S0_IDLE,
S1_START_SPI_CLK,
S2P_INST,
S2_INST,
S3P_ADDR,
S3_ADDR,
S4P_DATA,
S4_DATA,
S5_READ,
S5U_READ,
S6_STOP_SPI_CLK,
Q0_END);
type r_STATUS is
record
clk_fsm : SPI_clk_fsm;
spi_clk_fsm : SPI_spi_clk_fsm;
PULL_INST : STD_LOGIC;
PULL_ADDR : STD_LOGIC;
PULL_DATA : STD_LOGIC;
end record;
constant c_INST_LENGTH : NATURAL := 1;
constant c_ADDR_LENGTH : NATURAL := 3;
constant c_DATA_LENGTH : NATURAL := 256;
......
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @ 9d60a8a1
......@@ -58,17 +58,19 @@ entity spi_master_regs is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (15 downto 0)
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_i : in STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
);
end spi_master_regs;
architecture Behavioral of spi_master_regs is
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (15 downto 0);
signal s_SPI0 : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
......@@ -122,8 +124,11 @@ begin
when c_SPI2_addr =>
wb_data_o(15 downto 0) <= s_SPI2;
wb_data_o(31 downto 16) <= (others => '0');
s_wb_ack <= '1';
when others =>
s_wb_ack <= '1';
when c_SPI3_addr =>
wb_data_o <= SPI3_i;
s_wb_ack <= '1';
when others =>
end case;
end case;
end if;
......
hdl/spi_master_multifield/rtl/spi_master_top.vhd
View file @ 9d60a8a1
......@@ -44,7 +44,12 @@ use work.spi_master_pkg.ALL;
entity spi_master_top is
port(
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
......@@ -59,9 +64,9 @@ entity spi_master_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0);
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
......@@ -87,9 +92,10 @@ architecture Behavioral of spi_master_top is
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
......@@ -114,16 +120,18 @@ architecture Behavioral of spi_master_top is
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (15 downto 0)
SPI0_o : out STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_i : in STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0)
);
end component;
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (15 downto 0);
signal s_SPI0 : STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
signal s_SPI3 : STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
begin
......@@ -138,6 +146,7 @@ begin
SPI0_i => s_SPI0,
SPI1_i => s_SPI1,
SPI2_o => s_SPI2,
SPI3_o => s_SPI3,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
......@@ -163,7 +172,8 @@ begin
SPI0_o => s_SPI0,
SPI1_o => s_SPI1,
SPI2_i => s_SPI2
SPI2_i => s_SPI2,
SPI3_i => s_SPI3,
);
end Behavioral;
......
hdl/spi_master_multifield/test/spi_analyser.vhd
View file @ 9d60a8a1
......@@ -33,6 +33,11 @@ use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;
entity spi_analyser is
generic(
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port( rst_i : in STD_LOGIC;
SPI0_i : in r_SPI0;
SPI1_i : in r_SPI1;
......@@ -42,9 +47,9 @@ entity spi_analyser is
spi_clk_o : in STD_LOGIC;
spi_cs_n_o : in STD_LOGIC;
inst_check_o : out STD_LOGIC_VECTOR (7 downto 0);
addr_check_o : out STD_LOGIC_VECTOR (23 downto 0);
data_check_o : out STD_LOGIC_VECTOR (2047 downto 0);
inst_check_o : out STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0);
addr_check_o : out STD_LOGIC_VECTOR (g_ADDR_LENGTH*8 - 1 downto 0);
data_check_o : out STD_LOGIC_VECTOR (g_DATA_LENGTH*8 - 1 downto 0);
end_inst_flag_o : out STD_LOGIC;
end_addr_flag_o : out STD_LOGIC;
......@@ -63,18 +68,19 @@ architecture Behavioral of spi_analyser is
signal s_spi_mosi : STD_LOGIC;
signal s_spi_clk : STD_LOGIC;
signal s_inst_check : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal s_data_check : STD_LOGIC_VECTOR (2047 downto 0) := (others => '0');
signal s_inst_check : STD_LOGIC_VECTOR (g_INST_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_addr_check : STD_LOGIC_VECTOR (g_ADDR_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_data_check : STD_LOGIC_VECTOR (g_DATA_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_end_inst_flag : STD_LOGIC;
signal s_end_addr_flag : STD_LOGIC;
signal s_end_data_flag : STD_LOGIC;
begin
s_spi_mosi <= spi_mosi_o;
s_spi_clk <= spi_clk_o;
......
hdl/spi_master_multifield/test/spi_analyser_pkg.vhd
View file @ 9d60a8a1
......@@ -54,6 +54,26 @@ package spi_analyser_pkg is
);
end component;
component spi_slave_writer
generic(
g_READ_LENGTH : NATURAL := c_READ_LENGTH);
port( rst_i : in STD_LOGIC;
SPI0_i : in r_SPI0;
SPI1_i : in r_SPI1;
STATUS_i : in r_STATUS;
bytes_to_wr_i : in NATURAL;
read_i : in STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
end_read_flag_o : out STD_LOGIC;
spi_miso_o : out STD_LOGIC;
spi_clk_i : in STD_LOGIC
);
end component;
-- Clock period definitions
constant c_WISHBONE_PERIOD : TIME := 10 ns;
......
hdl/spi_master_multifield/test/spi_master_core_tb.vhd
View file @ 9d60a8a1
......@@ -43,7 +43,6 @@ architecture Behavioral of spi_master_core_tb is
g_INST_LENGTH : NATURAL := c_INST_LENGTH;
g_ADDR_LENGTH : NATURAL := c_ADDR_LENGTH;
g_DATA_LENGTH : NATURAL := c_DATA_LENGTH;
g_READ_LENGTH : NATURAL := c_READ_LENGTH;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
rst_i : in STD_LOGIC;
......@@ -53,13 +52,13 @@ architecture Behavioral of spi_master_core_tb is
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
data_o : out STD_LOGIC_VECTOR (8*g_READ_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (r_SPI0'a_length - 1 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (r_SPI1'a_length - 1 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (r_SPI2'a_length - 1 downto 0);
SPI3_o : out STD_LOGIC_VECTOR (r_SPI3'a_length - 1 downto 0);
rd_SPI3_o : out STD_LOGIC;
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
......@@ -75,7 +74,6 @@ architecture Behavioral of spi_master_core_tb is
signal s_inst : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0) := (others => '0');
signal s_addr : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0) := (others => '0');
signal s_data : STD_LOGIC_VECTOR (8*c_DATA_LENGTH - 1 downto 0) := (others => '0');
signal data_o : STD_LOGIC_VECTOR (8*c_READ_LENGTH - 1 downto 0);
signal inst_i : STD_LOGIC_VECTOR (8*c_INST_LENGTH - 1 downto 0) := (others => '0');
signal addr_i : STD_LOGIC_VECTOR (8*c_ADDR_LENGTH - 1 downto 0) := (others => '0');
......@@ -134,6 +132,7 @@ begin
SPI0_i => s_SPI0_slv,
SPI1_i => s_SPI1_slv,
SPI2_o => s_SPI2_slv,
SPI3_o => s_SPI3_slv,
spi_mosi_o => s_spi_mosi,
spi_miso_i => s_spi_miso,
spi_clk_o => s_spi_clk,
......
hdl/spi_master_multifield/test/spi_slave_writer.vhd 0 → 100755
View file @ 9d60a8a1
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.spi_master_pkg.ALL;
entity spi_slave_writer is
generic(
g_READ_LENGTH : NATURAL := c_READ_LENGTH);
port( rst_i : in STD_LOGIC;
SPI0_i : in r_SPI0;
SPI1_i : in r_SPI1;
STATUS_i : in r_STATUS;
bytes_to_wr_i : in NATURAL;
read_i : in STD_LOGIC_VECTOR(g_READ_LENGTH*8 - 1 downto 0);
end_read_flag_o : out STD_LOGIC;
spi_miso_o : out STD_LOGIC;
spi_clk_i : in STD_LOGIC
);
end spi_slave_writer;
architecture Behavioral of spi_slave_writer is
signal s_spi_count : NATURAL := 0;
signal s_SPI0 : r_SPI0;
signal s_SPI1 : r_SPI1;
signal s_STATUS : r_STATUS;
signal s_spi_clk : STD_LOGIC;
signal s_read : STD_LOGIC_VECTOR (g_READ_LENGTH*8 - 1 downto 0)
:= (others => '0');
signal s_bytes_writen : NATURAL;
signal s_end_read_flag : STD_LOGIC;
begin
s_SPI0 <= SPI0_i;
s_SPI1 <= SPI1_i;
s_spi_clk <= spi_clk_i;
s_read <= read_i;
s_STATUS <= STATUS_i;
end_read_flag_o <= s_end_read_flag;
p_spi_writer : process (spi_clk_i, rst_i) is
function write_on_rise (r_reg : r_SPI0) return STD_LOGIC is
variable v_return : STD_LOGIC;
begin
case r_reg.CPOL is
when '0' =>
if r_reg.CPHA = '0' then
v_return := '0';
else
v_return := '1';
end if;
when others =>
if r_reg.CPHA = '0' then
v_return := '1';
else
v_return := '0';
end if;
end case;
return v_return;
end function;
procedure write_bit is
begin
if s_STATUS.spi_clk_fsm = S5_READ then
s_bytes_writen <= s_bytes_writen + 1;
spi_miso_o <= s_read(r_SPI3'a_length - 1 - s_bytes_writen);
if s_bytes_writen = g_READ_LENGTH*8 - 1 then
s_end_read_flag <= '1';
end if;
else
spi_miso_o <= 'Z';
end if;
end procedure;
begin
if rst_i = '1' then
s_bytes_writen <= 0;
spi_miso_o <= 'Z';
s_end_read_flag <= '0';
else
if rising_edge(spi_clk_i)
and (write_on_rise(s_SPI0) = '1') then
write_bit;
elsif falling_edge(spi_clk_i)
and (write_on_rise(s_SPI0) = '0') then
write_bit;
end if;
end if;
end process p_spi_writer;
end;
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